When the clock speed is above about 4GHz, e.g. on modern PC hardware,
the timer overflows, resulting in a much lower frequency than expected.
Deal with this by capping the clock speed.
It would be possible to move to a 64-bit value for the clock, but that
is a pain to deal with. A better approach might be to express the clock
in MHz but that is left for later consideration.
Signed-off-by: Simon Glass <sjg@chromium.org>
When bootstage is used the timer can be inited before the CPU identity
is set up, resulting in the checks for the vendor not working.
Add a special call to work around this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add the driver for the AST2700 Ibex timer, which uses CPU
cycles as the timer count running at 200MHz.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The counter value read from TDR register may not be correct.
Read SECCNT and CNTR25M instead to get the correct timestamp.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Skip setting parent with dummy fixed-clock. Upstream linux might declare
an additional clock for the mtk timer and that additional clock might
also be a fixed-clock defined in DT. Setting parent of a dummy fixed-clock
resulta in error hence mtk timer fails to probe.
Skip setting parent to permit correct probe of the mtk timer.
Fixes: d3c3606c5c ("timer: MediaTek: add timer driver for MediaTek SoCs")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d, reversing
changes made to 2ee6f3a5f7.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
Greg Malysa <greg.malysa@timesys.com> says:
This series adds support for the ADI SC5xx machine type and includes two
core drivers that are required for being able to boot any board--a UART
driver, the gptimer driver which is used as a clock reference (CNTVCNT
is not supported on the armv7 sc5xx SoCs) and the clock tree driver. Our
corresponding Linux support relies on u-boot configuring the clocks
correctly before booting, so it is not possible to boot any board
without the CGU/CDU configuration happening here. There are also no
board files, device trees, or defconfigs included here, but some common
definitions that will be used to build board files currently are. The
sc5xx SoCs themselves include many armv7 families (sc57x, sc58x, and
sc594) all using an ARM Cortex-A5, and one armv8 family (sc598) indended
to be a drop-in replacement for the SC594 in terms of peripherals, with
a Cortex-A55 instead.
Some of the configuration code in dmcinit and clkinit is quite scary and
causes a lot of checkpatch violations. It is modified from code
initially provided by ADI, but it has not been fully rewritten. There's
a question of how important it is to clean up this code--it has some
quality violations, but it has been in use (including in production) for
over two years and is known to work for performing the low level SoC
initialization, while a rewrite might introduce timing or sequence bugs
that could take a significant amount of time to detect in the future.
In general terms, we -include include/linux/kconfig.h and so normal
U-Boot code does not need to also #include it. However, for code which
is shared with userspace we may need to add it so that either our full
config is available or so that macros such as CONFIG_IS_ENABLED() can be
evaluated. In this case make sure that we guard these includes with a
test for USE_HOSTCC so that it clear as to why we're doing this.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Add timer driver in Starfive SoC. It is an timer that outside
of CPU core and inside Starfive SoC.
Signed-off-by: Kuan Lim Lee <kuanlim.lee@starfivetech.com>
Signed-off-by: Wei Liang Lim <weiliang.lim@starfivetech.com>
Changes for v2:
- correct driver name, comment, variable
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Currently the "clock-frequency" DT property is only being considered as an
fallback if either there is no clock driver, the clock driver implements
the request-op correctly or there is no clock defined for the timer at all.
This patch makes "clock-frequency" also being picked as a fallback if
getting the clock-rate fails, since clk_get(_by_index) will return no
error, if a clock driver does not implement the request-op and does also
not support getting the rate of the clock in question.
timer_post_probe will take care if the property does not exist in the DT or
is defined as 0.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
The Andes PLMT driver directly accesses the mtime MMIO region,
indicating its intended use in the M-mode boot stage. However,
since U-Boot proper (S-mode) also uses the PLMT driver, we need
to specifically mark the region as readable through PMPCFGx (or
S/U-mode read-only shared data region for Smepmp) in OpenSBI.
Granting permission for this case doesn't make sense. Instead,
we should use the generic RISC-V timer driver to read the mtime
through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER
config, which ensures that the PLMT driver is linked exclusively
against M-mode U-Boot or U-Boot SPL binaries.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Add timer driver in Starfive SoC. It is an timer that outside
of CPU core and inside Starfive SoC.
Signed-off-by: Kuan Lim Lee <kuanlim.lee@starfivetech.com>
Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
timer_get_boot_us function is required to record the boot stages as
us-based timestamp.
To get a micro-second time from a timer tick, this converts the
formula like below to avoid zero result of (tick / rate) part.
From: time(us) = (tick / rate) * 1000000
To : time(us) = (tick * 1000) / (rate / 1000)
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
timer_get_boot_us function is required to record the boot stages as
us-based timestamp.
To get a micro-second time from a timer tick, this converts the
formula like below to avoid zero result of (tick / rate) part.
From: time(us) = (tick / rate) * 1000000
To : time(us) = (tick * 1000) / (rate / 1000)
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The last user of the NEEDS_MANUAL_RELOC has been removed in commit
26af162ac8 ("arch: m68k: Implement relocation")
Remove now unused NEEDS_MANUAL_RELOC code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
For the architectural timer on riscv, there already is a defined
device tree binding[1]. Allow timer instances to be created from
device tree matches, but for now retain the old mechanism, which
registers the timer biggy-back with the CPU.
[1] linux/Documentation/devicetree/bindings/timer/riscv,timer.yaml
Signed-off-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The TI AM654 timer is compatible with the omap-timer implementation,
so add it to the compatible id list.
Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Cc: Francesco Dolcini <francesco@dolcini.it>
Cc: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Nishanth Menon <nm@ti.com>
As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.
The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint timer driver to
support ACLINT mtimer device, using a per-driver data field to hold
the mtimer offset to the base address encoded in the mtimer node.
[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use a regs variable with uintptr_t size in the
dw-apb-timer.c file.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In the binding for the Rockchip timer the compatible string
consists of a SoC orientated string and a fall back string
"rockchip,rk3288-timer", so remove all unneeded ones and
fix driver name.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
It is not yet clear how to read the timer via EFI. The current value seems
much too high on a Framework laptop I tried. Adjust it to a lower
hard-coded value for now.
Signed-off-by: Simon Glass <sjg@chromium.org>
The fttmr010 timer driver was deleted by
commit 29fc6f2492 ("ARM: remove a320evb board support")
The original source file was: arch/arm/cpu/arm920t/a320/timer.c
Return the driver to the codebase in a DM compatible form.
A platform using fttmr010 will be submitted later.
This hardware is described in the datasheet [1], starting from page 348.
According to the datasheet, there is a Revision Register at offset 0x3C,
which is not present in 'struct fttmr010'. Add it and debug() print
revision in probe function.
[1]
https://bitbucket.org/Kasreyn/mkrom-uc7112lx/src/master/documents/FIC8120_DS_v1.2.pdf
Signed-off-by: Sergei Antonov <saproj@gmail.com>
Building sandbox_defconfig with CONFIG_SPL_TIMER=y results in an error
include/dm/platdata.h:63:33: error: static assertion failed:
"Cannot use U_BOOT_DRVINFO with of-platdata.
Please use devicetree instead"
Add a missing condition in the sandbox driver.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tracing is typically enabled by the time driver model starts up, so there
is no point in adding a 'notrace' to the timer-init function. However,
once the driver model timer is enabled, we do need to be able to access
the timer's private data when reading the timer, so add it to the core
function needed for that.
Update the function's documentation while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add timer support for T20/T30/T114/T124 and T210 based devices.
Driver is based on DM, has device tree support and can be
used on SPL and early boot stage.
Arm64 Tegra (apart T210) according to comment in tegra-common.h use
architected timer.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks. Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It was noticed that Clearfog is currently broken with this newly
introduced early_init_done() function. Apparently the timer is enabled
here when U-Boot is run but not configured - at least not correctly.
Resulting in a hangup in the timer reading functions.
To fix this, also read the value of the reload register and check it's
value with the one written to by U-Boot. Only if this matches, the
init has already been done.
Fixes: 5387b093cb ("timer: orion-timer: Fix problem with early static variable")
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Pali Rohár <pali@kernel.org>
Cc: Martin Rowe <martin.p.rowe@gmail.com>
Cc: Tony Dinh <mibodhi@gmail.com>
Cc: Pali Rohár <pali@kernel.org>
Cc: Michael Walle <michael@walle.cc>
We've noticed that at least one Kirkwood board (Pogo v4) has problems
with the new orion DM timer implementation. Debugging revealed that this
issue is related with the static variable "early_init_done" which does
not work correctly before relocation in all cases.
This patch removes this static variable and replaces it's functionality
via a function that detects if the timer is already initialized.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pali Rohár <pali@kernel.org>
Cc: Michael Walle <michael@walle.cc>
Cc: Tony Dinh <mibodhi@gmail.com>
Tested-by: Tony Dinh <mibodhi@gmail.com>
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Current xilinx_timer_get_count() implementation does not take into account
the periodic 32-bit wrap arounds, as it directly returns the 32-bit counter
register value. The roll-overs cause problems in the upper timer layers, as
generic timer code expects an incrementing 64-bit value from get_count() to
work correctly.
Add the missing 64-bit up-conversion to fix random hangs/delays in
__udelay().
Fixes: a36d86720f ("microblaze: Convert axi timer to DM driver")
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221012053656.1492457-3-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Relocate timer_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled.
The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done
logic works for drivers that use DM_FLAG_PRE_RELOC.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20221012053656.1492457-2-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Align timer uclass with the other subsystems and provide a timer_get_ops()
convenience macro.
Using this instead of the generic device_get_ops() also prevents
-Wdiscarded-qualifiers warnings when used with non-const variables.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20221012053656.1492457-1-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
The "Arm Ltd. Dual-Timer Module (SP804)" is a simple 32-bit count-down
timer IP with interrupt functionality, and is used in some SoCs from
various vendors.
Add a simple DM compliant timer driver, to allow users of the SP804 to
switch to DM_TIMER.
This relies on the input clock to be accessible via the DM clock
framework, which should be fine as we probably look at fixed-clock's
here anyway.
We re-program the control register in the probe() function, but keep
the divider in place, in case this has been set to something on purpose
before.
The TRM for the timer IP can be found here:
https://developer.arm.com/documentation/ddi0271/latest
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
STI timer is actually ARM Cortex A9 global timer. Convert the driver to
use generic global timer name and make it consistent with Linux kernel
global timer driver. This also allows any A9 based device to use this
driver.
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Move the code making sure that the timer is initialized only once into
orion_timer_init(), which is called from timer_early_init() and from
orion_timer_probe(). This way the timer is not re-initialized.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Michael Walle <michael@walle.cc>
Cc: Pali Rohár <pali@kernel.org>
This patch add general-purpose timer support for MediaTek MT7981/MT7986.
These two SoCs uses a newer version of timer with its register definition
slightly changed.
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
