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u-boot/arch/arm/cpu/armv8/fsl-layerscape/cpu.c

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
/*
Layerscape: Enable Job ring driver model. LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162 platforms are enabled with JR driver model. removed sec_init() call from board files. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc>
2022-03-24 06:20:35 +00:00
* Copyright 2017-2021 NXP
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
* Copyright 2014-2015 Freescale Semiconductor, Inc.
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
*/
#include <common.h>
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-14 18:36:40 +00:00
#include <clock_legacy.h>
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-14 19:57:32 +00:00
#include <cpu_func.h>
env: Move env_get_f() to env.h Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-01 15:46:42 +00:00
#include <env.h>
common: Move RAM-sizing functions to init.h These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org>
2019-12-28 17:45:05 +00:00
#include <init.h>
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-28 17:45:07 +00:00
#include <hang.h>
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:05 +00:00
#include <log.h>
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:39:56 +00:00
#include <net.h>
Move strtomhz() to vsprintf.h At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-14 19:57:20 +00:00
#include <vsprintf.h>
common: Drop net.h from common header Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:39:56 +00:00
#include <asm/cache.h>
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-31 03:38:53 +00:00
#include <asm/global_data.h>
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
#include <asm/io.h>
common: Drop asm/ptrace.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:06 +00:00
#include <asm/ptrace.h>
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-04-22 09:23:27 +00:00
#include <linux/arm-smccc.h>
treewide: replace #include <asm/errno.h> with <linux/errno.h> Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-21 02:28:55 +00:00
#include <linux/errno.h>
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
#include <asm/system.h>
arm: Prevent redefinition error in fsl-layerscape The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-16 20:33:51 +00:00
#include <fm_eth.h>
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
#include <asm/armv8/mmu.h>
#include <asm/io.h>
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <asm/arch/cpu.h>
#include <asm/arch/speed.h>
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-11 05:39:14 +00:00
#include <fsl_immap.h>
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
#include <asm/arch/mp.h>
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-17 00:03:01 +00:00
#include <efi_loader.h>
drivers/mc: Migrated MC Flibs to 0.5.2 Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree from "fsl,dprcr" to "fsl-mc". Print MC version info when appropriate. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-06 21:19:02 +00:00
#include <fsl-mc/fsl_mc.h>
ls2085a: esdhc: Add esdhc support for ls2085a This patch adds esdhc support for ls2085a. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-03-21 02:28:31 +00:00
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28 12:18:15 +00:00
#include <asm/armv8/sec_firmware.h>
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21 03:36:48 +00:00
#ifdef CONFIG_SYS_FSL_DDR
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-02-25 16:19:53 +00:00
#include <fsl_ddr_sdram.h>
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21 03:36:48 +00:00
#include <fsl_ddr.h>
#endif
common: freescale: Move arch-specific declarations The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-17 14:23:06 +00:00
#include <asm/arch/clock.h>
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-10 06:02:52 +00:00
#include <hwconfig.h>
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-15 21:01:00 +00:00
#include <fsl_qbman.h>
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:42 +00:00
#ifdef CONFIG_TFABOOT
env: Rename environment.h to env_internal.h This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-02 15:44:25 +00:00
#include <env_internal.h>
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:52 +00:00
#ifdef CONFIG_CHAIN_OF_TRUST
#include <fsl_validate.h>
#endif
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:42 +00:00
#endif
common: Move mii_init() function out of common.h This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-14 19:57:31 +00:00
#include <linux/mii.h>
Layerscape: Enable Job ring driver model. LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162 platforms are enabled with JR driver model. removed sec_init() call from board files. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc>
2022-03-24 06:20:35 +00:00
#include <dm.h>
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:42 +00:00
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
DECLARE_GLOBAL_DATA_PTR;
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-20 06:31:17 +00:00
CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
armv8: ls1043a: add SVR definitions for 23x23 package silicon LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-20 06:31:17 +00:00
CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-18 08:50:52 +00:00
CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-04-10 08:43:33 +00:00
CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:17:09 +00:00
CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-29 13:46:16 +00:00
CPU_TYPE_ENTRY(LX2162A, LX2162A, 16),
CPU_TYPE_ENTRY(LX2122A, LX2122A, 12),
CPU_TYPE_ENTRY(LX2082A, LX2082A, 8),
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
};
#define EARLY_PGTABLE_SIZE 0x5000
static struct mm_region early_map[] = {
#ifdef CONFIG_FSL_LSCH3
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
CFG_SYS_FSL_CCSR_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
{ CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
CFG_SYS_FSL_QSPI_SIZE1,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
#ifdef CONFIG_FSL_IFC
/* For IFC Region #1, only the first 4MB is cache-enabled */
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_IFC_BASE1, CFG_SYS_FSL_IFC_BASE1,
CFG_SYS_FSL_IFC_SIZE1_1,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_IFC_BASE1 + CFG_SYS_FSL_IFC_SIZE1_1,
CFG_SYS_FSL_IFC_BASE1 + CFG_SYS_FSL_IFC_SIZE1_1,
CFG_SYS_FSL_IFC_SIZE1 - CFG_SYS_FSL_IFC_SIZE1_1,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FLASH_BASE, CFG_SYS_FSL_IFC_BASE1,
CFG_SYS_FSL_IFC_SIZE1,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#endif
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
CFG_SYS_FSL_DRAM_SIZE1,
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2018-11-05 18:01:37 +00:00
#if defined(CONFIG_TFABOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
#endif
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#ifdef CONFIG_FSL_IFC
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
/* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_IFC_BASE2, CFG_SYS_FSL_IFC_BASE2,
CFG_SYS_FLASH_BASE - CFG_SYS_FSL_IFC_BASE2,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#endif
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
CFG_SYS_FSL_DCSR_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
CFG_SYS_FSL_DRAM_SIZE2,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
#ifdef CFG_SYS_FSL_DRAM_BASE3
{ CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3,
CFG_SYS_FSL_DRAM_SIZE3,
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:11:29 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#endif
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
#elif defined(CONFIG_FSL_LSCH2)
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
CFG_SYS_FSL_CCSR_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
CFG_SYS_FSL_DCSR_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
{ CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
CFG_SYS_FSL_QSPI_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#ifdef CONFIG_FSL_IFC
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_IFC_BASE, CFG_SYS_FSL_IFC_BASE,
CFG_SYS_FSL_IFC_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#endif
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
CFG_SYS_FSL_DRAM_SIZE1,
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2018-11-05 18:01:37 +00:00
#if defined(CONFIG_TFABOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
#endif
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
CFG_SYS_FSL_DRAM_SIZE2,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#endif
{}, /* list terminator */
};
static struct mm_region final_map[] = {
#ifdef CONFIG_FSL_LSCH3
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
CFG_SYS_FSL_CCSR_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
CFG_SYS_FSL_DRAM_SIZE1,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
{ CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
CFG_SYS_FSL_QSPI_SIZE1,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
{ CFG_SYS_FSL_QSPI_BASE2, CFG_SYS_FSL_QSPI_BASE2,
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
CFG_SYS_FSL_QSPI_SIZE2,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#ifdef CONFIG_FSL_IFC
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_IFC_BASE2, CFG_SYS_FSL_IFC_BASE2,
CFG_SYS_FSL_IFC_SIZE2,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#endif
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
CFG_SYS_FSL_DCSR_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_MC_BASE, CFG_SYS_FSL_MC_BASE,
CFG_SYS_FSL_MC_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_NI_BASE, CFG_SYS_FSL_NI_BASE,
CFG_SYS_FSL_NI_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
/* For QBMAN portal, only the first 64MB is cache-enabled */
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_QBMAN_BASE, CFG_SYS_FSL_QBMAN_BASE,
CFG_SYS_FSL_QBMAN_SIZE_1,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_QBMAN_BASE + CFG_SYS_FSL_QBMAN_SIZE_1,
CFG_SYS_FSL_QBMAN_BASE + CFG_SYS_FSL_QBMAN_SIZE_1,
CFG_SYS_FSL_QBMAN_SIZE - CFG_SYS_FSL_QBMAN_SIZE_1,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:33 +00:00
{ CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
CFG_SYS_PCIE1_PHYS_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:33 +00:00
{ CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
CFG_SYS_PCIE2_PHYS_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:33 +00:00
#ifdef CFG_SYS_PCIE3_PHYS_ADDR
{ CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
CFG_SYS_PCIE3_PHYS_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-04-10 08:43:33 +00:00
#endif
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:33 +00:00
#ifdef CFG_SYS_PCIE4_PHYS_ADDR
{ CFG_SYS_PCIE4_PHYS_ADDR, CFG_SYS_PCIE4_PHYS_ADDR,
CFG_SYS_PCIE4_PHYS_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
armv8: lx2160a: add MMU table entries for PCIe The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-04-08 10:15:41 +00:00
#endif
#ifdef SYS_PCIE5_PHYS_ADDR
{ SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
SYS_PCIE5_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#endif
#ifdef SYS_PCIE6_PHYS_ADDR
{ SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
SYS_PCIE6_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
#endif
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_WRIOP1_BASE, CFG_SYS_FSL_WRIOP1_BASE,
CFG_SYS_FSL_WRIOP1_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_AIOP1_BASE, CFG_SYS_FSL_AIOP1_BASE,
CFG_SYS_FSL_AIOP1_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_PEBUF_BASE, CFG_SYS_FSL_PEBUF_BASE,
CFG_SYS_FSL_PEBUF_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
CFG_SYS_FSL_DRAM_SIZE2,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
#ifdef CFG_SYS_FSL_DRAM_BASE3
{ CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3,
CFG_SYS_FSL_DRAM_SIZE3,
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:11:29 +00:00
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#endif
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
#elif defined(CONFIG_FSL_LSCH2)
{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
CONFIG_SYS_FSL_BOOTROM_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
CFG_SYS_FSL_CCSR_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
CFG_SYS_FSL_DCSR_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
{ CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
CFG_SYS_FSL_QSPI_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#ifdef CONFIG_FSL_IFC
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_IFC_BASE, CFG_SYS_FSL_IFC_BASE,
CFG_SYS_FSL_IFC_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#endif
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
CFG_SYS_FSL_DRAM_SIZE1,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_QBMAN_BASE, CFG_SYS_FSL_QBMAN_BASE,
CFG_SYS_FSL_QBMAN_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
CFG_SYS_FSL_DRAM_SIZE2,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:33 +00:00
{ CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
CFG_SYS_PCIE1_PHYS_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:33 +00:00
{ CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
CFG_SYS_PCIE2_PHYS_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:33 +00:00
#ifdef CFG_SYS_PCIE3_PHYS_ADDR
{ CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
CFG_SYS_PCIE3_PHYS_SIZE,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-04-10 08:43:33 +00:00
#endif
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
{ CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3,
CFG_SYS_FSL_DRAM_SIZE3,
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#endif
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
#ifdef CFG_SYS_MEM_RESERVE_SECURE
move data structure out of cpu.h Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:06 +00:00
{}, /* space holder for secure mem */
#endif
{},
};
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:23 +00:00
struct mm_region *mem_map = early_map;
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-04 00:09:54 +00:00
armv8/fsl-ch3: Add support to print SoC personality This patch adds support to print out the SoC personality. Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-28 09:24:06 +00:00
void cpu_name(char *name)
{
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
armv8/fsl-ch3: Add support to print SoC personality This patch adds support to print out the SoC personality. Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-28 09:24:06 +00:00
unsigned int i, svr, ver;
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
svr = gur_in32(&gur->svr);
armv8/fsl-ch3: Add support to print SoC personality This patch adds support to print out the SoC personality. Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-28 09:24:06 +00:00
ver = SVR_SOC_VER(svr);
for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
strcpy(name, cpu_type_list[i].name);
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-29 13:46:16 +00:00
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:17:09 +00:00
if (IS_C_PROCESSOR(svr))
strcat(name, "C");
#endif
armv8/fsl-ch3: Add support to print SoC personality This patch adds support to print out the SoC personality. Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-28 09:24:06 +00:00
if (IS_E_PROCESSOR(svr))
strcat(name, "E");
armv8/fsl-layerscape: print SoC revsion number The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-13 08:13:54 +00:00
sprintf(name + strlen(name), " Rev%d.%d",
SVR_MAJ(svr), SVR_MIN(svr));
armv8/fsl-ch3: Add support to print SoC personality This patch adds support to print out the SoC personality. Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-28 09:24:06 +00:00
break;
}
if (i == ARRAY_SIZE(cpu_type_list))
strcpy(name, "unknown");
}
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-05-03 13:41:00 +00:00
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
armv8: fsl-lsch3: Rewrite MMU translation table entries This patch rewrites MMU translation table entries. To start, all table entries are written as "invalid", then "device-ngnrnr" and "normal" are written to the entries to enable access to specific addresses. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-08-18 03:22:05 +00:00
/*
* To start MMU before DDR is available, we create MMU table in SRAM.
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
* The base address of SRAM is CFG_SYS_FSL_OCRAM_BASE. We use three
armv8: fsl-lsch3: Rewrite MMU translation table entries This patch rewrites MMU translation table entries. To start, all table entries are written as "invalid", then "device-ngnrnr" and "normal" are written to the entries to enable access to specific addresses. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-08-18 03:22:05 +00:00
* levels of translation tables here to cover 40-bit address space.
* We use 4KB granule size, with 40 bits physical address, T0SZ=24
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:23 +00:00
* Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
* Note, the debug print in cache_v8.c is not usable for debugging
* these early MMU tables because UART is not yet available.
armv8: fsl-lsch3: Rewrite MMU translation table entries This patch rewrites MMU translation table entries. To start, all table entries are written as "invalid", then "device-ngnrnr" and "normal" are written to the entries to enable access to specific addresses. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-08-18 03:22:05 +00:00
*/
static inline void early_mmu_setup(void)
{
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:23 +00:00
unsigned int el = current_el();
armv8: fsl-lsch3: Rewrite MMU translation table entries This patch rewrites MMU translation table entries. To start, all table entries are written as "invalid", then "device-ngnrnr" and "normal" are written to the entries to enable access to specific addresses. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-08-18 03:22:05 +00:00
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:23 +00:00
/* global data is already setup, no allocation yet */
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:28 +00:00
if (el == 3)
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE;
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:28 +00:00
else
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
gd->arch.tlb_addr = CFG_SYS_DDR_SDRAM_BASE;
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:23 +00:00
gd->arch.tlb_fillptr = gd->arch.tlb_addr;
gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
armv8: fsl-lsch3: Rewrite MMU translation table entries This patch rewrites MMU translation table entries. To start, all table entries are written as "invalid", then "device-ngnrnr" and "normal" are written to the entries to enable access to specific addresses. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-08-18 03:22:05 +00:00
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:23 +00:00
/* Create early page tables */
setup_pgtables();
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:23 +00:00
/* point TTBR to the new table */
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
armv8: always use current exception level for TCR_ELx access Currently get_tcr() takes an "el" parameter, to select the proper version of the TCR_ELx system register. This is problematic in case of the Apple M1, since it runs with HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout, and we get the wrong version. For U-Boot's purposes the only sensible choice here is the current exception level, and indeed most callers treat it like that, so let's remove that parameter and read the current EL inside the function. This allows us to check for the E2H bit, and pretend it's EL1 in this case. There are two callers which don't care about the EL, and they pass 0, which looks wrong, but is irrelevant in these two cases, since we don't use the return value there. So the change cannot affect those two. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Tested-by: Mark Kettenis <kettenis@openbsd.org>
2022-06-13 23:11:10 +00:00
get_tcr(NULL, NULL) &
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:23 +00:00
~(TCR_ORGN_MASK | TCR_IRGN_MASK),
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
MEMORY_ATTRIBUTES);
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-04 19:57:08 +00:00
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:23 +00:00
set_sctlr(get_sctlr() | CR_M);
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-04 19:57:08 +00:00
}
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-03 04:35:09 +00:00
static void fix_pcie_mmu_map(void)
{
armv8: ls2080a: Drop macro CONFIG_LS2080A Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-27 18:41:01 +00:00
#ifdef CONFIG_ARCH_LS2080A
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-03 04:35:09 +00:00
unsigned int i;
u32 svr, ver;
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-03 04:35:09 +00:00
svr = gur_in32(&gur->svr);
ver = SVR_SOC_VER(svr);
/* Fix PCIE base and size for LS2088A */
if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-27 09:38:06 +00:00
(ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
(ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-03 04:35:09 +00:00
for (i = 0; i < ARRAY_SIZE(final_map); i++) {
switch (final_map[i].phys) {
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:33 +00:00
case CFG_SYS_PCIE1_PHYS_ADDR:
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-03 04:35:09 +00:00
final_map[i].phys = 0x2000000000ULL;
final_map[i].virt = 0x2000000000ULL;
final_map[i].size = 0x800000000ULL;
break;
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:33 +00:00
case CFG_SYS_PCIE2_PHYS_ADDR:
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-03 04:35:09 +00:00
final_map[i].phys = 0x2800000000ULL;
final_map[i].virt = 0x2800000000ULL;
final_map[i].size = 0x800000000ULL;
break;
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:33 +00:00
#ifdef CFG_SYS_PCIE3_PHYS_ADDR
case CFG_SYS_PCIE3_PHYS_ADDR:
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-03 04:35:09 +00:00
final_map[i].phys = 0x3000000000ULL;
final_map[i].virt = 0x3000000000ULL;
final_map[i].size = 0x800000000ULL;
break;
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-04-10 08:43:33 +00:00
#endif
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:33 +00:00
#ifdef CFG_SYS_PCIE4_PHYS_ADDR
case CFG_SYS_PCIE4_PHYS_ADDR:
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-03 04:35:09 +00:00
final_map[i].phys = 0x3800000000ULL;
final_map[i].virt = 0x3800000000ULL;
final_map[i].size = 0x800000000ULL;
break;
armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-04-08 10:15:32 +00:00
#endif
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-03 04:35:09 +00:00
default:
break;
}
}
}
#endif
}
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
/*
armv8: fsl-lsch3: Rewrite MMU translation table entries This patch rewrites MMU translation table entries. To start, all table entries are written as "invalid", then "device-ngnrnr" and "normal" are written to the entries to enable access to specific addresses. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-08-18 03:22:05 +00:00
* The final tables look similar to early tables, but different in detail.
* These tables are in DRAM. Sub tables are added to enable cache for
* QBMan and OCRAM.
*
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:18 +00:00
* Put the MMU table in secure memory if gd->arch.secure_ram is valid.
* OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
*/
static inline void final_mmu_setup(void)
{
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:23 +00:00
u64 tlb_addr_save = gd->arch.tlb_addr;
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-04 19:57:08 +00:00
unsigned int el = current_el();
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:23 +00:00
int index;
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
pci: layerscape: add LS2088A series SoC pcie support The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-03 04:35:09 +00:00
/* fix the final_map before filling in the block entries */
fix_pcie_mmu_map();
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:23 +00:00
mem_map = final_map;
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:30 +00:00
/* Update mapping for DDR to actual size */
for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
/*
* Find the entry for DDR mapping and update the address and
* size. Zero-sized mapping will be skipped when creating MMU
* table.
*/
switch (final_map[index].virt) {
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
case CFG_SYS_FSL_DRAM_BASE1:
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:30 +00:00
final_map[index].virt = gd->bd->bi_dram[0].start;
final_map[index].phys = gd->bd->bi_dram[0].start;
final_map[index].size = gd->bd->bi_dram[0].size;
break;
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
#ifdef CFG_SYS_FSL_DRAM_BASE2
case CFG_SYS_FSL_DRAM_BASE2:
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:30 +00:00
#if (CONFIG_NR_DRAM_BANKS >= 2)
final_map[index].virt = gd->bd->bi_dram[1].start;
final_map[index].phys = gd->bd->bi_dram[1].start;
final_map[index].size = gd->bd->bi_dram[1].size;
#else
final_map[index].size = 0;
#endif
break;
#endif
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
#ifdef CFG_SYS_FSL_DRAM_BASE3
case CFG_SYS_FSL_DRAM_BASE3:
armv8: layerscape: Update MMU mapping with actual DDR size Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:30 +00:00
#if (CONFIG_NR_DRAM_BANKS >= 3)
final_map[index].virt = gd->bd->bi_dram[2].start;
final_map[index].phys = gd->bd->bi_dram[2].start;
final_map[index].size = gd->bd->bi_dram[2].size;
#else
final_map[index].size = 0;
#endif
break;
#endif
default:
break;
}
}
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
#ifdef CFG_SYS_MEM_RESERVE_SECURE
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:23 +00:00
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
if (el == 3) {
/*
* Only use gd->arch.secure_ram if the address is
* recalculated. Align to 4KB for MMU table.
*/
/* put page tables in secure ram */
index = ARRAY_SIZE(final_map) - 2;
gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
final_map[index].virt = gd->arch.secure_ram & ~0x3;
final_map[index].phys = final_map[index].virt;
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
final_map[index].size = CFG_SYS_MEM_RESERVE_SECURE;
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:23 +00:00
final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
armv8: Move secure_ram variable out of generic global data Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:18 +00:00
gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:23 +00:00
tlb_addr_save = gd->arch.tlb_addr;
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-04 19:57:08 +00:00
} else {
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:23 +00:00
/* Use allocated (board_f.c) memory for TLB */
tlb_addr_save = gd->arch.tlb_allocated;
gd->arch.tlb_addr = tlb_addr_save;
armv8: fsl-layerscape: Make DDR non secure in MMU tables DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-04 19:57:08 +00:00
}
}
#endif
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
armv8: layerscape: Convert to use common MMU framework Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-24 23:46:23 +00:00
/* Reset the fill ptr */
gd->arch.tlb_fillptr = tlb_addr_save;
/* Create normal system page tables */
setup_pgtables();
/* Create emergency page tables */
gd->arch.tlb_addr = gd->arch.tlb_fillptr;
gd->arch.tlb_emerg = gd->arch.tlb_addr;
setup_pgtables();
gd->arch.tlb_addr = tlb_addr_save;
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:31 +00:00
/* Disable cache and MMU */
dcache_disable(); /* TLBs are invalidated */
invalidate_icache_all();
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
/* point TTBR to the new table */
armv8: always use current exception level for TCR_ELx access Currently get_tcr() takes an "el" parameter, to select the proper version of the TCR_ELx system register. This is problematic in case of the Apple M1, since it runs with HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout, and we get the wrong version. For U-Boot's purposes the only sensible choice here is the current exception level, and indeed most callers treat it like that, so let's remove that parameter and read the current EL inside the function. This allows us to check for the E2H bit, and pretend it's EL1 in this case. There are two callers which don't care about the EL, and they pass 0, which looks wrong, but is irrelevant in these two cases, since we don't use the return value there. So the change cannot affect those two. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Tested-by: Mark Kettenis <kettenis@openbsd.org>
2022-06-13 23:11:10 +00:00
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup. When final MMU table is setup in DDR, TCR attributes must match those of the memroy for cacheability and shareability. Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-06-29 07:50:42 +00:00
MEMORY_ATTRIBUTES);
armv8: layerscape: Fix the sequence of changing MMU table This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:31 +00:00
armv8: fsl-layerscape: mmu: Fix enabling MMU MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com>
2016-07-22 17:52:23 +00:00
set_sctlr(get_sctlr() | CR_M);
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
}
arm64: Fix layerscape mmu setup With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 19:26:12 +00:00
u64 get_page_table_size(void)
{
return 0x10000;
}
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
int arch_cpu_init(void)
{
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com>
2017-05-15 15:51:59 +00:00
/*
* This function is called before U-Boot relocates itself to speed up
* on system running. It is not necessary to run if performance is not
* critical. Skip if MMU is already enabled by SPL or other means.
*/
if (get_sctlr() & CR_M)
return 0;
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
icache_enable();
__asm_invalidate_dcache_all();
__asm_invalidate_tlb_all();
early_mmu_setup();
set_sctlr(get_sctlr() | CR_C);
return 0;
}
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28 12:18:12 +00:00
void mmu_setup(void)
{
final_mmu_setup();
}
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
/*
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28 12:18:12 +00:00
* This function is called from common/board_r.c.
* It recreates MMU table in main memory.
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
*/
void enable_caches(void)
{
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28 12:18:12 +00:00
mmu_setup();
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
__asm_invalidate_tlb_all();
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28 12:18:12 +00:00
icache_enable();
dcache_enable();
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
}
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-05-03 13:41:00 +00:00
#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:42 +00:00
#ifdef CONFIG_TFABOOT
enum boot_src __get_boot_src(u32 porsr1)
{
enum boot_src src = BOOT_SOURCE_RESERVED;
u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:11:29 +00:00
#if !defined(CONFIG_NXP_LSCH3_2)
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:42 +00:00
u32 val;
#endif
debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
#if defined(CONFIG_FSL_LSCH3)
armv8:fsl-layerscape: Add support for Chassis 3.2 NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:11:29 +00:00
#if defined(CONFIG_NXP_LSCH3_2)
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:42 +00:00
switch (rcw_src) {
case RCW_SRC_SDHC1_VAL:
src = BOOT_SOURCE_SD_MMC;
break;
case RCW_SRC_SDHC2_VAL:
src = BOOT_SOURCE_SD_MMC2;
break;
case RCW_SRC_I2C1_VAL:
src = BOOT_SOURCE_I2C1_EXTENDED;
break;
case RCW_SRC_FLEXSPI_NAND2K_VAL:
src = BOOT_SOURCE_XSPI_NAND;
break;
case RCW_SRC_FLEXSPI_NAND4K_VAL:
src = BOOT_SOURCE_XSPI_NAND;
break;
case RCW_SRC_RESERVED_1_VAL:
src = BOOT_SOURCE_RESERVED;
break;
case RCW_SRC_FLEXSPI_NOR_24B:
src = BOOT_SOURCE_XSPI_NOR;
break;
default:
src = BOOT_SOURCE_RESERVED;
}
#else
val = rcw_src & RCW_SRC_TYPE_MASK;
if (val == RCW_SRC_NOR_VAL) {
val = rcw_src & NOR_TYPE_MASK;
switch (val) {
case NOR_16B_VAL:
case NOR_32B_VAL:
src = BOOT_SOURCE_IFC_NOR;
break;
default:
src = BOOT_SOURCE_RESERVED;
}
} else {
/* RCW SRC Serial Flash */
val = rcw_src & RCW_SRC_SERIAL_MASK;
switch (val) {
case RCW_SRC_QSPI_VAL:
/* RCW SRC Serial NOR (QSPI) */
src = BOOT_SOURCE_QSPI_NOR;
break;
case RCW_SRC_SD_CARD_VAL:
/* RCW SRC SD Card */
src = BOOT_SOURCE_SD_MMC;
break;
case RCW_SRC_EMMC_VAL:
/* RCW SRC EMMC */
armv8: fsl-layerscape: fixes for TFABOOT framework Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-27 04:37:49 +00:00
src = BOOT_SOURCE_SD_MMC;
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:42 +00:00
break;
case RCW_SRC_I2C1_VAL:
/* RCW SRC I2C1 Extended */
src = BOOT_SOURCE_I2C1_EXTENDED;
break;
default:
src = BOOT_SOURCE_RESERVED;
}
}
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
#endif
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:42 +00:00
#elif defined(CONFIG_FSL_LSCH2)
/* RCW SRC NAND */
val = rcw_src & RCW_SRC_NAND_MASK;
if (val == RCW_SRC_NAND_VAL) {
val = rcw_src & NAND_RESERVED_MASK;
if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
src = BOOT_SOURCE_IFC_NAND;
} else {
/* RCW SRC NOR */
val = rcw_src & RCW_SRC_NOR_MASK;
if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
src = BOOT_SOURCE_IFC_NOR;
} else {
switch (rcw_src) {
case QSPI_VAL1:
case QSPI_VAL2:
src = BOOT_SOURCE_QSPI_NOR;
break;
case SD_VAL:
src = BOOT_SOURCE_SD_MMC;
break;
default:
src = BOOT_SOURCE_RESERVED;
}
}
}
#endif
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:02:09 +00:00
if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
src = BOOT_SOURCE_QSPI_NOR;
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:42 +00:00
debug("%s: src 0x%x\n", __func__, src);
return src;
}
enum boot_src get_boot_src(void)
{
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-04-22 09:23:27 +00:00
struct arm_smccc_res res;
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:02:09 +00:00
u32 porsr1 = 0;
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:42 +00:00
#if defined(CONFIG_FSL_LSCH3)
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
#elif defined(CONFIG_FSL_LSCH2)
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:02:09 +00:00
#endif
if (current_el() == 2) {
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-04-22 09:23:27 +00:00
arm_smccc_smc(SIP_SVC_RCW, 0, 0, 0, 0, 0, 0, 0, &res);
if (!res.a0)
porsr1 = res.a1;
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:02:09 +00:00
}
if (current_el() == 3 || !porsr1) {
#ifdef CONFIG_FSL_LSCH3
porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
#elif defined(CONFIG_FSL_LSCH2)
porsr1 = in_be32(&gur->porsr1);
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:42 +00:00
#endif
armv8: fsl-layerscape: Update parsing boot source Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com>
2018-11-05 18:02:09 +00:00
}
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:42 +00:00
debug("%s: porsr1 0x%x\n", __func__, porsr1);
return __get_boot_src(porsr1);
}
#ifdef CONFIG_ENV_IS_IN_MMC
int mmc_get_env_dev(void)
{
enum boot_src src = get_boot_src();
int dev = CONFIG_SYS_MMC_ENV_DEV;
switch (src) {
case BOOT_SOURCE_SD_MMC:
dev = 0;
break;
case BOOT_SOURCE_SD_MMC2:
dev = 1;
break;
default:
break;
}
return dev;
}
#endif
armv8: layerscape: env: Switch to arch_env_get_location() Implement arch_env_get_location() instead of env_get_location(), so that the env_get_location() can be implemented on board level and override the arch_env_get_location() architecture defaults. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Adam Ford <aford173@gmail.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Behún <marek.behun@nic.cz> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Vladimir Oltean <vladimir.oltean@nxp.com>
2022-04-06 00:21:33 +00:00
enum env_location arch_env_get_location(enum env_operation op, int prio)
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:42 +00:00
{
enum boot_src src = get_boot_src();
enum env_location env_loc = ENVL_NOWHERE;
if (prio)
return ENVL_UNKNOWN;
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE. ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-04-23 06:06:04 +00:00
#ifdef CONFIG_ENV_IS_NOWHERE
return env_loc;
armv8: fsl-layerscape: bootcmd identification for TFABOOT Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:52 +00:00
#endif
armv8: fsl-layerscape: identify boot source from PORSR register PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:42 +00:00
switch (src) {
case BOOT_SOURCE_IFC_NOR:
env_loc = ENVL_FLASH;
break;
case BOOT_SOURCE_QSPI_NOR:
/* FALLTHROUGH */
case BOOT_SOURCE_XSPI_NOR:
env_loc = ENVL_SPI_FLASH;
break;
case BOOT_SOURCE_IFC_NAND:
/* FALLTHROUGH */
case BOOT_SOURCE_QSPI_NAND:
/* FALLTHROUGH */
case BOOT_SOURCE_XSPI_NAND:
env_loc = ENVL_NAND;
break;
case BOOT_SOURCE_SD_MMC:
/* FALLTHROUGH */
case BOOT_SOURCE_SD_MMC2:
env_loc = ENVL_MMC;
break;
case BOOT_SOURCE_I2C1_EXTENDED:
/* FALLTHROUGH */
default:
break;
}
return env_loc;
}
#endif /* CONFIG_TFABOOT */
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
armv8/fsl-lsch3: Update code to release secondary cores NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-17 06:59:56 +00:00
u32 initiator_type(u32 cluster, int init_id)
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
{
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
u32 type = 0;
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
type = gur_in32(&gur->tp_ityp[idx]);
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
if (type & TP_ITYP_AV)
return type;
return 0;
}
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com>
2016-09-13 19:40:30 +00:00
u32 cpu_pos_mask(void)
{
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
armv8: fsl-layerscape: Fix "cpu status" command The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com>
2016-09-13 19:40:30 +00:00
int i = 0;
u32 cluster, type, mask = 0;
do {
int j;
cluster = gur_in32(&gur->tp_cluster[i].lower);
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
type = initiator_type(cluster, j);
if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
}
i++;
} while ((cluster & TP_CLUSTER_EOC) == 0x0);
return mask;
}
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
u32 cpu_mask(void)
{
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
int i = 0, count = 0;
u32 cluster, type, mask = 0;
do {
int j;
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
cluster = gur_in32(&gur->tp_cluster[i].lower);
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
type = initiator_type(cluster, j);
if (type) {
if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
mask |= 1 << count;
count++;
}
}
i++;
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
} while ((cluster & TP_CLUSTER_EOC) == 0x0);
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
return mask;
}
/*
* Return the number of cores on this SOC.
*/
int cpu_numcores(void)
{
return hweight32(cpu_mask());
}
int fsl_qoriq_core_to_cluster(unsigned int core)
{
struct ccsr_gur __iomem *gur =
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
(void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
int i = 0, count = 0;
u32 cluster;
do {
int j;
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
cluster = gur_in32(&gur->tp_cluster[i].lower);
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
if (initiator_type(cluster, j)) {
if (count == core)
return i;
count++;
}
}
i++;
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
} while ((cluster & TP_CLUSTER_EOC) == 0x0);
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
return -1; /* cannot identify the cluster */
}
u32 fsl_qoriq_core_to_type(unsigned int core)
{
struct ccsr_gur __iomem *gur =
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
(void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
int i = 0, count = 0;
u32 cluster, type;
do {
int j;
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
cluster = gur_in32(&gur->tp_cluster[i].lower);
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
type = initiator_type(cluster, j);
if (type) {
if (count == core)
return type;
count++;
}
}
i++;
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
} while ((cluster & TP_CLUSTER_EOC) == 0x0);
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
return -1; /* cannot identify the cluster */
}
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-17 06:59:51 +00:00
#ifndef CONFIG_FSL_LSCH3
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2016-06-13 04:28:32 +00:00
uint get_svr(void)
{
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2016-06-13 04:28:32 +00:00
return gur_in32(&gur->svr);
}
armv8: lsch3: Add generic get_svr() in assembly Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-17 06:59:51 +00:00
#endif
arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2016-06-13 04:28:32 +00:00
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
struct sys_info sysinfo;
char buf[32];
unsigned int i, core;
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2016-04-04 18:41:26 +00:00
u32 type, rcw, svr = gur_in32(&gur->svr);
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
armv8/fsl-ch3: Add support to print SoC personality This patch adds support to print out the SoC personality. Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-28 09:24:06 +00:00
puts("SoC: ");
cpu_name(buf);
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2016-04-04 18:41:26 +00:00
printf(" %s (0x%x)\n", buf, svr);
armv8/fsl-ch3: Add support to print SoC personality This patch adds support to print out the SoC personality. Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-28 09:24:06 +00:00
memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
get_sys_info(&sysinfo);
puts("Clock Configuration:");
for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
if (!(i % 3))
puts("\n ");
type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
printf("CPU%d(%s):%-4s MHz ", core,
type == TY_ITYP_VER_A7 ? "A7 " :
(type == TY_ITYP_VER_A53 ? "A53" :
armv8: fsl-layerscape: Add A72 core detection Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-05 08:01:52 +00:00
(type == TY_ITYP_VER_A57 ? "A57" :
(type == TY_ITYP_VER_A72 ? "A72" : " "))),
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
strmhz(buf, sysinfo.freq_processor[core]));
}
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-10 08:44:15 +00:00
/* Display platform clock as Bus frequency. */
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
printf("\n Bus: %-4s MHz ",
armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-10 08:44:15 +00:00
strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
armv8/fsl-lsch3: Fix DDR speed message DDR speed should be in MT/s, not MHz. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
2015-05-28 09:24:05 +00:00
printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:54 +00:00
#ifdef CONFIG_SYS_DPAA_FMAN
printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
#endif
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-09 11:12:07 +00:00
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2016-04-04 18:41:26 +00:00
if (soc_has_dp_ddr()) {
printf(" DP-DDR: %-4s MT/s",
strmhz(buf, sysinfo.freq_ddrbus2));
}
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
#endif
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
puts("\n");
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
/*
* Display the RCW, so that no one gets confused as to what RCW
armv8/fsl-ch3: Add support to print RCW configuration This patch adds support to print out the Reset Configuration Word information. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-03-21 02:28:20 +00:00
* we're actually using for this boot.
*/
puts("Reset Configuration Word (RCW):");
for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
rcw = gur_in32(&gur->rcwsr[i]);
armv8/fsl-ch3: Add support to print RCW configuration This patch adds support to print out the Reset Configuration Word information. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-03-21 02:28:20 +00:00
if ((i % 4) == 0)
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
printf("\n %08x:", i * 4);
armv8/fsl-ch3: Add support to print RCW configuration This patch adds support to print out the Reset Configuration Word information. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-03-21 02:28:20 +00:00
printf(" %08x", rcw);
}
puts("\n");
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-06-23 22:15:54 +00:00
return 0;
}
#endif
armv8/fsl-lsch3: Add support to load and start MC Firmware Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
2014-06-23 22:15:55 +00:00
ls2085a: esdhc: Add esdhc support for ls2085a This patch adds esdhc support for ls2085a. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-03-21 02:28:31 +00:00
#ifdef CONFIG_FSL_ESDHC
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2020-06-26 06:13:33 +00:00
int cpu_mmc_init(struct bd_info *bis)
ls2085a: esdhc: Add esdhc support for ls2085a This patch adds esdhc support for ls2085a. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-03-21 02:28:31 +00:00
{
return fsl_esdhc_mmc_init(bis);
}
#endif
treewide: convert bd_t to struct bd_info by coccinelle The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2020-06-26 06:13:33 +00:00
int cpu_eth_init(struct bd_info *bis)
armv8/fsl-lsch3: Add support to load and start MC Firmware Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
2014-06-23 22:15:55 +00:00
{
int error = 0;
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-05 10:12:29 +00:00
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
driver/fsl-mc: Add support of MC Flibs Freescale's Layerscape Management Complex (MC) provide support various objects like DPRC, DPNI, DPBP and DPIO. Where: DPRC: Place holdes for other MC objectes like DPNI, DPBP, DPIO DPBP: Management of buffer pool DPIO: Used for used to QBMan portal DPNI: Represents standard network interface These objects are used for DPAA ethernet drivers. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com> Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-19 16:20:45 +00:00
error = fsl_mc_ldpaa_init(bis);
armv8/fsl-lsch3: Add support to load and start MC Firmware Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
2014-06-23 22:15:55 +00:00
#endif
return error;
}
armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-09-08 19:20:00 +00:00
armv8: layerscape: add PSCI support for cpu release For cpu release command, check whether PSCI is supported firstly, if supported, use PSCI to kick off secondary cores, otherwise still use spin table. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> [Fixed checkpatch alignment CHECKs] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-21 04:12:49 +00:00
int check_psci(void)
armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-09-08 19:20:00 +00:00
{
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-19 05:27:39 +00:00
unsigned int psci_ver;
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-05 06:30:14 +00:00
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-19 05:27:39 +00:00
psci_ver = sec_firmware_support_psci_version();
if (psci_ver == PSCI_INVALID_VER)
return 1;
return 0;
}
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-10 06:02:52 +00:00
static void config_core_prefetch(void)
{
char *buf = NULL;
char buffer[HWCONFIG_BUFFER_SIZE];
const char *prefetch_arg = NULL;
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-04-22 09:23:27 +00:00
struct arm_smccc_res res;
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-10 06:02:52 +00:00
size_t arglen;
unsigned int mask;
if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
buf = buffer;
fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Tested-by: Michael Walle <michael@walle.cc>
2019-10-31 05:41:09 +00:00
else
return;
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-10 06:02:52 +00:00
prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
&arglen, buf);
if (prefetch_arg) {
mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
if (mask & 0x1) {
printf("Core0 prefetch can't be disabled\n");
return;
}
#define SIP_PREFETCH_DISABLE_64 0xC200FF13
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-04-22 09:23:27 +00:00
arm_smccc_smc(SIP_PREFETCH_DISABLE_64, mask, 0, 0, 0, 0, 0, 0,
&res);
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-10 06:02:52 +00:00
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-04-22 09:23:27 +00:00
if (res.a0)
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-10 06:02:52 +00:00
printf("Prefetch disable config failed for mask ");
else
printf("Prefetch disable config passed for mask ");
printf("0x%x\n", mask);
}
}
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-27 15:19:32 +00:00
#ifdef CONFIG_PCIE_ECAM_GENERIC
__weak void set_ecam_icids(void)
{
}
#endif
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-19 05:27:39 +00:00
int arch_early_init_r(void)
{
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-05 06:30:14 +00:00
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-02-14 05:04:31 +00:00
u32 svr_dev_id;
/*
* erratum A009635 is valid only for LS2080A SoC and
* its personalitiesi
*/
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-04 04:18:28 +00:00
svr_dev_id = get_svr();
if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
armv8/fsl-layerscape: Update erratum A009635 implementation Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-02-14 05:04:31 +00:00
erratum_a009635();
armv8: ls2085a: Add workaround of errata A009635 If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-05 06:30:14 +00:00
#endif
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21 03:36:48 +00:00
#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
erratum_a009942_check_cpo();
#endif
arm: psci: make psci usable on single core socs PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-19 05:27:39 +00:00
if (check_psci()) {
debug("PSCI: PSCI does not exist.\n");
/* if PSCI does not exist, boot secondary cores here */
if (fsl_layerscape_wake_seconday_cores())
ARMv8/Layerscape: switch SMP method accordingly If the PSCI and PPA is ready, skip the fixup for spin-table and waking secondary cores. Otherwise, change SMP method to spin-table, and the device node of PSCI will be removed. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28 12:18:15 +00:00
printf("Did not wake secondary cores\n");
}
armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-09-08 19:20:00 +00:00
armv8: fsl-layerscape: Add support of disabling core prefetch Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-10 06:02:52 +00:00
config_core_prefetch();
armv8: Add SerDes framework for Layerscape Architecture Add support of SerDes framework for Layerscape Architecture. - Add support of 2 SerDes block - Add SerDes protocol parsing and detection - Create table of SerDes protocol supported by LS2085A Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-21 02:28:16 +00:00
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:54 +00:00
#endif
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2018-10-29 11:28:26 +00:00
#ifdef CONFIG_SYS_FSL_HAS_RGMII
/* some dpmacs in armv8a based freescale layerscape SOCs can be
net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-09-18 12:32:34 +00:00
* configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2018-10-29 11:28:26 +00:00
* EC*_PMUX(rgmii) bits in RCW.
* e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
* serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23 10:50:38 +00:00
* Now if a dpmac is enabled as RGMII through ECx_PMUX then it takes
* precedence over SerDes protocol. i.e. in LX2160A if we select serdes
* protocol that configures dpmac17 as SGMII and set the EC1_PMUX as
* RGMII, then the dpmac is RGMII and not SGMII.
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2018-10-29 11:28:26 +00:00
*
net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23 10:50:38 +00:00
* Therefore, even thought fsl_rgmii_init is after fsl_serdes_init
* function of SOC, the dpmac will be enabled as RGMII even if it was
* also enabled before as SGMII. If ECx_PMUX is not configured for
* RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init().
armv8: fsl-layerscape: reorder rgmii dpmacs' enablement some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2018-10-29 11:28:26 +00:00
*/
fsl_rgmii_init();
#endif
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:54 +00:00
#ifdef CONFIG_FMAN_ENET
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-23 13:25:19 +00:00
#ifndef CONFIG_DM_ETH
armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:54 +00:00
fman_enet_init();
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-15 21:01:00 +00:00
#endif
driver: net: fm: add DM ETH support Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-23 13:25:19 +00:00
#endif
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-15 21:01:00 +00:00
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_qbman_portals();
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-27 15:19:32 +00:00
#endif
#ifdef CONFIG_PCIE_ECAM_GENERIC
set_ecam_icids();
armv8: Add SerDes framework for Layerscape Architecture Add support of SerDes framework for Layerscape Architecture. - Add support of 2 SerDes block - Add SerDes protocol parsing and detection - Create table of SerDes protocol supported by LS2085A Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-21 02:28:16 +00:00
#endif
armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-09-08 19:20:00 +00:00
return 0;
}
armv8/ls2085a: Fix generic timer clock source The timer clock is system clock divided by 4, not fixed 12MHz. This is common to the SoC, not board specific. Primary core is fixed when u-boot still runs in board_f. Secondary cores are fixed by reading a variable set by u-boot. Signed-off-by: York Sun <yorksun@freescale.com> CC: Mark Rutland <mark.rutland@arm.com>
2015-03-21 02:28:08 +00:00
int timer_init(void)
{
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
#ifdef CONFIG_FSL_LSCH3
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
u32 __iomem *cltbenr = (u32 *)CFG_SYS_FSL_PMU_CLTBENR;
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
#endif
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-08-08 08:00:30 +00:00
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
defined(CONFIG_ARCH_LS1028A)
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-08 02:31:42 +00:00
u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-17 06:59:52 +00:00
u32 svr_dev_id;
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-08 02:31:42 +00:00
#endif
armv8/ls2085a: Fix generic timer clock source The timer clock is system clock divided by 4, not fixed 12MHz. This is common to the SoC, not board specific. Primary core is fixed when u-boot still runs in board_f. Secondary cores are fixed by reading a variable set by u-boot. Signed-off-by: York Sun <yorksun@freescale.com> CC: Mark Rutland <mark.rutland@arm.com>
2015-03-21 02:28:08 +00:00
#ifdef COUNTER_FREQUENCY_REAL
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
/* Update with accurate clock frequency */
armv8: layerscape: Make U-Boot EL2 safe When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com>
2017-05-15 15:51:59 +00:00
if (current_el() == 3)
asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
armv8/ls2085a: Fix generic timer clock source The timer clock is system clock divided by 4, not fixed 12MHz. This is common to the SoC, not board specific. Primary core is fixed when u-boot still runs in board_f. Secondary cores are fixed by reading a variable set by u-boot. Signed-off-by: York Sun <yorksun@freescale.com> CC: Mark Rutland <mark.rutland@arm.com>
2015-03-21 02:28:08 +00:00
#endif
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
#ifdef CONFIG_FSL_LSCH3
armv8/ls2085a: Fix generic timer clock source The timer clock is system clock divided by 4, not fixed 12MHz. This is common to the SoC, not board specific. Primary core is fixed when u-boot still runs in board_f. Secondary cores are fixed by reading a variable set by u-boot. Signed-off-by: York Sun <yorksun@freescale.com> CC: Mark Rutland <mark.rutland@arm.com>
2015-03-21 02:28:08 +00:00
/* Enable timebase for all clusters.
* It is safe to do so even some clusters are not enabled.
*/
out_le32(cltbenr, 0xf);
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
#endif
armv8/ls2085a: Fix generic timer clock source The timer clock is system clock divided by 4, not fixed 12MHz. This is common to the SoC, not board specific. Primary core is fixed when u-boot still runs in board_f. Secondary cores are fixed by reading a variable set by u-boot. Signed-off-by: York Sun <yorksun@freescale.com> CC: Mark Rutland <mark.rutland@arm.com>
2015-03-21 02:28:08 +00:00
armv8: ls1028a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-08-08 08:00:30 +00:00
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
defined(CONFIG_ARCH_LS1028A)
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-08 02:31:42 +00:00
/*
* In certain Layerscape SoCs, the clock for each core's
* has an enable bit in the PMU Physical Core Time Base Enable
* Register (PCTBENR), which allows the watchdog to operate.
*/
setbits_le32(pctbenr, 0xff);
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-17 06:59:52 +00:00
/*
* For LS2080A SoC and its personalities, timer controller
* offset is different
*/
armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-12-04 04:18:28 +00:00
svr_dev_id = get_svr();
if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
armv8: lsch3: Use SVR based timer base address detection Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-17 06:59:52 +00:00
cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
armv8/ls2080a: configure PMU's PCTBENR to enable WDT The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-08 02:31:42 +00:00
#endif
armv8/ls2085a: Fix generic timer clock source The timer clock is system clock divided by 4, not fixed 12MHz. This is common to the SoC, not board specific. Primary core is fixed when u-boot still runs in board_f. Secondary cores are fixed by reading a variable set by u-boot. Signed-off-by: York Sun <yorksun@freescale.com> CC: Mark Rutland <mark.rutland@arm.com>
2015-03-21 02:28:08 +00:00
/* Enable clock for timer
* This is a global setting.
*/
out_le32(cntcr, 0x1);
return 0;
}
armv8/ls2085a: Add support for reset request Add support for reset_cpu() by asserting RESET_REQ_B. Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-03-21 02:28:09 +00:00
arm64: layerscape: Support SYSRESET CONFIG_SYSRESET provides its own implementation of reset_cpu. Disable our version when it is enabled. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-09-26 16:47:37 +00:00
#if !CONFIG_IS_ENABLED(SYSRESET)
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29 00:27:13 +00:00
__efi_runtime_data u32 __iomem *rstcr = (u32 *)CFG_SYS_FSL_RST_ADDR;
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-17 00:03:01 +00:00
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-12-15 15:47:52 +00:00
void __efi_runtime reset_cpu(void)
armv8/ls2085a: Add support for reset request Add support for reset_cpu() by asserting RESET_REQ_B. Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-03-21 02:28:09 +00:00
{
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-29 13:46:16 +00:00
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-09 08:36:05 +00:00
/* clear the RST_REQ_MSK and SW_RST_REQ */
out_le32(rstcr, 0x0);
/* initiate the sw reset request */
out_le32(rstcr, 0x1);
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:17:09 +00:00
#else
armv8: lx2160a: fix reset sequence Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-09 08:36:05 +00:00
u32 val;
armv8/ls2085a: Add support for reset request Add support for reset_cpu() by asserting RESET_REQ_B. Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-03-21 02:28:09 +00:00
/* Raise RESET_REQ_B */
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
val = scfg_in32(rstcr);
armv8/ls2085a: Add support for reset request Add support for reset_cpu() by asserting RESET_REQ_B. Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-03-21 02:28:09 +00:00
val |= 0x02;
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 11:47:50 +00:00
scfg_out32(rstcr, val);
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:17:09 +00:00
#endif
armv8/ls2085a: Add support for reset request Add support for reset_cpu() by asserting RESET_REQ_B. Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-03-21 02:28:09 +00:00
}
arm64: layerscape: Support SYSRESET CONFIG_SYSRESET provides its own implementation of reset_cpu. Disable our version when it is enabled. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-09-26 16:47:37 +00:00
#endif
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-07 19:08:58 +00:00
fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride <matt@traverse.com.au> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-10-18 03:27:54 +00:00
#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-17 00:03:01 +00:00
void __efi_runtime EFIAPI efi_reset_system(
enum efi_reset_type reset_type,
efi_status_t reset_status,
unsigned long data_size, void *reset_data)
{
switch (reset_type) {
case EFI_RESET_COLD:
case EFI_RESET_WARM:
efi_loader: add missing EFI_RESET_PLATFORM_SPECIFIC EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2018-02-06 21:00:22 +00:00
case EFI_RESET_PLATFORM_SPECIFIC:
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-12-15 15:47:52 +00:00
reset_cpu();
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-17 00:03:01 +00:00
break;
case EFI_RESET_SHUTDOWN:
/* Nothing we can do */
break;
}
while (1) { }
}
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2018-03-03 14:28:59 +00:00
efi_status_t efi_reset_system_init(void)
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-17 00:03:01 +00:00
{
efi_loader: exit status for efi_reset_system_init efi_reset_system_init provides the architecture or board specific initialization of the EFI subsystem. Errors should be caught and signalled by a return code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2018-03-03 14:28:59 +00:00
return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
armv8: fsl-layerscape: Add support for efi_loader RTS reset When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-17 00:03:01 +00:00
}
#endif
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com>
2017-09-07 17:12:32 +00:00
/*
* Calculate reserved memory with given memory bank
* Return aligned memory size on success
* Return (ram_size + needed size) for failure
*/
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-07 19:08:58 +00:00
phys_size_t board_reserve_ram_top(phys_size_t ram_size)
{
phys_size_t ram_top = ram_size;
armv8: ls2080aqds: Add support for SD boot Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-05 10:12:29 +00:00
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com>
2017-09-07 17:12:32 +00:00
ram_top = mc_get_dram_block_size();
if (ram_top > ram_size)
return ram_size + ram_top;
ram_top = ram_size - ram_top;
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
/* The start address of MC reserved memory needs to be aligned. */
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-07 19:08:58 +00:00
ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
#endif
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
return ram_size - ram_top;
}
phys_size_t get_effective_memsize(void)
{
phys_size_t ea_size, rem = 0;
/*
* For ARMv8 SoCs, DDR memory is split into two or three regions. The
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-03 21:50:49 +00:00
* first region is 2GB space at 0x8000_0000. Secure memory needs to
* allocated from first region. If the memory extends to the second
* region (or the third region if applicable), Management Complex (MC)
* memory should be put into the highest region, i.e. the end of DDR
global: Migrate CONFIG_MAX_MEM_MAPPED to CFG Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-04 15:04:50 +00:00
* memory. CFG_MAX_MEM_MAPPED is set to the size of first region so
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-03 21:50:49 +00:00
* U-Boot doesn't relocate itself into higher address. Should DDR be
* configured to skip the first region, this function needs to be
* adjusted.
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
*/
global: Migrate CONFIG_MAX_MEM_MAPPED to CFG Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-04 15:04:50 +00:00
if (gd->ram_size > CFG_MAX_MEM_MAPPED) {
ea_size = CFG_MAX_MEM_MAPPED;
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
rem = gd->ram_size - ea_size;
} else {
ea_size = gd->ram_size;
}
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
#ifdef CFG_SYS_MEM_RESERVE_SECURE
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
/* Check if we have enough space for secure memory */
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
if (ea_size > CFG_SYS_MEM_RESERVE_SECURE)
ea_size -= CFG_SYS_MEM_RESERVE_SECURE;
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-03 21:50:49 +00:00
else
printf("Error: No enough space for secure memory.\n");
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
#endif
/* Check if we have enough memory for MC */
if (rem < board_reserve_ram_top(rem)) {
/* Not enough memory in high region to reserve */
armv8: fsl-layerscape: Fix MC reserved memory calculation In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com>
2017-09-07 17:12:32 +00:00
if (ea_size > board_reserve_ram_top(ea_size))
ea_size -= board_reserve_ram_top(ea_size);
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
else
printf("Error: No enough space for reserved memory.\n");
}
return ea_size;
}
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:58 +00:00
#ifdef CONFIG_TFABOOT
phys_size_t tfa_get_dram_size(void)
{
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-04-22 09:23:27 +00:00
struct arm_smccc_res res;
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:58 +00:00
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-04-22 09:23:27 +00:00
arm_smccc_smc(SMC_DRAM_BANK_INFO, -1, 0, 0, 0, 0, 0, 0, &res);
if (res.a0)
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:58 +00:00
return 0;
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-04-22 09:23:27 +00:00
return res.a1;
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:58 +00:00
}
static int tfa_dram_init_banksize(void)
{
int i = 0, ret = 0;
phys_size_t dram_size = tfa_get_dram_size();
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-04-22 09:23:27 +00:00
struct arm_smccc_res res;
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:58 +00:00
debug("dram_size %llx\n", dram_size);
if (!dram_size)
return -EINVAL;
do {
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-04-22 09:23:27 +00:00
arm_smccc_smc(SMC_DRAM_BANK_INFO, i, 0, 0, 0, 0, 0, 0, &res);
if (res.a0) {
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:58 +00:00
ret = -EINVAL;
break;
}
armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-04-22 09:23:27 +00:00
debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2);
gd->bd->bi_dram[i].start = res.a1;
gd->bd->bi_dram[i].size = res.a2;
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:58 +00:00
dram_size -= gd->bd->bi_dram[i].size;
i++;
} while (dram_size);
if (i > 0)
ret = 0;
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-28 02:19:28 +00:00
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:58 +00:00
/* Assign memory for MC */
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
if (gd->bd->bi_dram[2].size >=
board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
gd->arch.resv_ram = gd->bd->bi_dram[2].start +
gd->bd->bi_dram[2].size -
board_reserve_ram_top(gd->bd->bi_dram[2].size);
} else
#endif
{
if (gd->bd->bi_dram[1].size >=
board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
gd->arch.resv_ram = gd->bd->bi_dram[1].start +
gd->bd->bi_dram[1].size -
board_reserve_ram_top(gd->bd->bi_dram[1].size);
} else if (gd->bd->bi_dram[0].size >
board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
gd->arch.resv_ram = gd->bd->bi_dram[0].start +
gd->bd->bi_dram[0].size -
board_reserve_ram_top(gd->bd->bi_dram[0].size);
}
}
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-28 02:19:28 +00:00
#endif /* CONFIG_RESV_RAM */
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:58 +00:00
return ret;
}
#endif
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-03-31 14:40:32 +00:00
int dram_init_banksize(void)
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
{
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
phys_size_t dp_ddr_size;
#endif
armv8: layerscape: add SMC calls for DDR size and bank info Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-11-05 18:01:58 +00:00
#ifdef CONFIG_TFABOOT
if (!tfa_dram_init_banksize())
return 0;
#endif
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
/*
* gd->ram_size has the total size of DDR memory, less reserved secure
* memory. The DDR extends from low region to high region(s) presuming
* no hole is created with DDR configuration. gd->arch.secure_ram tracks
* the location of secure memory. gd->arch.resv_ram tracks the location
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-28 15:42:12 +00:00
* of reserved memory for Management Complex (MC). Because gd->ram_size
* is reduced by this function if secure memory is reserved, checking
* gd->arch.secure_ram should be done to avoid running it repeatedly.
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
*/
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-28 15:42:12 +00:00
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
#ifdef CFG_SYS_MEM_RESERVE_SECURE
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-28 15:42:12 +00:00
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
debug("No need to run again, skip %s\n", __func__);
return 0;
}
#endif
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:37 +00:00
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) {
gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
gd->bd->bi_dram[1].size = gd->ram_size -
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
CFG_SYS_DDR_BLOCK1_SIZE;
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
CONFIG_SYS_DDR_BLOCK2_SIZE;
gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
}
#endif
} else {
gd->bd->bi_dram[0].size = gd->ram_size;
}
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
#ifdef CFG_SYS_MEM_RESERVE_SECURE
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-03 21:50:49 +00:00
if (gd->bd->bi_dram[0].size >
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
CFG_SYS_MEM_RESERVE_SECURE) {
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-03 21:50:49 +00:00
gd->bd->bi_dram[0].size -=
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
CFG_SYS_MEM_RESERVE_SECURE;
armv8: fsl-layerscape: Allocate Secure memory from first ddr region This change is required due to trusted OS (OP-TEE) not being position independent code, it requires compile time fixed base address. To take care of this it is assumed that all layerscape armv8 platforms has minimum 2G ddr in first region. So we can have fixed address space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from top of first 2G ddr region and compile trusted OS with this fixed base address. But one exception here is ls1012 where we have only 1G (rdb) or 512M (frdm) ddr memory. For those we can have different fixed compile time base addresses for trusted OS. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-10-03 21:50:49 +00:00
gd->arch.secure_ram = gd->bd->bi_dram[0].start +
gd->bd->bi_dram[0].size;
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE;
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
}
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
#endif /* CFG_SYS_MEM_RESERVE_SECURE */
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-28 02:19:28 +00:00
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
/* Assign memory for MC */
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
if (gd->bd->bi_dram[2].size >=
board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
gd->arch.resv_ram = gd->bd->bi_dram[2].start +
gd->bd->bi_dram[2].size -
board_reserve_ram_top(gd->bd->bi_dram[2].size);
} else
#endif
{
if (gd->bd->bi_dram[1].size >=
board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
gd->arch.resv_ram = gd->bd->bi_dram[1].start +
gd->bd->bi_dram[1].size -
board_reserve_ram_top(gd->bd->bi_dram[1].size);
} else if (gd->bd->bi_dram[0].size >
board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
gd->arch.resv_ram = gd->bd->bi_dram[0].start +
gd->bd->bi_dram[0].size -
board_reserve_ram_top(gd->bd->bi_dram[0].size);
}
}
fsl-layerscape: Add RESV_RAM check in resv_ram addr The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-28 02:19:28 +00:00
#endif /* CONFIG_RESV_RAM */
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
#error "This SoC shouldn't have DP DDR"
#endif
if (soc_has_dp_ddr()) {
/* initialize DP-DDR here */
puts("DP-DDR: ");
/*
* DDR controller use 0 as the base address for binding.
* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
*/
dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
CONFIG_DP_DDR_CTRL,
CONFIG_DP_DDR_NUM_CTRLS,
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
NULL, NULL, NULL);
if (dp_ddr_size) {
gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
gd->bd->bi_dram[2].size = dp_ddr_size;
} else {
puts("Not detected");
}
}
#endif
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-03-31 14:40:32 +00:00
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
#ifdef CFG_SYS_MEM_RESERVE_SECURE
armv8: fsl-layerscape: Avoid running dram_init_banksize again gd->ram_size is reduced in this function to reserve secure memory. Avoid running this function again to further reduce memory size. This fixes issue for SPL boot with PPA image loaded in which case secure memory is incorrectly allocated due to repeated calling. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-28 15:42:12 +00:00
debug("%s is called. gd->ram_size is reduced to %lu\n",
__func__, (ulong)gd->ram_size);
#endif
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-03-31 14:40:32 +00:00
return 0;
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
}
efi_loader: simplify ifdefs Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2018-08-30 21:43:43 +00:00
#if CONFIG_IS_ENABLED(EFI_LOADER)
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
void efi_add_known_memory(void)
{
int i;
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-05-17 10:29:19 +00:00
phys_addr_t ram_start;
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
phys_size_t ram_size;
/* Add RAM */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
#error "This SoC shouldn't have DP DDR"
#endif
if (i == 2)
continue; /* skip DP-DDR */
#endif
ram_start = gd->bd->bi_dram[i].start;
ram_size = gd->bd->bi_dram[i].size;
#ifdef CONFIG_RESV_RAM
if (gd->arch.resv_ram >= ram_start &&
gd->arch.resv_ram < ram_start + ram_size)
ram_size = gd->arch.resv_ram - ram_start;
#endif
efi_loader: round the memory area in efi_add_memory_map() Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-05-17 10:29:19 +00:00
efi_add_memory_map(ram_start, ram_size,
EFI_CONVENTIONAL_MEMORY);
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
}
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-07 19:08:58 +00:00
}
armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:28 +00:00
#endif
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:34 +00:00
/*
* Before DDR size is known, early MMU table have DDR mapped as device memory
* to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
* needs to be set for these mappings.
* If a special case configures DDR with holes in the mapping, the holes need
* to be marked as invalid. This is not implemented in this function.
*/
void update_early_mmu_table(void)
{
if (!gd->arch.tlb_addr)
return;
global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-10 16:19:45 +00:00
if (gd->ram_size <= CFG_SYS_FSL_DRAM_SIZE1) {
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:34 +00:00
mmu_change_region_attr(
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:37 +00:00
CFG_SYS_SDRAM_BASE,
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:34 +00:00
gd->ram_size,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |
PTE_TYPE_VALID);
} else {
mmu_change_region_attr(
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:37 +00:00
CFG_SYS_SDRAM_BASE,
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
CFG_SYS_DDR_BLOCK1_SIZE,
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:34 +00:00
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |
PTE_TYPE_VALID);
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
#ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
#error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
#endif
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
if (gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE >
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:34 +00:00
CONFIG_SYS_DDR_BLOCK2_SIZE) {
mmu_change_region_attr(
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
CFG_SYS_DDR_BLOCK2_BASE,
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:34 +00:00
CONFIG_SYS_DDR_BLOCK2_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |
PTE_TYPE_VALID);
mmu_change_region_attr(
CONFIG_SYS_DDR_BLOCK3_BASE,
gd->ram_size -
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
CFG_SYS_DDR_BLOCK1_SIZE -
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:34 +00:00
CONFIG_SYS_DDR_BLOCK2_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |
PTE_TYPE_VALID);
} else
#endif
{
mmu_change_region_attr(
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
CFG_SYS_DDR_BLOCK2_BASE,
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:34 +00:00
gd->ram_size -
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
CFG_SYS_DDR_BLOCK1_SIZE,
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:34 +00:00
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |
PTE_TYPE_VALID);
}
}
}
__weak int dram_init(void)
{
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-02-25 16:19:53 +00:00
#ifdef CONFIG_SYS_FSL_DDR
arm: freescale: Rename initdram() to fsl_initdram() This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-06 18:47:04 +00:00
fsl_initdram();
armv8: layerscape: Add TFABOOT support Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2018-11-05 18:01:37 +00:00
#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
defined(CONFIG_SPL_BUILD)
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:34 +00:00
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-02-25 16:19:53 +00:00
#endif
armv8: layerscape: Update early MMU for DDR after initialization In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-06 17:02:34 +00:00
#endif
return 0;
}
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-10 23:05:40 +00:00
#ifdef CONFIG_ARCH_MISC_INIT
__weak int serdes_misc_init(void)
{
return 0;
}
int arch_misc_init(void)
{
Layerscape: Enable Job ring driver model. LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162 platforms are enabled with JR driver model. removed sec_init() call from board files. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc>
2022-03-24 06:20:35 +00:00
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
caam: Fix crash in case caam_jr_probe failed If probing caam_jr returns failure, the variable "dev" will not be initialized, so we can't use dev->name for the error print. Otherwise it will cause crash. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
2022-05-11 08:26:20 +00:00
printf("Failed to initialize caam_jr: %d\n", ret);
Layerscape: Enable Job ring driver model. LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162 platforms are enabled with JR driver model. removed sec_init() call from board files. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc>
2022-03-24 06:20:35 +00:00
}
arch: armv8: fsl-layerscape: export serdes config to environment Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-10 23:05:40 +00:00
serdes_misc_init();
return 0;
}
#endif
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