2018-05-06 21:58:06 +00:00
|
|
|
# SPDX-License-Identifier: GPL-2.0+
|
armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.
SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:17:09 +00:00
|
|
|
# Copyright 2016-2018 NXP
|
2015-10-26 11:47:50 +00:00
|
|
|
# Copyright 2014-2015, Freescale Semiconductor
|
|
|
|
|
|
|
|
obj-y += cpu.o
|
|
|
|
obj-y += lowlevel.o
|
|
|
|
obj-y += soc.o
|
2018-01-06 03:34:23 +00:00
|
|
|
ifndef CONFIG_SPL_BUILD
|
2015-10-26 11:47:50 +00:00
|
|
|
obj-$(CONFIG_MP) += mp.o
|
|
|
|
obj-$(CONFIG_OF_LIBFDT) += fdt.o
|
2018-01-06 03:34:23 +00:00
|
|
|
endif
|
2015-10-26 11:47:50 +00:00
|
|
|
obj-$(CONFIG_SPL) += spl.o
|
2017-01-16 09:31:49 +00:00
|
|
|
obj-$(CONFIG_$(SPL_)FSL_LS_PPA) += ppa.o
|
2015-10-26 11:47:50 +00:00
|
|
|
|
|
|
|
ifneq ($(CONFIG_FSL_LSCH3),)
|
|
|
|
obj-y += fsl_lsch3_speed.o
|
|
|
|
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
|
2015-10-26 11:47:51 +00:00
|
|
|
else
|
|
|
|
ifneq ($(CONFIG_FSL_LSCH2),)
|
|
|
|
obj-y += fsl_lsch2_speed.o
|
|
|
|
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o
|
|
|
|
endif
|
2015-10-26 11:47:50 +00:00
|
|
|
endif
|
|
|
|
|
armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.
SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:17:09 +00:00
|
|
|
ifneq ($(CONFIG_ARCH_LX2160A),)
|
|
|
|
obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
|
|
|
|
endif
|
|
|
|
|
2017-03-27 18:41:01 +00:00
|
|
|
ifneq ($(CONFIG_ARCH_LS2080A),)
|
2015-11-09 11:12:07 +00:00
|
|
|
obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
|
2015-11-09 11:12:20 +00:00
|
|
|
endif
|
|
|
|
|
2017-03-27 18:41:02 +00:00
|
|
|
ifneq ($(CONFIG_ARCH_LS1043A),)
|
2015-10-26 11:47:52 +00:00
|
|
|
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
|
2016-12-08 03:58:26 +00:00
|
|
|
obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o
|
2018-08-27 14:33:59 +00:00
|
|
|
obj-y += icid.o ls1043_ids.o
|
2015-10-26 11:47:52 +00:00
|
|
|
endif
|
2016-06-03 13:11:31 +00:00
|
|
|
|
2016-09-26 15:09:26 +00:00
|
|
|
ifneq ($(CONFIG_ARCH_LS1012A),)
|
2016-06-03 13:11:31 +00:00
|
|
|
obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
|
|
|
|
endif
|
2016-07-05 08:01:55 +00:00
|
|
|
|
2016-09-26 15:09:24 +00:00
|
|
|
ifneq ($(CONFIG_ARCH_LS1046A),)
|
2016-07-05 08:01:55 +00:00
|
|
|
obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
|
2018-08-09 12:19:46 +00:00
|
|
|
obj-y += icid.o ls1046_ids.o
|
2016-07-05 08:01:55 +00:00
|
|
|
endif
|
armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:53 +00:00
|
|
|
|
|
|
|
ifneq ($(CONFIG_ARCH_LS1088A),)
|
|
|
|
obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
|
2019-07-30 14:29:58 +00:00
|
|
|
obj-y += icid.o ls1088_ids.o
|
armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:53 +00:00
|
|
|
endif
|
armv8: ls1028a: Add NXP LS1028A SoC support
Ls1028a SoC is based on Layerscape Chassis Generation 3.2
architecture with features:
2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN
ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers,
6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc.
Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-04-10 08:43:33 +00:00
|
|
|
|
|
|
|
ifneq ($(CONFIG_ARCH_LS1028A),)
|
|
|
|
obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o
|
2019-07-30 14:29:59 +00:00
|
|
|
obj-y += icid.o ls1028_ids.o
|
armv8: ls1028a: Add NXP LS1028A SoC support
Ls1028a SoC is based on Layerscape Chassis Generation 3.2
architecture with features:
2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN
ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers,
6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc.
Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-04-10 08:43:33 +00:00
|
|
|
endif
|