2015-07-25 17:46:26 +00:00
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#
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# Multifunction miscellaneous devices
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#
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menu "Multifunction device drivers"
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2015-10-07 12:20:51 +00:00
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config MISC
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bool "Enable Driver Model for Misc drivers"
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depends on DM
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help
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Enable driver model for miscellaneous devices. This class is
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used only for those do not fit other more general classes. A
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set of generic read, write and ioctl methods may be used to
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access the device.
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2018-11-18 15:14:27 +00:00
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config SPL_MISC
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bool "Enable Driver Model for Misc drivers in SPL"
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depends on SPL_DM
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2022-04-22 20:11:37 +00:00
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default MISC
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2018-11-18 15:14:27 +00:00
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help
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Enable driver model for miscellaneous devices. This class is
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used only for those do not fit other more general classes. A
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set of generic read, write and ioctl methods may be used to
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access the device.
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config TPL_MISC
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bool "Enable Driver Model for Misc drivers in TPL"
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depends on TPL_DM
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2022-04-22 20:11:37 +00:00
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default MISC
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help
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Enable driver model for miscellaneous devices. This class is
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used only for those do not fit other more general classes. A
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set of generic read, write and ioctl methods may be used to
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access the device.
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config VPL_MISC
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bool "Enable Driver Model for Misc drivers in VPL"
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depends on VPL_DM
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default MISC
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2018-11-18 15:14:27 +00:00
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help
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Enable driver model for miscellaneous devices. This class is
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used only for those do not fit other more general classes. A
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set of generic read, write and ioctl methods may be used to
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access the device.
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misc: Add support for nvmem cells
This adds support for "nvmem cells" as seen in Linux. The nvmem device
class in Linux is used for various assorted ROMs and EEPROMs. In this
sense, it is similar to UCLASS_MISC, but also includes
UCLASS_I2C_EEPROM, UCLASS_RTC, and UCLASS_MTD. New drivers corresponding
to a Linux-style nvmem device should be implemented as one of the
previously-mentioned uclasses. The nvmem API acts as a compatibility
layer to adapt the (slightly different) APIs of these uclasses. It also
handles the lookup of nvmem cells.
While nvmem devices can be accessed directly, they are most often used
by reading/writing contiguous values called "cells". Cells typically
hold information like calibration, versions, or configuration (such as
mac addresses).
nvmem devices can specify "cells" in their device tree:
qfprom: eeprom@700000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00700000 0x100000>;
/* ... */
tsens_calibration: calib@404 {
reg = <0x404 0x10>;
};
};
which can then be referenced like:
tsens {
/* ... */
nvmem-cells = <&tsens_calibration>;
nvmem-cell-names = "calibration";
};
The tsens driver could then read the calibration value like:
struct nvmem_cell cal_cell;
u8 cal[16];
nvmem_cell_get_by_name(dev, "calibration", &cal_cell);
nvmem_cell_read(&cal_cell, cal, sizeof(cal));
Because nvmem devices are not all of the same uclass, supported uclasses
must register a nvmem_interface struct. This allows CONFIG_NVMEM to be
enabled without depending on specific uclasses. At the moment,
nvmem_interface is very bare-bones, and assumes that no initialization
is necessary. However, this could be amended in the future.
Although I2C_EEPROM and MISC are quite similar (and could likely be
unified), they present different read/write function signatures. To
abstract over this, NVMEM uses the same read/write signature as Linux.
In particular, short read/writes are not allowed, which is allowed by
MISC.
The functionality implemented by nvmem cells is very similar to that
provided by i2c_eeprom_partition. "fixed-partition"s for eeproms does
not seem to have made its way into Linux or into any device tree other
than sandbox. It is possible that with the introduction of this API it
would be possible to remove it.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-05-05 17:11:39 +00:00
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config NVMEM
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bool "NVMEM support"
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help
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This adds support for a common interface to different types of
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non-volatile memory. Consumers can use nvmem-cells properties to look
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up hardware configuration data such as MAC addresses and calibration
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settings.
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config SPL_NVMEM
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bool "NVMEM support in SPL"
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help
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This adds support for a common interface to different types of
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non-volatile memory. Consumers can use nvmem-cells properties to look
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up hardware configuration data such as MAC addresses and calibration
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settings.
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2015-10-14 00:43:31 +00:00
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config ALTERA_SYSID
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bool "Altera Sysid support"
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depends on MISC
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help
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Select this to enable a sysid for Altera devices. Please find
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details on the "Embedded Peripherals IP User Guide" of Altera.
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2017-06-09 17:28:44 +00:00
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config ATSHA204A
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bool "Support for Atmel ATSHA204A module"
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2022-04-12 09:20:44 +00:00
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select BITREVERSE
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2017-06-09 17:28:44 +00:00
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depends on MISC
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help
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Enable support for I2C connected Atmel's ATSHA204A
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CryptoAuthentication module found for example on the Turris Omnia
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board.
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2022-03-08 00:24:04 +00:00
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config GATEWORKS_SC
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bool "Gateworks System Controller Support"
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depends on MISC
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help
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Enable access for the Gateworks System Controller used on Gateworks
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boards to provide a boot watchdog, power control, temperature monitor,
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voltage ADCs, and EEPROM.
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2017-05-05 17:21:38 +00:00
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config ROCKCHIP_EFUSE
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bool "Rockchip e-fuse support"
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depends on MISC
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help
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Enable (read-only) access for the e-fuse block found in Rockchip
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SoCs: accesses can either be made using byte addressing and a length
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or through child-nodes that are generated based on the e-fuse map
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retrieved from the DTS.
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This driver currently supports the RK3399 only, but can easily be
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extended (by porting the read function from the Linux kernel sources)
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to support other recent Rockchip devices.
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2019-09-25 15:57:49 +00:00
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config ROCKCHIP_OTP
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bool "Rockchip OTP Support"
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depends on MISC
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help
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Enable (read-only) access for the one-time-programmable memory block
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found in Rockchip SoCs: accesses can either be made using byte
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addressing and a length or through child-nodes that are generated
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based on the e-fuse map retrieved from the DTS.
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2020-05-29 06:03:21 +00:00
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config SIFIVE_OTP
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bool "SiFive eMemory OTP driver"
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depends on MISC
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help
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Enable support for reading and writing the eMemory OTP on the
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SiFive SoCs.
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2018-09-28 12:43:31 +00:00
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config VEXPRESS_CONFIG
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bool "Enable support for Arm Versatile Express config bus"
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depends on MISC
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help
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If you say Y here, you will get support for accessing the
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configuration bus on the Arm Versatile Express boards via
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a sysreg driver.
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2015-02-13 19:20:47 +00:00
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config CMD_CROS_EC
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bool "Enable crosec command"
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depends on CROS_EC
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help
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Enable command-line access to the Chrome OS EC (Embedded
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Controller). This provides the 'crosec' command which has
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a number of sub-commands for performing EC tasks such as
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updating its flash, accessing a small saved context area
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and talking to the I2C bus behind the EC (if there is one).
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config CROS_EC
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bool "Enable Chrome OS EC"
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help
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Enable access to the Chrome OS EC. This is a separate
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microcontroller typically available on a SPI bus on Chromebooks. It
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provides access to the keyboard, some internal storage and may
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control access to the battery and main PMIC depending on the
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device. You can use the 'crosec' command to access it.
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2018-11-18 15:14:27 +00:00
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config SPL_CROS_EC
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bool "Enable Chrome OS EC in SPL"
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2022-05-10 16:51:47 +00:00
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depends on SPL_MISC
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2018-11-18 15:14:27 +00:00
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help
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Enable access to the Chrome OS EC in SPL. This is a separate
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microcontroller typically available on a SPI bus on Chromebooks. It
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provides access to the keyboard, some internal storage and may
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control access to the battery and main PMIC depending on the
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device. You can use the 'crosec' command to access it.
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config TPL_CROS_EC
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bool "Enable Chrome OS EC in TPL"
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2022-05-10 16:51:47 +00:00
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depends on TPL_MISC
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2018-11-18 15:14:27 +00:00
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help
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Enable access to the Chrome OS EC in TPL. This is a separate
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microcontroller typically available on a SPI bus on Chromebooks. It
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provides access to the keyboard, some internal storage and may
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control access to the battery and main PMIC depending on the
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device. You can use the 'crosec' command to access it.
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2022-04-30 06:56:53 +00:00
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config VPL_CROS_EC
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bool "Enable Chrome OS EC in VPL"
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2022-05-10 16:51:47 +00:00
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depends on VPL_MISC
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2022-04-30 06:56:53 +00:00
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help
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Enable access to the Chrome OS EC in VPL. This is a separate
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microcontroller typically available on a SPI bus on Chromebooks. It
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provides access to the keyboard, some internal storage and may
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control access to the battery and main PMIC depending on the
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device. You can use the 'crosec' command to access it.
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2015-02-13 19:20:47 +00:00
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config CROS_EC_I2C
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bool "Enable Chrome OS EC I2C driver"
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depends on CROS_EC
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help
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Enable I2C access to the Chrome OS EC. This is used on older
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ARM Chromebooks such as snow and spring before the standard bus
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changed to SPI. The EC will accept commands across the I2C using
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a special message protocol, and provide responses.
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config CROS_EC_LPC
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bool "Enable Chrome OS EC LPC driver"
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depends on CROS_EC
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help
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Enable I2C access to the Chrome OS EC. This is used on x86
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Chromebooks such as link and falco. The keyboard is provided
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through a legacy port interface, so on x86 machines the main
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function of the EC is power and thermal management.
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2018-11-18 15:14:27 +00:00
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config SPL_CROS_EC_LPC
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bool "Enable Chrome OS EC LPC driver in SPL"
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2022-05-10 16:51:47 +00:00
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depends on CROS_EC && SPL_MISC
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2018-11-18 15:14:27 +00:00
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help
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Enable I2C access to the Chrome OS EC. This is used on x86
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Chromebooks such as link and falco. The keyboard is provided
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through a legacy port interface, so on x86 machines the main
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function of the EC is power and thermal management.
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config TPL_CROS_EC_LPC
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bool "Enable Chrome OS EC LPC driver in TPL"
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2022-05-10 16:51:47 +00:00
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depends on CROS_EC && TPL_MISC
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2018-11-18 15:14:27 +00:00
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help
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Enable I2C access to the Chrome OS EC. This is used on x86
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Chromebooks such as link and falco. The keyboard is provided
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through a legacy port interface, so on x86 machines the main
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function of the EC is power and thermal management.
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2022-04-30 06:56:53 +00:00
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config VPL_CROS_EC_LPC
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bool "Enable Chrome OS EC LPC driver in VPL"
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2022-05-10 16:51:47 +00:00
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depends on CROS_EC && VPL_MISC
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2022-04-30 06:56:53 +00:00
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help
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Enable I2C access to the Chrome OS EC. This is used on x86
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Chromebooks such as link and falco. The keyboard is provided
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through a legacy port interface, so on x86 machines the main
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function of the EC is power and thermal management.
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2015-03-26 15:29:40 +00:00
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config CROS_EC_SANDBOX
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bool "Enable Chrome OS EC sandbox driver"
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depends on CROS_EC && SANDBOX
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help
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Enable a sandbox emulation of the Chrome OS EC. This supports
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keyboard (use the -l flag to enable the LCD), verified boot context,
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EC flash read/write/erase support and a few other things. It is
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enough to perform a Chrome OS verified boot on sandbox.
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2018-11-18 15:14:27 +00:00
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config SPL_CROS_EC_SANDBOX
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bool "Enable Chrome OS EC sandbox driver in SPL"
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depends on SPL_CROS_EC && SANDBOX
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help
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Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
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keyboard (use the -l flag to enable the LCD), verified boot context,
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EC flash read/write/erase support and a few other things. It is
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enough to perform a Chrome OS verified boot on sandbox.
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config TPL_CROS_EC_SANDBOX
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bool "Enable Chrome OS EC sandbox driver in TPL"
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depends on TPL_CROS_EC && SANDBOX
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help
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Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
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keyboard (use the -l flag to enable the LCD), verified boot context,
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EC flash read/write/erase support and a few other things. It is
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enough to perform a Chrome OS verified boot on sandbox.
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2022-04-30 06:56:53 +00:00
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config VPL_CROS_EC_SANDBOX
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bool "Enable Chrome OS EC sandbox driver in VPL"
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depends on VPL_CROS_EC && SANDBOX
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help
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Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
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keyboard (use the -l flag to enable the LCD), verified boot context,
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EC flash read/write/erase support and a few other things. It is
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enough to perform a Chrome OS verified boot on sandbox.
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2015-02-13 19:20:47 +00:00
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config CROS_EC_SPI
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bool "Enable Chrome OS EC SPI driver"
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depends on CROS_EC
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help
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Enable SPI access to the Chrome OS EC. This is used on newer
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ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
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provides a faster and more robust interface than I2C but the bugs
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are less interesting.
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2017-05-17 09:25:02 +00:00
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config DS4510
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bool "Enable support for DS4510 CPU supervisor"
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help
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Enable support for the Maxim DS4510 CPU supervisor. It has an
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integrated 64-byte EEPROM, four programmable non-volatile I/O pins
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and a configurable timer for the supervisor function. The device is
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connected over I2C.
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2015-08-26 07:41:33 +00:00
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config FSL_SEC_MON
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2015-02-27 04:14:22 +00:00
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bool "Enable FSL SEC_MON Driver"
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help
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Freescale Security Monitor block is responsible for monitoring
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system states.
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Security Monitor can be transitioned on any security failures,
|
|
|
|
|
like software violations or hardware security violations.
|
2015-03-12 10:22:46 +00:00
|
|
|
|
2019-12-07 04:41:58 +00:00
|
|
|
config IRQ
|
2021-03-08 15:48:13 +00:00
|
|
|
bool "Interrupt controller"
|
2019-12-07 04:41:58 +00:00
|
|
|
help
|
2021-03-08 15:48:13 +00:00
|
|
|
This enables support for interrupt controllers, including ITSS.
|
2019-12-07 04:41:58 +00:00
|
|
|
Some devices have extra features, such as Apollo Lake. The
|
|
|
|
|
device has its own uclass since there are several operations
|
|
|
|
|
involved.
|
|
|
|
|
|
2018-12-16 22:25:19 +00:00
|
|
|
config JZ4780_EFUSE
|
|
|
|
|
bool "Ingenic JZ4780 eFUSE support"
|
|
|
|
|
depends on ARCH_JZ47XX
|
|
|
|
|
help
|
|
|
|
|
This selects support for the eFUSE on Ingenic JZ4780 SoCs.
|
|
|
|
|
|
arm: layerscape: Add sfp driver
This adds a driver for the Security Fuse Processor (SFP) present on
LS1012A, LS1021A, LS1043A, and LS1046A processors. It holds the
Super-Root Key (SRK), One-Time-Programmable Master Key (OTPMK), and
other "security" related fuses. Similar devices (sharing the same name)
are present on other processors, but for the moment this just supports
the LS2 variants.
The mirror registers are loaded during power-on reset. All mirror
registers must be programmed or read at once. Because of this, `fuse
prog` will program all fuses, even though only one might be specified.
To prevent accidentally burning through all your fuse programming cycles
with something like `fuse prog 0 0 A B C D`, we limit ourselves to one
programming cycle per reset. Fuses are numbered based on their address.
The fuse at 0x1e80200 is 0, the fuse at 0x1e80204 is 1, etc.
The TA_PROG_SFP supply must be enabled when programming fuses, but must
be disabled when reading them. Typically this supply is enabled by
inserting a jumper or by setting a register in the board's FPGA. I've
also added support for using a regulator. This could be helpful for
automatically issuing the FPGA write, or for toggling a GPIO controlling
the supply.
I suggest using the following procedure for programming:
1. Override the fuses you wish to program
=> fuse override 0 2 A B C D
2. Inspect the values and ensure that they are what you expect
=> fuse sense 0 2 4
3. Enable TA_PROG_SFP
4. Issue a program command using OSPR0 as a dummy. Since it contains the
write-protect bit you will usually want to write it last anyway.
=> fuse prog 0 0 0
5. Disable TA_PROG_SFP
6. Read back the fuses and ensure they are correct
=> fuse read 0 2 4
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-22 18:34:18 +00:00
|
|
|
config LS2_SFP
|
|
|
|
|
bool "Layerscape Security Fuse Processor"
|
|
|
|
|
depends on FSL_LSCH2 || ARCH_LS1021A
|
|
|
|
|
depends on MISC
|
|
|
|
|
imply DM_REGULATOR
|
|
|
|
|
help
|
|
|
|
|
This adds support for the Security Fuse Processor found on Layerscape
|
|
|
|
|
SoCs. It contains various fuses related to secure boot, including the
|
|
|
|
|
Super Root Key hash, One-Time-Programmable Master Key, Debug
|
|
|
|
|
Challenge/Response values, and others. Fuses are numbered according
|
|
|
|
|
to their four-byte offset from the start of the bank.
|
|
|
|
|
|
|
|
|
|
If you don't need to read/program fuses, say 'n'.
|
|
|
|
|
|
2015-08-27 06:49:05 +00:00
|
|
|
config MXC_OCOTP
|
|
|
|
|
bool "Enable MXC OCOTP Driver"
|
2019-07-22 01:24:55 +00:00
|
|
|
depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
|
2019-03-25 16:24:57 +00:00
|
|
|
default y
|
2015-08-27 06:49:05 +00:00
|
|
|
help
|
|
|
|
|
If you say Y here, you will get support for the One Time
|
|
|
|
|
Programmable memory pages that are stored on the some
|
|
|
|
|
Freescale i.MX processors.
|
|
|
|
|
|
2021-09-25 16:49:28 +00:00
|
|
|
config SPL_MXC_OCOTP
|
|
|
|
|
bool "Enable MXC OCOTP driver in SPL"
|
2022-05-10 16:51:47 +00:00
|
|
|
depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
|
2021-09-25 16:49:28 +00:00
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
If you say Y here, you will get support for the One Time
|
|
|
|
|
Programmable memory pages, that are stored on some
|
|
|
|
|
Freescale i.MX processors, in SPL.
|
|
|
|
|
|
2022-06-07 08:33:54 +00:00
|
|
|
config NPCM_OTP
|
|
|
|
|
bool "Nnvoton NPCM BMC On-Chip OTP Memory Support"
|
|
|
|
|
depends on (ARM && ARCH_NPCM)
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Support NPCM BMC OTP memory (fuse).
|
|
|
|
|
To compile this driver as a module, choose M here: the module
|
|
|
|
|
will be called npcm_otp.
|
|
|
|
|
|
2016-07-19 05:45:46 +00:00
|
|
|
config NUVOTON_NCT6102D
|
|
|
|
|
bool "Enable Nuvoton NCT6102D Super I/O driver"
|
|
|
|
|
help
|
|
|
|
|
If you say Y here, you will get support for the Nuvoton
|
|
|
|
|
NCT6102D Super I/O driver. This can be used to enable or
|
|
|
|
|
disable the legacy UART, the watchdog or other devices
|
|
|
|
|
in the Nuvoton Super IO chips on X86 platforms.
|
|
|
|
|
|
2019-12-07 04:41:55 +00:00
|
|
|
config P2SB
|
2020-07-01 11:37:23 +00:00
|
|
|
bool "Intel Primary to Sideband Bridge"
|
2019-12-07 04:41:55 +00:00
|
|
|
depends on X86 || SANDBOX
|
|
|
|
|
help
|
2020-07-01 11:37:23 +00:00
|
|
|
This enables support for the Intel Primary to Sideband Bridge,
|
2019-12-07 04:41:55 +00:00
|
|
|
abbreviated to P2SB. The P2SB is used to access various peripherals
|
|
|
|
|
such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
|
|
|
|
|
space. The space is segmented into different channels and peripherals
|
|
|
|
|
are accessed by device-specific means within those channels. Devices
|
|
|
|
|
should be added in the device tree as subnodes of the P2SB. A
|
|
|
|
|
Peripheral Channel Register? (PCR) API is provided to access those
|
|
|
|
|
devices - see pcr_readl(), etc.
|
|
|
|
|
|
|
|
|
|
config SPL_P2SB
|
2020-07-01 11:37:23 +00:00
|
|
|
bool "Intel Primary to Sideband Bridge in SPL"
|
2022-05-10 16:51:47 +00:00
|
|
|
depends on SPL_MISC && (X86 || SANDBOX)
|
2019-12-07 04:41:55 +00:00
|
|
|
help
|
2020-07-01 11:37:23 +00:00
|
|
|
The Primary to Sideband Bridge is used to access various peripherals
|
2019-12-07 04:41:55 +00:00
|
|
|
through memory-mapped I/O in a large chunk of PCI space. The space is
|
|
|
|
|
segmented into different channels and peripherals are accessed by
|
|
|
|
|
device-specific means within those channels. Devices should be added
|
|
|
|
|
in the device tree as subnodes of the p2sb.
|
|
|
|
|
|
|
|
|
|
config TPL_P2SB
|
2020-07-01 11:37:23 +00:00
|
|
|
bool "Intel Primary to Sideband Bridge in TPL"
|
2022-05-10 16:51:47 +00:00
|
|
|
depends on TPL_MISC && (X86 || SANDBOX)
|
2019-12-07 04:41:55 +00:00
|
|
|
help
|
2020-07-01 11:37:23 +00:00
|
|
|
The Primary to Sideband Bridge is used to access various peripherals
|
2019-12-07 04:41:55 +00:00
|
|
|
through memory-mapped I/O in a large chunk of PCI space. The space is
|
|
|
|
|
segmented into different channels and peripherals are accessed by
|
|
|
|
|
device-specific means within those channels. Devices should be added
|
|
|
|
|
in the device tree as subnodes of the p2sb.
|
|
|
|
|
|
2016-01-22 02:43:31 +00:00
|
|
|
config PWRSEQ
|
|
|
|
|
bool "Enable power-sequencing drivers"
|
|
|
|
|
depends on DM
|
|
|
|
|
help
|
|
|
|
|
Power-sequencing drivers provide support for controlling power for
|
|
|
|
|
devices. They are typically referenced by a phandle from another
|
|
|
|
|
device. When the device is started up, its power sequence can be
|
|
|
|
|
initiated.
|
|
|
|
|
|
|
|
|
|
config SPL_PWRSEQ
|
|
|
|
|
bool "Enable power-sequencing drivers for SPL"
|
2022-05-10 16:51:47 +00:00
|
|
|
depends on SPL_MISC && PWRSEQ
|
2016-01-22 02:43:31 +00:00
|
|
|
help
|
|
|
|
|
Power-sequencing drivers provide support for controlling power for
|
|
|
|
|
devices. They are typically referenced by a phandle from another
|
|
|
|
|
device. When the device is started up, its power sequence can be
|
|
|
|
|
initiated.
|
|
|
|
|
|
2015-03-12 10:22:46 +00:00
|
|
|
config PCA9551_LED
|
|
|
|
|
bool "Enable PCA9551 LED driver"
|
|
|
|
|
help
|
|
|
|
|
Enable driver for PCA9551 LED controller. This controller
|
|
|
|
|
is connected via I2C. So I2C needs to be enabled.
|
|
|
|
|
|
|
|
|
|
config PCA9551_I2C_ADDR
|
|
|
|
|
hex "I2C address of PCA9551 LED controller"
|
|
|
|
|
depends on PCA9551_LED
|
|
|
|
|
default 0x60
|
|
|
|
|
help
|
|
|
|
|
The I2C address of the PCA9551 LED controller.
|
2015-06-23 21:39:13 +00:00
|
|
|
|
2018-05-17 13:24:06 +00:00
|
|
|
config STM32MP_FUSE
|
|
|
|
|
bool "Enable STM32MP fuse wrapper providing the fuse API"
|
|
|
|
|
depends on ARCH_STM32MP && MISC
|
|
|
|
|
default y if CMD_FUSE
|
|
|
|
|
help
|
|
|
|
|
If you say Y here, you will get support for the fuse API (OTP)
|
|
|
|
|
for STM32MP architecture.
|
|
|
|
|
This API is needed for CMD_FUSE.
|
|
|
|
|
|
2017-09-13 16:00:08 +00:00
|
|
|
config STM32_RCC
|
|
|
|
|
bool "Enable RCC driver for the STM32 SoC's family"
|
2020-05-06 12:02:42 +00:00
|
|
|
depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
|
2017-09-13 16:00:08 +00:00
|
|
|
help
|
|
|
|
|
Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
|
|
|
|
|
block) is responsible of the management of the clock and reset
|
|
|
|
|
generation.
|
|
|
|
|
This driver is similar to an MFD driver in the Linux kernel.
|
|
|
|
|
|
2016-09-13 16:45:57 +00:00
|
|
|
config TEGRA_CAR
|
|
|
|
|
bool "Enable support for the Tegra CAR driver"
|
|
|
|
|
depends on TEGRA_NO_BPMP
|
|
|
|
|
help
|
|
|
|
|
The Tegra CAR (Clock and Reset Controller) is a HW module that
|
|
|
|
|
controls almost all clocks and resets in a Tegra SoC.
|
|
|
|
|
|
2016-08-08 15:41:34 +00:00
|
|
|
config TEGRA186_BPMP
|
|
|
|
|
bool "Enable support for the Tegra186 BPMP driver"
|
|
|
|
|
depends on TEGRA186
|
|
|
|
|
help
|
|
|
|
|
The Tegra BPMP (Boot and Power Management Processor) is a separate
|
|
|
|
|
auxiliary CPU embedded into Tegra to perform power management work,
|
|
|
|
|
and controls related features such as clocks, resets, power domains,
|
|
|
|
|
PMIC I2C bus, etc. This driver provides the core low-level
|
|
|
|
|
communication path by which feature-specific drivers (such as clock)
|
|
|
|
|
can make requests to the BPMP. This driver is similar to an MFD
|
|
|
|
|
driver in the Linux kernel.
|
|
|
|
|
|
2020-12-23 15:11:18 +00:00
|
|
|
config TEST_DRV
|
|
|
|
|
bool "Enable support for test drivers"
|
|
|
|
|
default y if SANDBOX
|
|
|
|
|
help
|
|
|
|
|
This enables drivers and uclasses that provides a way of testing the
|
|
|
|
|
operations of memory allocation and driver/uclass methods in driver
|
|
|
|
|
model. This should only be enabled for testing as it is not useful for
|
|
|
|
|
anything else.
|
|
|
|
|
|
2022-04-10 04:27:14 +00:00
|
|
|
config USB_HUB_USB251XB
|
|
|
|
|
tristate "USB251XB Hub Controller Configuration Driver"
|
|
|
|
|
depends on I2C
|
|
|
|
|
help
|
|
|
|
|
This option enables support for configuration via SMBus of the
|
|
|
|
|
Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration
|
|
|
|
|
parameters may be set in devicetree or platform data.
|
|
|
|
|
Say Y or M here if you need to configure such a device via SMBus.
|
|
|
|
|
|
2018-08-06 19:26:50 +00:00
|
|
|
config TWL4030_LED
|
|
|
|
|
bool "Enable TWL4030 LED controller"
|
|
|
|
|
help
|
|
|
|
|
Enable this to add support for the TWL4030 LED controller.
|
|
|
|
|
|
2016-01-19 13:05:10 +00:00
|
|
|
config WINBOND_W83627
|
|
|
|
|
bool "Enable Winbond Super I/O driver"
|
|
|
|
|
help
|
|
|
|
|
If you say Y here, you will get support for the Winbond
|
|
|
|
|
W83627 Super I/O driver. This can be used to enable the
|
|
|
|
|
legacy UART or other devices in the Winbond Super IO chips
|
|
|
|
|
on X86 platforms.
|
|
|
|
|
|
2016-05-23 02:37:14 +00:00
|
|
|
config QFW
|
|
|
|
|
bool
|
|
|
|
|
help
|
2021-03-19 07:21:40 +00:00
|
|
|
Hidden option to enable QEMU fw_cfg interface and uclass. This will
|
|
|
|
|
be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
|
|
|
|
|
|
|
|
|
|
config QFW_PIO
|
|
|
|
|
bool
|
|
|
|
|
depends on QFW
|
|
|
|
|
help
|
|
|
|
|
Hidden option to enable PIO QEMU fw_cfg interface. This will be
|
|
|
|
|
selected by the appropriate QEMU board.
|
2016-05-23 02:37:14 +00:00
|
|
|
|
2021-03-19 07:21:42 +00:00
|
|
|
config QFW_MMIO
|
|
|
|
|
bool
|
|
|
|
|
depends on QFW
|
|
|
|
|
help
|
|
|
|
|
Hidden option to enable MMIO QEMU fw_cfg interface. This will be
|
|
|
|
|
selected by the appropriate QEMU board.
|
|
|
|
|
|
2016-06-22 13:14:16 +00:00
|
|
|
config I2C_EEPROM
|
|
|
|
|
bool "Enable driver for generic I2C-attached EEPROMs"
|
|
|
|
|
depends on MISC
|
|
|
|
|
help
|
|
|
|
|
Enable a generic driver for EEPROMs attached via I2C.
|
2017-08-13 14:00:28 +00:00
|
|
|
|
2017-09-06 05:08:14 +00:00
|
|
|
|
|
|
|
|
config SPL_I2C_EEPROM
|
|
|
|
|
bool "Enable driver for generic I2C-attached EEPROMs for SPL"
|
2022-05-10 16:51:47 +00:00
|
|
|
depends on SPL_MISC
|
2017-09-06 05:08:14 +00:00
|
|
|
help
|
|
|
|
|
This option is an SPL-variant of the I2C_EEPROM option.
|
|
|
|
|
See the help of I2C_EEPROM for details.
|
|
|
|
|
|
2017-08-13 14:00:28 +00:00
|
|
|
config SYS_I2C_EEPROM_ADDR
|
|
|
|
|
hex "Chip address of the EEPROM device"
|
2021-08-17 21:59:45 +00:00
|
|
|
depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
|
2017-08-13 14:00:28 +00:00
|
|
|
default 0
|
|
|
|
|
|
2021-08-17 21:59:45 +00:00
|
|
|
if I2C_EEPROM
|
2017-08-13 14:00:28 +00:00
|
|
|
|
|
|
|
|
config SYS_I2C_EEPROM_ADDR_OVERFLOW
|
|
|
|
|
hex "EEPROM Address Overflow"
|
2021-12-11 19:55:47 +00:00
|
|
|
default 0x0
|
2017-08-13 14:00:28 +00:00
|
|
|
help
|
|
|
|
|
EEPROM chips that implement "address overflow" are ones
|
|
|
|
|
like Catalyst 24WC04/08/16 which has 9/10/11 bits of
|
|
|
|
|
address and the extra bits end up in the "chip address" bit
|
|
|
|
|
slots. This makes a 24WC08 (1Kbyte) chip look like four 256
|
|
|
|
|
byte chips.
|
|
|
|
|
|
|
|
|
|
endif
|
|
|
|
|
|
2018-04-27 12:53:33 +00:00
|
|
|
config GDSYS_RXAUI_CTRL
|
|
|
|
|
bool "Enable gdsys RXAUI control driver"
|
|
|
|
|
depends on MISC
|
|
|
|
|
help
|
|
|
|
|
Support gdsys FPGA's RXAUI control.
|
2018-07-31 12:24:15 +00:00
|
|
|
|
|
|
|
|
config GDSYS_IOEP
|
|
|
|
|
bool "Enable gdsys IOEP driver"
|
|
|
|
|
depends on MISC
|
|
|
|
|
help
|
|
|
|
|
Support gdsys FPGA's IO endpoint driver.
|
2018-08-06 08:23:46 +00:00
|
|
|
|
|
|
|
|
config MPC83XX_SERDES
|
|
|
|
|
bool "Enable MPC83xx serdes driver"
|
|
|
|
|
depends on MISC
|
|
|
|
|
help
|
|
|
|
|
Support for serdes found on MPC83xx SoCs.
|
|
|
|
|
|
2018-07-06 08:28:03 +00:00
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config FS_LOADER
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bool "Enable loader driver for file system"
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help
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This is file system generic loader which can be used to load
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the file image from the storage into target such as memory.
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The consumer driver would then use this loader to program whatever,
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ie. the FPGA device.
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2022-01-27 12:16:53 +00:00
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config SPL_FS_LOADER
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bool "Enable loader driver for file system"
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2022-05-10 16:51:47 +00:00
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depends on SPL
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2022-01-27 12:16:53 +00:00
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help
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This is file system generic loader which can be used to load
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the file image from the storage into target such as memory.
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The consumer driver would then use this loader to program whatever,
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ie. the FPGA device.
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2018-10-04 07:00:54 +00:00
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config GDSYS_SOC
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bool "Enable gdsys SOC driver"
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depends on MISC
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help
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Support for gdsys IHS SOC, a simple bus associated with each gdsys
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IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
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register maps are contained within the FPGA's register map.
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2018-10-04 07:00:55 +00:00
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config IHS_FPGA
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bool "Enable IHS FPGA driver"
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depends on MISC
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help
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Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
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gdsys devices, which supply the majority of the functionality offered
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by the devices. This driver supports both CON and CPU variants of the
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devices, depending on the device tree entry.
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2020-02-14 09:18:15 +00:00
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config ESM_K3
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bool "Enable K3 ESM driver"
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depends on ARCH_K3
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help
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Support ESM (Error Signaling Module) on TI K3 SoCs.
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2018-10-04 07:00:55 +00:00
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2019-10-09 09:23:39 +00:00
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config MICROCHIP_FLEXCOM
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bool "Enable Microchip Flexcom driver"
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depends on MISC
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help
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The Atmel Flexcom is just a wrapper which embeds a SPI controller,
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an I2C controller and an USART.
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Only one function can be used at a time and is chosen at boot time
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according to the device tree.
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2019-10-24 09:30:46 +00:00
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config K3_AVS0
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depends on ARCH_K3 && SPL_DM_REGULATOR
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bool "AVS class 0 support for K3 devices"
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help
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K3 devices have the optimized voltage values for the main voltage
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domains stored in efuse within the VTM IP. This driver reads the
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optimized voltage from the efuse, so that it can be programmed
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to the PMIC on board.
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2020-02-14 09:18:16 +00:00
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config ESM_PMIC
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bool "Enable PMIC ESM driver"
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depends on DM_PMIC
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help
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Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
|
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typically to reboot the board in error condition.
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|
2021-12-11 19:55:49 +00:00
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config FSL_IFC
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bool
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|
2022-02-25 12:36:24 +00:00
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|
|
config SL28CPLD
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bool "Enable Kontron sl28cpld multi-function driver"
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|
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depends on DM_I2C
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help
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Support for the Kontron sl28cpld management controller. This is
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|
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the base driver which provides common access methods for the
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sub-drivers.
|
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|
2015-07-25 17:46:26 +00:00
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endmenu
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