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drivers: hierarchize drivers Kconfig menu The menuconfig for drivers are getting more and more cluttered and unreadable because too many entries are displayed in a single flat menu. Use hierarchic menu for each category. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Update to apply again in a few places, drop USB hunk] Signed-off-by: Tom Rini <trini@konsulko.com>
2015-07-25 17:46:26 +00:00
#
# Multifunction miscellaneous devices
#
menu "Multifunction device drivers"
dm: implement a Miscellaneous uclass Implement a Miscellaneous uclass with generic read or write operations. This class is used only for those do not fit other more general classes. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-07 12:20:51 +00:00
config MISC
bool "Enable Driver Model for Misc drivers"
depends on DM
help
Enable driver model for miscellaneous devices. This class is
used only for those do not fit other more general classes. A
set of generic read, write and ioctl methods may be used to
access the device.
nios2: convert altera sysid to driver model Convert altera sysid to driver model with misc uclass. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-10-14 00:43:31 +00:00
config ALTERA_SYSID
bool "Altera Sysid support"
depends on MISC
help
Select this to enable a sysid for Altera devices. Please find
details on the "Embedded Peripherals IP User Guide" of Altera.
drivers/misc: Add basic support for ATSHA204A Crypto module This module can be found on the Turris Omnia board connected via the I2C interface. Among some cryptographic functions, the chip has a 512 bit One Time Programmable memory, 88 byte configuration memory and 512 byte general purpose memory. The Turris Omnia stores serial number and device MAC address in the OTP memory. This commit adds basic support for reading the EEPROM and also exposes the chips Random Number Generator. The driver is based on code by Josh Datko, Cryptotronix, jbd@cryptotronix.com and also Tomas Hlavacek, CZ.NIC, tomas.hlavacek@nic.cz Signed-off-by: Tomas Hlavacek <tomas.hlavacek@nic.cz> Signed-off-by: Marek Behun <marek.behun@nic.cz> create mode 100644 drivers/misc/atsha204a-i2c.c create mode 100644 include/atsha204a-i2c.h Signed-off-by: Stefan Roese <sr@denx.de>
2017-06-09 17:28:44 +00:00
config ATSHA204A
bool "Support for Atmel ATSHA204A module"
depends on MISC
help
Enable support for I2C connected Atmel's ATSHA204A
CryptoAuthentication module found for example on the Turris Omnia
board.
rockchip: efuse: add (misc) driver for RK3399 non-secure efuse block This adds a simple driver for reading the efuse block of the RK3399. It should be easy enough to add drivers for other devices (e.g. the RK3328, RK3368, etc.) by passing the device details via driver_data. Unlike the kernel driver (using the nvmem subsystem), we don't expose the efuse as multiple named cells, but rather as a linear memory that can be read using misc_read(...). The primary use case (as of today) is the generation of a 'serial#' (and a 'cpuid#') environment variable for the RK3399-Q7 (Puma) system-on-module. Note that this adds a debug-only (i.e. only if DEBUG is defined) command 'rk3399_dump_efuses' that dumps the efuse block's content. N.B.: The name 'rk3399_dump_efuses' was intentionally chosen to include a SoC-name (together with a comment in the function) to remind whoever adds support for additional SoCs that this function currently makes assumptions regarding the size of the fuse-box based on the RK3399. The hope is that the function is adjusted to reflect any changes resulting from generalising the driver for multiple SoCs and is then renamed. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-05 17:21:38 +00:00
config ROCKCHIP_EFUSE
bool "Rockchip e-fuse support"
depends on MISC
help
Enable (read-only) access for the e-fuse block found in Rockchip
SoCs: accesses can either be made using byte addressing and a length
or through child-nodes that are generated based on the e-fuse map
retrieved from the DTS.
This driver currently supports the RK3399 only, but can easily be
extended (by porting the read function from the Linux kernel sources)
to support other recent Rockchip devices.
dm: cros_ec: Convert to Kconfig Since both I2C and SPI are converted to Kconfig, we can convert cros_ec to Kconfig for these buses. LPC will need to wait until driver mode PCI is available. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-13 19:20:47 +00:00
config CMD_CROS_EC
bool "Enable crosec command"
depends on CROS_EC
help
Enable command-line access to the Chrome OS EC (Embedded
Controller). This provides the 'crosec' command which has
a number of sub-commands for performing EC tasks such as
updating its flash, accessing a small saved context area
and talking to the I2C bus behind the EC (if there is one).
config CROS_EC
bool "Enable Chrome OS EC"
help
Enable access to the Chrome OS EC. This is a separate
microcontroller typically available on a SPI bus on Chromebooks. It
provides access to the keyboard, some internal storage and may
control access to the battery and main PMIC depending on the
device. You can use the 'crosec' command to access it.
config CROS_EC_I2C
bool "Enable Chrome OS EC I2C driver"
depends on CROS_EC
help
Enable I2C access to the Chrome OS EC. This is used on older
ARM Chromebooks such as snow and spring before the standard bus
changed to SPI. The EC will accept commands across the I2C using
a special message protocol, and provide responses.
config CROS_EC_LPC
bool "Enable Chrome OS EC LPC driver"
depends on CROS_EC
help
Enable I2C access to the Chrome OS EC. This is used on x86
Chromebooks such as link and falco. The keyboard is provided
through a legacy port interface, so on x86 machines the main
function of the EC is power and thermal management.
sandbox: cros_ec: Add Kconfig for sandbox EC config Move CONFIG_CROS_EC_SANDBOX to Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-26 15:29:40 +00:00
config CROS_EC_SANDBOX
bool "Enable Chrome OS EC sandbox driver"
depends on CROS_EC && SANDBOX
help
Enable a sandbox emulation of the Chrome OS EC. This supports
keyboard (use the -l flag to enable the LCD), verified boot context,
EC flash read/write/erase support and a few other things. It is
enough to perform a Chrome OS verified boot on sandbox.
dm: cros_ec: Convert to Kconfig Since both I2C and SPI are converted to Kconfig, we can convert cros_ec to Kconfig for these buses. LPC will need to wait until driver mode PCI is available. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-13 19:20:47 +00:00
config CROS_EC_SPI
bool "Enable Chrome OS EC SPI driver"
depends on CROS_EC
help
Enable SPI access to the Chrome OS EC. This is used on newer
ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
provides a faster and more robust interface than I2C but the bugs
are less interesting.
Convert CONFIG_DS4510 to Kconfig This converts the following to Kconfig: CONFIG_DS4510 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2017-05-17 09:25:02 +00:00
config DS4510
bool "Enable support for DS4510 CPU supervisor"
help
Enable support for the Maxim DS4510 CPU supervisor. It has an
integrated 64-byte EEPROM, four programmable non-volatile I/O pins
and a configurable timer for the supervisor function. The device is
connected over I2C.
driver: misc: correct Kconfig entry Should use FSL_SEC_MON, not CONFIG_FSL_SEC_MON as Kconfig entry. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:41:33 +00:00
config FSL_SEC_MON
fsl_sec_mon: Add driver for Security Monitor block of Freescale The Security Monitor is the SOC’s central reporting point for security-relevant events such as the success or failure of boot software validation and the detection of potential security compromises. The API's for transition of Security states have been added which will be used in case of SECURE BOOT. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-27 04:14:22 +00:00
bool "Enable FSL SEC_MON Driver"
help
Freescale Security Monitor block is responsible for monitoring
system states.
Security Monitor can be transitioned on any security failures,
like software violations or hardware security violations.
misc: led: Add PCA9551 LED driver This patch adds a driver for the PCA9551 LED controller. Originated-by: Timo Herbrecher <t.herbrecher@gateware.de> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Cc: Fabio Estevam <festevam@gmail.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-03-12 10:22:46 +00:00
driver: misc: add MXC_OCOTP Kconfig entry Add MXC_OCOTP Kconfig entry. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-08-27 06:49:05 +00:00
config MXC_OCOTP
bool "Enable MXC OCOTP Driver"
help
If you say Y here, you will get support for the One Time
Programmable memory pages that are stored on the some
Freescale i.MX processors.
misc: Add simple driver for some Nuvoton NCT6102D devices This simple driver provides some functions to control some of the integrated devices. The watchdog is enabled per default. This driver adds a function to disable the watchdog. Also the internal legacy UART (io address 0x3f8/0x2f8) is enabled per default. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org>
2016-07-19 05:45:46 +00:00
config NUVOTON_NCT6102D
bool "Enable Nuvoton NCT6102D Super I/O driver"
help
If you say Y here, you will get support for the Nuvoton
NCT6102D Super I/O driver. This can be used to enable or
disable the legacy UART, the watchdog or other devices
in the Nuvoton Super IO chips on X86 platforms.
dm: Add a power sequencing uclass Some devices need special sequences to be used when starting up. Add a uclass for this. Drivers can be added to provide specific features as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-22 02:43:31 +00:00
config PWRSEQ
bool "Enable power-sequencing drivers"
depends on DM
help
Power-sequencing drivers provide support for controlling power for
devices. They are typically referenced by a phandle from another
device. When the device is started up, its power sequence can be
initiated.
config SPL_PWRSEQ
bool "Enable power-sequencing drivers for SPL"
depends on PWRSEQ
help
Power-sequencing drivers provide support for controlling power for
devices. They are typically referenced by a phandle from another
device. When the device is started up, its power sequence can be
initiated.
misc: led: Add PCA9551 LED driver This patch adds a driver for the PCA9551 LED controller. Originated-by: Timo Herbrecher <t.herbrecher@gateware.de> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Cc: Fabio Estevam <festevam@gmail.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-03-12 10:22:46 +00:00
config PCA9551_LED
bool "Enable PCA9551 LED driver"
help
Enable driver for PCA9551 LED controller. This controller
is connected via I2C. So I2C needs to be enabled.
config PCA9551_I2C_ADDR
hex "I2C address of PCA9551 LED controller"
depends on PCA9551_LED
default 0x60
help
The I2C address of the PCA9551 LED controller.
dm: Add a system reset uclass It is common for system reset to be available at multiple levels in modern hardware. For example, an SoC may provide a reset option, and a board may provide its own reset for reasons of security or thoroughness. It is useful to be able to model this hardware without hard-coding the behaviour in the SoC or board. Also there is a distinction sometimes between resetting just the CPU (leaving GPIO state alone) and resetting all the PMICs, just cutting power. To achieve this, add a simple system reset uclass. It allows multiple devices to provide reset functionality and provides a way to walk through them, requesting a particular reset type until is it provided. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:13 +00:00
stm32mp1: add FUSE command support Add support of fuse command (read/write/program/sense) on bank 0 to access to BSEC SAFMEM (4096 OTP bits). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-17 13:24:06 +00:00
config STM32MP_FUSE
bool "Enable STM32MP fuse wrapper providing the fuse API"
depends on ARCH_STM32MP && MISC
default y if CMD_FUSE
help
If you say Y here, you will get support for the fuse API (OTP)
for STM32MP architecture.
This API is needed for CMD_FUSE.
dm: misc: add stm32 rcc driver This patch adds the support of reset and clock control block (rcc) found on STM32 SoCs. This driver is similar to a MFD linux driver. This driver supports currently STM32H7 only. STM32F4 and STM32F7 will be migrated to this rcc MFD driver in the future to uniformize all STM32 SoCs already upstreamed. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-13 16:00:08 +00:00
config STM32_RCC
bool "Enable RCC driver for the STM32 SoC's family"
misc: stm32: Add STM32MP1 support Following next kernel rcc bindings, we must use a MFD RCC driver which is able to bind both clock and reset drivers. We can reuse and adapt RCC MFD driver already available for MCU SoCs (F4/F7/H7). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-09 13:17:20 +00:00
depends on (STM32 || ARCH_STM32MP) && MISC
dm: misc: add stm32 rcc driver This patch adds the support of reset and clock control block (rcc) found on STM32 SoCs. This driver is similar to a MFD linux driver. This driver supports currently STM32H7 only. STM32F4 and STM32F7 will be migrated to this rcc MFD driver in the future to uniformize all STM32 SoCs already upstreamed. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-13 16:00:08 +00:00
help
Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
block) is responsible of the management of the clock and reset
generation.
This driver is similar to an MFD driver in the Linux kernel.
misc: implement Tegra CAR core driver The Tegra CAR (Clock And Reset) module provides control of most clocks and reset signals within the Tegra SoC. This change implements a driver for this module. However, since the module implements multiple kinds of services (clocks, resets, perhaps more), all this driver does is bind various sub-devices, which in turn provide the real services. This driver is essentially an "MFD" (Multi-Function Device) in Linux kernel speak. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-09-13 16:45:57 +00:00
config TEGRA_CAR
bool "Enable support for the Tegra CAR driver"
depends on TEGRA_NO_BPMP
help
The Tegra CAR (Clock and Reset Controller) is a HW module that
controls almost all clocks and resets in a Tegra SoC.
misc: add Tegra BPMP driver The Tegra BPMP (Boot and Power Management Processor) is a separate auxiliary CPU embedded into Tegra to perform power management work, and controls related features such as clocks, resets, power domains, PMIC I2C bus, etc. This driver provides the core low-level communication path by which feature-specific drivers (such as clock) can make requests to the BPMP. This driver is similar to an MFD driver in the Linux kernel. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-08 15:41:34 +00:00
config TEGRA186_BPMP
bool "Enable support for the Tegra186 BPMP driver"
depends on TEGRA186
help
The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work,
and controls related features such as clocks, resets, power domains,
PMIC I2C bus, etc. This driver provides the core low-level
communication path by which feature-specific drivers (such as clock)
can make requests to the BPMP. This driver is similar to an MFD
driver in the Linux kernel.
Convert CONFIG_TWL4030_LED et al to Kconfig This converts the following to Kconfig: CONFIG_TWL4030_LED CONFIG_TWL4030_INPUT This also removes dead references to: CONFIG_TWL4030_KEYPAD Signed-off-by: Adam Ford <aford173@gmail.com>
2018-08-06 19:26:50 +00:00
config TWL4030_LED
bool "Enable TWL4030 LED controller"
help
Enable this to add support for the TWL4030 LED controller.
misc: Add simple driver to enable the legacy UART on Winbond Super IO chips On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8) are provided by a superio chip connected to the LPC bus. We must program the superio chip so that serial ports are available for us. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 13:05:10 +00:00
config WINBOND_W83627
bool "Enable Winbond Super I/O driver"
help
If you say Y here, you will get support for the Winbond
W83627 Super I/O driver. This can be used to enable the
legacy UART or other devices in the Winbond Super IO chips
on X86 platforms.
x86: qemu: split qfw command interface and qfw core This patch splits qfw command interface and qfw core function into two files, and introduces a new Kconfig option (CONFIG_QFW) for qfw core. Now when qfw command interface is enabled, it will automatically select qfw core. This patch also makes the ACPI table generation select CONFIG_QFW. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 02:37:14 +00:00
config QFW
bool
help
Hidden option to enable QEMU fw_cfg interface. This will be selected by
cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h] Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 02:37:17 +00:00
either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
x86: qemu: split qfw command interface and qfw core This patch splits qfw command interface and qfw core function into two files, and introduces a new Kconfig option (CONFIG_QFW) for qfw core. Now when qfw command interface is enabled, it will automatically select qfw core. This patch also makes the ACPI table generation select CONFIG_QFW. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 02:37:14 +00:00
i2c_eeprom: Add reading support This patch implements the reading functionality for the generic I2C EEPROM driver, which was just a non-functional stub until now. Since the page size will be of importance for the writing support, we add suitable members to the private data structure to keep track of it. Compatibility strings for a range of at24c* chips are added. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2016-06-22 13:14:16 +00:00
config I2C_EEPROM
bool "Enable driver for generic I2C-attached EEPROMs"
depends on MISC
help
Enable a generic driver for EEPROMs attached via I2C.
Kconfig: Add EEPROM options to Kconfig when I2C_EEPROM is set Add the following options to drivers/misc/Kconfig: SYS_I2C_EEPROM_ADDR SYS_I2C_EEPROM_BUS SYS_EEPROM_SIZE SYS_EEPROM_PAGE_WRITE_BITS SYS_EEPROM_PAGE_WRITE_DELAY_MS SYS_I2C_EEPROM_ADDR_LEN SYS_I2C_EEPROM_ADDR_OVERFLOW This does not migrate any boards, but provides a foundations for those who want/need these options Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Migrate uniphier] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-13 14:00:28 +00:00
misc: Kconfig: Add SPL_I2C_EEPROM option This option is an SPL-variant of the I2C_EEPROM option to enable the driver for generic I2C-attached EEPROMs for SPL. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-06 05:08:14 +00:00
config SPL_I2C_EEPROM
bool "Enable driver for generic I2C-attached EEPROMs for SPL"
depends on MISC && SPL && SPL_DM
help
This option is an SPL-variant of the I2C_EEPROM option.
See the help of I2C_EEPROM for details.
i2c: Added Kconfig support for CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET This patch added Kconfig support for CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET and enabled it in respective defconfig. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-02-16 13:37:21 +00:00
config ZYNQ_GEM_I2C_MAC_OFFSET
hex "Set the I2C MAC offset"
default 0x0
help
Set the MAC offset for i2C.
Kconfig: Add EEPROM options to Kconfig when I2C_EEPROM is set Add the following options to drivers/misc/Kconfig: SYS_I2C_EEPROM_ADDR SYS_I2C_EEPROM_BUS SYS_EEPROM_SIZE SYS_EEPROM_PAGE_WRITE_BITS SYS_EEPROM_PAGE_WRITE_DELAY_MS SYS_I2C_EEPROM_ADDR_LEN SYS_I2C_EEPROM_ADDR_OVERFLOW This does not migrate any boards, but provides a foundations for those who want/need these options Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Migrate uniphier] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-13 14:00:28 +00:00
if I2C_EEPROM
config SYS_I2C_EEPROM_ADDR
hex "Chip address of the EEPROM device"
default 0
config SYS_I2C_EEPROM_BUS
int "I2C bus of the EEPROM device."
default 0
config SYS_EEPROM_SIZE
int "Size in bytes of the EEPROM device"
default 256
config SYS_EEPROM_PAGE_WRITE_BITS
int "Number of bits used to address bytes in a single page"
default 0
help
The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
A 64 byte page, for example would require six bits.
config SYS_EEPROM_PAGE_WRITE_DELAY_MS
int "Number of milliseconds to delay between page writes"
default 0
config SYS_I2C_EEPROM_ADDR_LEN
int "Length in bytes of the EEPROM memory array address"
default 1
help
Note: This is NOT the chip address length!
config SYS_I2C_EEPROM_ADDR_OVERFLOW
hex "EEPROM Address Overflow"
default 0
help
EEPROM chips that implement "address overflow" are ones
like Catalyst 24WC04/08/16 which has 9/10/11 bits of
address and the extra bits end up in the "chip address" bit
slots. This makes a 24WC08 (1Kbyte) chip look like four 256
byte chips.
endif
gdsys: drivers: Add gdsys_rxaui_ctrl driver Add a driver for RXAUI control on IHS FPGAs. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-27 12:53:33 +00:00
config GDSYS_RXAUI_CTRL
bool "Enable gdsys RXAUI control driver"
depends on MISC
help
Support gdsys FPGA's RXAUI control.
misc: Add gdsys_ioep driver Add driver for the IHS IO endpoint on IHS FPGAs. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-07-31 12:24:15 +00:00
config GDSYS_IOEP
bool "Enable gdsys IOEP driver"
depends on MISC
help
Support gdsys FPGA's IO endpoint driver.
misc: Add MPC83xx serdes driver Add a driver to configure the SerDes (Serializer/Deserializer) lanes on the MPC83xx architecture. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-06 08:23:46 +00:00
config MPC83XX_SERDES
bool "Enable MPC83xx serdes driver"
depends on MISC
help
Support for serdes found on MPC83xx SoCs.
drivers: hierarchize drivers Kconfig menu The menuconfig for drivers are getting more and more cluttered and unreadable because too many entries are displayed in a single flat menu. Use hierarchic menu for each category. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Update to apply again in a few places, drop USB hunk] Signed-off-by: Tom Rini <trini@konsulko.com>
2015-07-25 17:46:26 +00:00
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