mirror of
https://github.com/AsahiLinux/u-boot
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621 lines
21 KiB
Text
621 lines
21 KiB
Text
#
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# Multifunction miscellaneous devices
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#
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menu "Multifunction device drivers"
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config MISC
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bool "Enable Driver Model for Misc drivers"
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depends on DM
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help
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Enable driver model for miscellaneous devices. This class is
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used only for those do not fit other more general classes. A
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set of generic read, write and ioctl methods may be used to
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access the device.
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config SPL_MISC
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bool "Enable Driver Model for Misc drivers in SPL"
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depends on SPL_DM
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default MISC
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help
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Enable driver model for miscellaneous devices. This class is
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used only for those do not fit other more general classes. A
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set of generic read, write and ioctl methods may be used to
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access the device.
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config TPL_MISC
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bool "Enable Driver Model for Misc drivers in TPL"
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depends on TPL_DM
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default MISC
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help
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Enable driver model for miscellaneous devices. This class is
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used only for those do not fit other more general classes. A
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set of generic read, write and ioctl methods may be used to
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access the device.
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config VPL_MISC
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bool "Enable Driver Model for Misc drivers in VPL"
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depends on VPL_DM
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default MISC
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help
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Enable driver model for miscellaneous devices. This class is
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used only for those do not fit other more general classes. A
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set of generic read, write and ioctl methods may be used to
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access the device.
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config NVMEM
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bool "NVMEM support"
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help
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This adds support for a common interface to different types of
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non-volatile memory. Consumers can use nvmem-cells properties to look
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up hardware configuration data such as MAC addresses and calibration
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settings.
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config SPL_NVMEM
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bool "NVMEM support in SPL"
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help
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This adds support for a common interface to different types of
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non-volatile memory. Consumers can use nvmem-cells properties to look
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up hardware configuration data such as MAC addresses and calibration
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settings.
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config ALTERA_SYSID
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bool "Altera Sysid support"
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depends on MISC
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help
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Select this to enable a sysid for Altera devices. Please find
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details on the "Embedded Peripherals IP User Guide" of Altera.
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config ATSHA204A
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bool "Support for Atmel ATSHA204A module"
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select BITREVERSE
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depends on MISC
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help
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Enable support for I2C connected Atmel's ATSHA204A
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CryptoAuthentication module found for example on the Turris Omnia
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board.
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config GATEWORKS_SC
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bool "Gateworks System Controller Support"
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depends on MISC
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help
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Enable access for the Gateworks System Controller used on Gateworks
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boards to provide a boot watchdog, power control, temperature monitor,
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voltage ADCs, and EEPROM.
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config ROCKCHIP_EFUSE
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bool "Rockchip e-fuse support"
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depends on MISC
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help
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Enable (read-only) access for the e-fuse block found in Rockchip
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SoCs: accesses can either be made using byte addressing and a length
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or through child-nodes that are generated based on the e-fuse map
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retrieved from the DTS.
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This driver currently supports the RK3399 only, but can easily be
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extended (by porting the read function from the Linux kernel sources)
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to support other recent Rockchip devices.
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config ROCKCHIP_OTP
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bool "Rockchip OTP Support"
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depends on MISC
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help
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Enable (read-only) access for the one-time-programmable memory block
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found in Rockchip SoCs: accesses can either be made using byte
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addressing and a length or through child-nodes that are generated
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based on the e-fuse map retrieved from the DTS.
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config SIFIVE_OTP
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bool "SiFive eMemory OTP driver"
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depends on MISC
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help
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Enable support for reading and writing the eMemory OTP on the
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SiFive SoCs.
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config VEXPRESS_CONFIG
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bool "Enable support for Arm Versatile Express config bus"
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depends on MISC
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help
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If you say Y here, you will get support for accessing the
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configuration bus on the Arm Versatile Express boards via
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a sysreg driver.
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config CMD_CROS_EC
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bool "Enable crosec command"
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depends on CROS_EC
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help
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Enable command-line access to the Chrome OS EC (Embedded
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Controller). This provides the 'crosec' command which has
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a number of sub-commands for performing EC tasks such as
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updating its flash, accessing a small saved context area
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and talking to the I2C bus behind the EC (if there is one).
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config CROS_EC
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bool "Enable Chrome OS EC"
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help
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Enable access to the Chrome OS EC. This is a separate
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microcontroller typically available on a SPI bus on Chromebooks. It
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provides access to the keyboard, some internal storage and may
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control access to the battery and main PMIC depending on the
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device. You can use the 'crosec' command to access it.
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config SPL_CROS_EC
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bool "Enable Chrome OS EC in SPL"
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depends on SPL_MISC
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help
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Enable access to the Chrome OS EC in SPL. This is a separate
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microcontroller typically available on a SPI bus on Chromebooks. It
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provides access to the keyboard, some internal storage and may
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control access to the battery and main PMIC depending on the
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device. You can use the 'crosec' command to access it.
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config TPL_CROS_EC
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bool "Enable Chrome OS EC in TPL"
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depends on TPL_MISC
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help
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Enable access to the Chrome OS EC in TPL. This is a separate
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microcontroller typically available on a SPI bus on Chromebooks. It
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provides access to the keyboard, some internal storage and may
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control access to the battery and main PMIC depending on the
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device. You can use the 'crosec' command to access it.
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config VPL_CROS_EC
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bool "Enable Chrome OS EC in VPL"
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depends on VPL_MISC
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help
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Enable access to the Chrome OS EC in VPL. This is a separate
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microcontroller typically available on a SPI bus on Chromebooks. It
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provides access to the keyboard, some internal storage and may
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control access to the battery and main PMIC depending on the
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device. You can use the 'crosec' command to access it.
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config CROS_EC_I2C
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bool "Enable Chrome OS EC I2C driver"
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depends on CROS_EC
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help
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Enable I2C access to the Chrome OS EC. This is used on older
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ARM Chromebooks such as snow and spring before the standard bus
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changed to SPI. The EC will accept commands across the I2C using
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a special message protocol, and provide responses.
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config CROS_EC_LPC
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bool "Enable Chrome OS EC LPC driver"
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depends on CROS_EC
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help
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Enable I2C access to the Chrome OS EC. This is used on x86
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Chromebooks such as link and falco. The keyboard is provided
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through a legacy port interface, so on x86 machines the main
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function of the EC is power and thermal management.
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config SPL_CROS_EC_LPC
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bool "Enable Chrome OS EC LPC driver in SPL"
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depends on CROS_EC && SPL_MISC
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help
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Enable I2C access to the Chrome OS EC. This is used on x86
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Chromebooks such as link and falco. The keyboard is provided
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through a legacy port interface, so on x86 machines the main
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function of the EC is power and thermal management.
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config TPL_CROS_EC_LPC
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bool "Enable Chrome OS EC LPC driver in TPL"
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depends on CROS_EC && TPL_MISC
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help
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Enable I2C access to the Chrome OS EC. This is used on x86
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Chromebooks such as link and falco. The keyboard is provided
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through a legacy port interface, so on x86 machines the main
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function of the EC is power and thermal management.
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config VPL_CROS_EC_LPC
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bool "Enable Chrome OS EC LPC driver in VPL"
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depends on CROS_EC && VPL_MISC
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help
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Enable I2C access to the Chrome OS EC. This is used on x86
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Chromebooks such as link and falco. The keyboard is provided
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through a legacy port interface, so on x86 machines the main
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function of the EC is power and thermal management.
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config CROS_EC_SANDBOX
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bool "Enable Chrome OS EC sandbox driver"
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depends on CROS_EC && SANDBOX
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help
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Enable a sandbox emulation of the Chrome OS EC. This supports
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keyboard (use the -l flag to enable the LCD), verified boot context,
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EC flash read/write/erase support and a few other things. It is
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enough to perform a Chrome OS verified boot on sandbox.
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config SPL_CROS_EC_SANDBOX
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bool "Enable Chrome OS EC sandbox driver in SPL"
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depends on SPL_CROS_EC && SANDBOX
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help
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Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
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keyboard (use the -l flag to enable the LCD), verified boot context,
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EC flash read/write/erase support and a few other things. It is
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enough to perform a Chrome OS verified boot on sandbox.
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config TPL_CROS_EC_SANDBOX
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bool "Enable Chrome OS EC sandbox driver in TPL"
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depends on TPL_CROS_EC && SANDBOX
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help
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Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
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keyboard (use the -l flag to enable the LCD), verified boot context,
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EC flash read/write/erase support and a few other things. It is
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enough to perform a Chrome OS verified boot on sandbox.
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config VPL_CROS_EC_SANDBOX
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bool "Enable Chrome OS EC sandbox driver in VPL"
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depends on VPL_CROS_EC && SANDBOX
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help
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Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
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keyboard (use the -l flag to enable the LCD), verified boot context,
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EC flash read/write/erase support and a few other things. It is
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enough to perform a Chrome OS verified boot on sandbox.
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config CROS_EC_SPI
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bool "Enable Chrome OS EC SPI driver"
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depends on CROS_EC
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help
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Enable SPI access to the Chrome OS EC. This is used on newer
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ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
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provides a faster and more robust interface than I2C but the bugs
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are less interesting.
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config DS4510
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bool "Enable support for DS4510 CPU supervisor"
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help
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Enable support for the Maxim DS4510 CPU supervisor. It has an
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integrated 64-byte EEPROM, four programmable non-volatile I/O pins
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and a configurable timer for the supervisor function. The device is
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connected over I2C.
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config FSL_SEC_MON
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bool "Enable FSL SEC_MON Driver"
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help
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Freescale Security Monitor block is responsible for monitoring
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system states.
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Security Monitor can be transitioned on any security failures,
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like software violations or hardware security violations.
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config IRQ
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bool "Interrupt controller"
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help
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This enables support for interrupt controllers, including ITSS.
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Some devices have extra features, such as Apollo Lake. The
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device has its own uclass since there are several operations
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involved.
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config JZ4780_EFUSE
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bool "Ingenic JZ4780 eFUSE support"
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depends on ARCH_JZ47XX
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help
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This selects support for the eFUSE on Ingenic JZ4780 SoCs.
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config LS2_SFP
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bool "Layerscape Security Fuse Processor"
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depends on FSL_LSCH2 || ARCH_LS1021A
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depends on MISC
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imply DM_REGULATOR
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help
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This adds support for the Security Fuse Processor found on Layerscape
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SoCs. It contains various fuses related to secure boot, including the
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Super Root Key hash, One-Time-Programmable Master Key, Debug
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Challenge/Response values, and others. Fuses are numbered according
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to their four-byte offset from the start of the bank.
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If you don't need to read/program fuses, say 'n'.
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config MXC_OCOTP
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bool "Enable MXC OCOTP Driver"
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depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
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default y
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help
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If you say Y here, you will get support for the One Time
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Programmable memory pages that are stored on the some
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Freescale i.MX processors.
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config SPL_MXC_OCOTP
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bool "Enable MXC OCOTP driver in SPL"
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depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
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default y
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help
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If you say Y here, you will get support for the One Time
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Programmable memory pages, that are stored on some
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Freescale i.MX processors, in SPL.
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config NPCM_OTP
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bool "Nnvoton NPCM BMC On-Chip OTP Memory Support"
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depends on (ARM && ARCH_NPCM)
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default n
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help
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Support NPCM BMC OTP memory (fuse).
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To compile this driver as a module, choose M here: the module
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will be called npcm_otp.
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config NUVOTON_NCT6102D
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bool "Enable Nuvoton NCT6102D Super I/O driver"
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help
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If you say Y here, you will get support for the Nuvoton
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NCT6102D Super I/O driver. This can be used to enable or
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disable the legacy UART, the watchdog or other devices
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in the Nuvoton Super IO chips on X86 platforms.
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config P2SB
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bool "Intel Primary to Sideband Bridge"
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depends on X86 || SANDBOX
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help
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This enables support for the Intel Primary to Sideband Bridge,
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abbreviated to P2SB. The P2SB is used to access various peripherals
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such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
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space. The space is segmented into different channels and peripherals
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are accessed by device-specific means within those channels. Devices
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should be added in the device tree as subnodes of the P2SB. A
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Peripheral Channel Register? (PCR) API is provided to access those
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devices - see pcr_readl(), etc.
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config SPL_P2SB
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bool "Intel Primary to Sideband Bridge in SPL"
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depends on SPL_MISC && (X86 || SANDBOX)
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help
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The Primary to Sideband Bridge is used to access various peripherals
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through memory-mapped I/O in a large chunk of PCI space. The space is
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segmented into different channels and peripherals are accessed by
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device-specific means within those channels. Devices should be added
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in the device tree as subnodes of the p2sb.
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config TPL_P2SB
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bool "Intel Primary to Sideband Bridge in TPL"
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depends on TPL_MISC && (X86 || SANDBOX)
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help
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The Primary to Sideband Bridge is used to access various peripherals
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through memory-mapped I/O in a large chunk of PCI space. The space is
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segmented into different channels and peripherals are accessed by
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device-specific means within those channels. Devices should be added
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in the device tree as subnodes of the p2sb.
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config PWRSEQ
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bool "Enable power-sequencing drivers"
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depends on DM
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help
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Power-sequencing drivers provide support for controlling power for
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devices. They are typically referenced by a phandle from another
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device. When the device is started up, its power sequence can be
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initiated.
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config SPL_PWRSEQ
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bool "Enable power-sequencing drivers for SPL"
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depends on SPL_MISC && PWRSEQ
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help
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Power-sequencing drivers provide support for controlling power for
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devices. They are typically referenced by a phandle from another
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device. When the device is started up, its power sequence can be
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initiated.
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config PCA9551_LED
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bool "Enable PCA9551 LED driver"
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help
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Enable driver for PCA9551 LED controller. This controller
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is connected via I2C. So I2C needs to be enabled.
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config PCA9551_I2C_ADDR
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hex "I2C address of PCA9551 LED controller"
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depends on PCA9551_LED
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default 0x60
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help
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The I2C address of the PCA9551 LED controller.
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config STM32MP_FUSE
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bool "Enable STM32MP fuse wrapper providing the fuse API"
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depends on ARCH_STM32MP && MISC
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default y if CMD_FUSE
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help
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If you say Y here, you will get support for the fuse API (OTP)
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for STM32MP architecture.
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This API is needed for CMD_FUSE.
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config STM32_RCC
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bool "Enable RCC driver for the STM32 SoC's family"
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depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
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help
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Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
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block) is responsible of the management of the clock and reset
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generation.
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This driver is similar to an MFD driver in the Linux kernel.
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config TEGRA_CAR
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bool "Enable support for the Tegra CAR driver"
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depends on TEGRA_NO_BPMP
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help
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The Tegra CAR (Clock and Reset Controller) is a HW module that
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controls almost all clocks and resets in a Tegra SoC.
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config TEGRA186_BPMP
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bool "Enable support for the Tegra186 BPMP driver"
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depends on TEGRA186
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help
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The Tegra BPMP (Boot and Power Management Processor) is a separate
|
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auxiliary CPU embedded into Tegra to perform power management work,
|
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and controls related features such as clocks, resets, power domains,
|
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PMIC I2C bus, etc. This driver provides the core low-level
|
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communication path by which feature-specific drivers (such as clock)
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can make requests to the BPMP. This driver is similar to an MFD
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driver in the Linux kernel.
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config TEST_DRV
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bool "Enable support for test drivers"
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default y if SANDBOX
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help
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This enables drivers and uclasses that provides a way of testing the
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operations of memory allocation and driver/uclass methods in driver
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model. This should only be enabled for testing as it is not useful for
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anything else.
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config USB_HUB_USB251XB
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tristate "USB251XB Hub Controller Configuration Driver"
|
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depends on I2C
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help
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|
This option enables support for configuration via SMBus of the
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Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration
|
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parameters may be set in devicetree or platform data.
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Say Y or M here if you need to configure such a device via SMBus.
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config TWL4030_LED
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bool "Enable TWL4030 LED controller"
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help
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Enable this to add support for the TWL4030 LED controller.
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config WINBOND_W83627
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bool "Enable Winbond Super I/O driver"
|
|
help
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If you say Y here, you will get support for the Winbond
|
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W83627 Super I/O driver. This can be used to enable the
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legacy UART or other devices in the Winbond Super IO chips
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on X86 platforms.
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config QFW
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bool
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help
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Hidden option to enable QEMU fw_cfg interface and uclass. This will
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be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
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config QFW_PIO
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bool
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depends on QFW
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help
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Hidden option to enable PIO QEMU fw_cfg interface. This will be
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selected by the appropriate QEMU board.
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config QFW_MMIO
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bool
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depends on QFW
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help
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|
Hidden option to enable MMIO QEMU fw_cfg interface. This will be
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selected by the appropriate QEMU board.
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config I2C_EEPROM
|
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bool "Enable driver for generic I2C-attached EEPROMs"
|
|
depends on MISC
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help
|
|
Enable a generic driver for EEPROMs attached via I2C.
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config SPL_I2C_EEPROM
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bool "Enable driver for generic I2C-attached EEPROMs for SPL"
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depends on SPL_MISC
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help
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This option is an SPL-variant of the I2C_EEPROM option.
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See the help of I2C_EEPROM for details.
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config SYS_I2C_EEPROM_ADDR
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hex "Chip address of the EEPROM device"
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depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
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default 0
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if I2C_EEPROM
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config SYS_I2C_EEPROM_ADDR_OVERFLOW
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hex "EEPROM Address Overflow"
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default 0x0
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help
|
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EEPROM chips that implement "address overflow" are ones
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|
like Catalyst 24WC04/08/16 which has 9/10/11 bits of
|
|
address and the extra bits end up in the "chip address" bit
|
|
slots. This makes a 24WC08 (1Kbyte) chip look like four 256
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|
byte chips.
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endif
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config GDSYS_RXAUI_CTRL
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bool "Enable gdsys RXAUI control driver"
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|
depends on MISC
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|
help
|
|
Support gdsys FPGA's RXAUI control.
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|
|
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config GDSYS_IOEP
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bool "Enable gdsys IOEP driver"
|
|
depends on MISC
|
|
help
|
|
Support gdsys FPGA's IO endpoint driver.
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|
|
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config MPC83XX_SERDES
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|
bool "Enable MPC83xx serdes driver"
|
|
depends on MISC
|
|
help
|
|
Support for serdes found on MPC83xx SoCs.
|
|
|
|
config FS_LOADER
|
|
bool "Enable loader driver for file system"
|
|
help
|
|
This is file system generic loader which can be used to load
|
|
the file image from the storage into target such as memory.
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|
|
|
The consumer driver would then use this loader to program whatever,
|
|
ie. the FPGA device.
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|
|
|
config SPL_FS_LOADER
|
|
bool "Enable loader driver for file system"
|
|
depends on SPL
|
|
help
|
|
This is file system generic loader which can be used to load
|
|
the file image from the storage into target such as memory.
|
|
|
|
The consumer driver would then use this loader to program whatever,
|
|
ie. the FPGA device.
|
|
|
|
config GDSYS_SOC
|
|
bool "Enable gdsys SOC driver"
|
|
depends on MISC
|
|
help
|
|
Support for gdsys IHS SOC, a simple bus associated with each gdsys
|
|
IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
|
|
register maps are contained within the FPGA's register map.
|
|
|
|
config IHS_FPGA
|
|
bool "Enable IHS FPGA driver"
|
|
depends on MISC
|
|
help
|
|
Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
|
|
gdsys devices, which supply the majority of the functionality offered
|
|
by the devices. This driver supports both CON and CPU variants of the
|
|
devices, depending on the device tree entry.
|
|
config ESM_K3
|
|
bool "Enable K3 ESM driver"
|
|
depends on ARCH_K3
|
|
help
|
|
Support ESM (Error Signaling Module) on TI K3 SoCs.
|
|
|
|
config MICROCHIP_FLEXCOM
|
|
bool "Enable Microchip Flexcom driver"
|
|
depends on MISC
|
|
help
|
|
The Atmel Flexcom is just a wrapper which embeds a SPI controller,
|
|
an I2C controller and an USART.
|
|
Only one function can be used at a time and is chosen at boot time
|
|
according to the device tree.
|
|
|
|
config K3_AVS0
|
|
depends on ARCH_K3 && SPL_DM_REGULATOR
|
|
bool "AVS class 0 support for K3 devices"
|
|
help
|
|
K3 devices have the optimized voltage values for the main voltage
|
|
domains stored in efuse within the VTM IP. This driver reads the
|
|
optimized voltage from the efuse, so that it can be programmed
|
|
to the PMIC on board.
|
|
|
|
config ESM_PMIC
|
|
bool "Enable PMIC ESM driver"
|
|
depends on DM_PMIC
|
|
help
|
|
Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
|
|
typically to reboot the board in error condition.
|
|
|
|
config FSL_IFC
|
|
bool
|
|
|
|
config SL28CPLD
|
|
bool "Enable Kontron sl28cpld multi-function driver"
|
|
depends on DM_I2C
|
|
help
|
|
Support for the Kontron sl28cpld management controller. This is
|
|
the base driver which provides common access methods for the
|
|
sub-drivers.
|
|
|
|
endmenu
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