2018-08-16 15:30:07 +00:00
|
|
|
|
2019-10-03 17:50:03 +00:00
|
|
|
menuconfig MTD_RAW_NAND
|
2018-08-16 15:30:08 +00:00
|
|
|
bool "Raw NAND Device Support"
|
2019-10-03 17:50:03 +00:00
|
|
|
if MTD_RAW_NAND
|
2018-08-16 15:30:07 +00:00
|
|
|
|
|
|
|
|
config SYS_NAND_SELF_INIT
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
This option, if enabled, provides more flexible and linux-like
|
|
|
|
|
NAND initialization process.
|
|
|
|
|
|
2018-12-06 13:57:09 +00:00
|
|
|
config SYS_NAND_DRIVER_ECC_LAYOUT
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
Omit standard ECC layouts to safe space. Select this if your driver
|
|
|
|
|
is known to provide its own ECC layout.
|
|
|
|
|
|
2019-08-22 10:28:04 +00:00
|
|
|
config SYS_NAND_USE_FLASH_BBT
|
|
|
|
|
bool "Enable BBT (Bad Block Table) support"
|
|
|
|
|
help
|
|
|
|
|
Enable the BBT (Bad Block Table) usage.
|
|
|
|
|
|
2018-08-16 15:30:07 +00:00
|
|
|
config NAND_ATMEL
|
|
|
|
|
bool "Support Atmel NAND controller"
|
|
|
|
|
imply SYS_NAND_USE_FLASH_BBT
|
|
|
|
|
help
|
|
|
|
|
Enable this driver for NAND flash platforms using an Atmel NAND
|
|
|
|
|
controller.
|
|
|
|
|
|
2018-12-15 07:36:46 +00:00
|
|
|
if NAND_ATMEL
|
|
|
|
|
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|
|
|
config ATMEL_NAND_HWECC
|
|
|
|
|
bool "Atmel Hardware ECC"
|
|
|
|
|
|
|
|
|
|
config ATMEL_NAND_HW_PMECC
|
|
|
|
|
bool "Atmel Programmable Multibit ECC (PMECC)"
|
|
|
|
|
select ATMEL_NAND_HWECC
|
|
|
|
|
help
|
|
|
|
|
The Programmable Multibit ECC (PMECC) controller is a programmable
|
|
|
|
|
binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
|
|
|
|
|
|
|
|
|
|
config PMECC_CAP
|
|
|
|
|
int "PMECC Correctable ECC Bits"
|
|
|
|
|
depends on ATMEL_NAND_HW_PMECC
|
|
|
|
|
default 2
|
|
|
|
|
help
|
|
|
|
|
Correctable ECC bits, can be 2, 4, 8, 12, and 24.
|
|
|
|
|
|
|
|
|
|
config PMECC_SECTOR_SIZE
|
|
|
|
|
int "PMECC Sector Size"
|
|
|
|
|
depends on ATMEL_NAND_HW_PMECC
|
|
|
|
|
default 512
|
|
|
|
|
help
|
|
|
|
|
Sector size, in bytes, can be 512 or 1024.
|
|
|
|
|
|
|
|
|
|
config SPL_GENERATE_ATMEL_PMECC_HEADER
|
|
|
|
|
bool "Atmel PMECC Header Generation"
|
|
|
|
|
select ATMEL_NAND_HWECC
|
|
|
|
|
select ATMEL_NAND_HW_PMECC
|
|
|
|
|
help
|
|
|
|
|
Generate Programmable Multibit ECC (PMECC) header for SPL image.
|
|
|
|
|
|
|
|
|
|
endif
|
|
|
|
|
|
2019-03-15 14:14:36 +00:00
|
|
|
config NAND_BRCMNAND
|
|
|
|
|
bool "Support Broadcom NAND controller"
|
2019-10-03 17:50:04 +00:00
|
|
|
depends on OF_CONTROL && DM && DM_MTD
|
2019-03-15 14:14:36 +00:00
|
|
|
help
|
|
|
|
|
Enable the driver for NAND flash on platforms using a Broadcom NAND
|
|
|
|
|
controller.
|
|
|
|
|
|
2019-08-28 17:12:15 +00:00
|
|
|
config NAND_BRCMNAND_6368
|
|
|
|
|
bool "Support Broadcom NAND controller on bcm6368"
|
|
|
|
|
depends on NAND_BRCMNAND && ARCH_BMIPS
|
|
|
|
|
help
|
|
|
|
|
Enable support for broadcom nand driver on bcm6368.
|
|
|
|
|
|
2020-01-07 19:14:13 +00:00
|
|
|
config NAND_BRCMNAND_68360
|
|
|
|
|
bool "Support Broadcom NAND controller on bcm68360"
|
|
|
|
|
depends on NAND_BRCMNAND && ARCH_BCM68360
|
|
|
|
|
help
|
|
|
|
|
Enable support for broadcom nand driver on bcm68360.
|
|
|
|
|
|
2019-03-15 14:14:36 +00:00
|
|
|
config NAND_BRCMNAND_6838
|
|
|
|
|
bool "Support Broadcom NAND controller on bcm6838"
|
|
|
|
|
depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
|
|
|
|
|
help
|
|
|
|
|
Enable support for broadcom nand driver on bcm6838.
|
|
|
|
|
|
|
|
|
|
config NAND_BRCMNAND_6858
|
|
|
|
|
bool "Support Broadcom NAND controller on bcm6858"
|
|
|
|
|
depends on NAND_BRCMNAND && ARCH_BCM6858
|
|
|
|
|
help
|
|
|
|
|
Enable support for broadcom nand driver on bcm6858.
|
|
|
|
|
|
|
|
|
|
config NAND_BRCMNAND_63158
|
|
|
|
|
bool "Support Broadcom NAND controller on bcm63158"
|
|
|
|
|
depends on NAND_BRCMNAND && ARCH_BCM63158
|
|
|
|
|
help
|
|
|
|
|
Enable support for broadcom nand driver on bcm63158.
|
|
|
|
|
|
2018-08-16 15:30:07 +00:00
|
|
|
config NAND_DAVINCI
|
|
|
|
|
bool "Support TI Davinci NAND controller"
|
|
|
|
|
help
|
|
|
|
|
Enable this driver for NAND flash controllers available in TI Davinci
|
|
|
|
|
and Keystone2 platforms
|
|
|
|
|
|
2021-09-13 00:32:24 +00:00
|
|
|
config KEYSTONE_RBL_NAND
|
|
|
|
|
depends on ARCH_KEYSTONE
|
|
|
|
|
def_bool y
|
|
|
|
|
|
2021-09-22 18:50:29 +00:00
|
|
|
config SPL_NAND_LOAD
|
|
|
|
|
def_bool y
|
|
|
|
|
depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
|
|
|
|
|
|
2018-08-16 15:30:07 +00:00
|
|
|
config NAND_DENALI
|
|
|
|
|
bool
|
|
|
|
|
select SYS_NAND_SELF_INIT
|
|
|
|
|
imply CMD_NAND
|
|
|
|
|
|
|
|
|
|
config NAND_DENALI_DT
|
|
|
|
|
bool "Support Denali NAND controller as a DT device"
|
|
|
|
|
select NAND_DENALI
|
2020-01-30 13:07:59 +00:00
|
|
|
depends on OF_CONTROL && DM_MTD
|
2018-08-16 15:30:07 +00:00
|
|
|
help
|
|
|
|
|
Enable the driver for NAND flash on platforms using a Denali NAND
|
|
|
|
|
controller as a DT device.
|
|
|
|
|
|
2021-09-22 18:50:37 +00:00
|
|
|
config NAND_FSL_ELBC
|
|
|
|
|
bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
|
|
|
|
|
depends on FSL_ELBC
|
|
|
|
|
help
|
|
|
|
|
Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
|
|
|
|
|
|
|
|
|
|
config NAND_FSL_IFC
|
|
|
|
|
bool "Support Freescale Integrated Flash Controller NAND driver"
|
|
|
|
|
help
|
|
|
|
|
Enable the Freescale Integrated Flash Controller NAND driver.
|
|
|
|
|
|
2021-09-22 18:50:28 +00:00
|
|
|
config NAND_LPC32XX_MLC
|
|
|
|
|
bool "Support LPC32XX_MLC controller"
|
|
|
|
|
help
|
|
|
|
|
Enable the LPC32XX MLC NAND controller.
|
|
|
|
|
|
2018-08-16 15:30:07 +00:00
|
|
|
config NAND_LPC32XX_SLC
|
|
|
|
|
bool "Support LPC32XX_SLC controller"
|
|
|
|
|
help
|
|
|
|
|
Enable the LPC32XX SLC NAND controller.
|
|
|
|
|
|
|
|
|
|
config NAND_OMAP_GPMC
|
|
|
|
|
bool "Support OMAP GPMC NAND controller"
|
|
|
|
|
depends on ARCH_OMAP2PLUS
|
|
|
|
|
help
|
|
|
|
|
Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
|
|
|
|
|
GPMC controller is used for parallel NAND flash devices, and can
|
|
|
|
|
do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
|
|
|
|
|
and BCH16 ECC algorithms.
|
|
|
|
|
|
2021-09-22 18:50:39 +00:00
|
|
|
if NAND_OMAP_GPMC
|
|
|
|
|
|
2018-08-16 15:30:07 +00:00
|
|
|
config NAND_OMAP_GPMC_PREFETCH
|
|
|
|
|
bool "Enable GPMC Prefetch"
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
On OMAP platforms that use the GPMC controller
|
|
|
|
|
(CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
|
|
|
|
|
uses the prefetch mode to speed up read operations.
|
|
|
|
|
|
|
|
|
|
config NAND_OMAP_ELM
|
|
|
|
|
bool "Enable ELM driver for OMAPxx and AMxx platforms."
|
2021-09-22 18:50:39 +00:00
|
|
|
depends on !OMAP34XX
|
2018-08-16 15:30:07 +00:00
|
|
|
help
|
|
|
|
|
ELM controller is used for ECC error detection (not ECC calculation)
|
|
|
|
|
of BCH4, BCH8 and BCH16 ECC algorithms.
|
|
|
|
|
Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
|
|
|
|
|
thus such SoC platforms need to depend on software library for ECC error
|
|
|
|
|
detection. However ECC calculation on such plaforms would still be
|
|
|
|
|
done by GPMC controller.
|
|
|
|
|
|
2021-09-22 18:50:39 +00:00
|
|
|
choice
|
|
|
|
|
prompt "ECC scheme"
|
|
|
|
|
default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
|
|
|
|
|
help
|
|
|
|
|
On OMAP platforms, this CONFIG specifies NAND ECC scheme.
|
|
|
|
|
It can take following values:
|
|
|
|
|
OMAP_ECC_HAM1_CODE_SW
|
|
|
|
|
1-bit Hamming code using software lib.
|
|
|
|
|
(for legacy devices only)
|
|
|
|
|
OMAP_ECC_HAM1_CODE_HW
|
|
|
|
|
1-bit Hamming code using GPMC hardware.
|
|
|
|
|
(for legacy devices only)
|
|
|
|
|
OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
|
|
|
|
|
4-bit BCH code (unsupported)
|
|
|
|
|
OMAP_ECC_BCH4_CODE_HW
|
|
|
|
|
4-bit BCH code (unsupported)
|
|
|
|
|
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
|
|
|
|
|
8-bit BCH code with
|
|
|
|
|
- ecc calculation using GPMC hardware engine,
|
|
|
|
|
- error detection using software library.
|
|
|
|
|
- requires CONFIG_BCH to enable software BCH library
|
|
|
|
|
(For legacy device which do not have ELM h/w engine)
|
|
|
|
|
OMAP_ECC_BCH8_CODE_HW
|
|
|
|
|
8-bit BCH code with
|
|
|
|
|
- ecc calculation using GPMC hardware engine,
|
|
|
|
|
- error detection using ELM hardware engine.
|
|
|
|
|
OMAP_ECC_BCH16_CODE_HW
|
|
|
|
|
16-bit BCH code with
|
|
|
|
|
- ecc calculation using GPMC hardware engine,
|
|
|
|
|
- error detection using ELM hardware engine.
|
|
|
|
|
|
|
|
|
|
How to select ECC scheme on OMAP and AMxx platforms ?
|
|
|
|
|
-----------------------------------------------------
|
|
|
|
|
Though higher ECC schemes have more capability to detect and correct
|
|
|
|
|
bit-flips, but still selection of ECC scheme is dependent on following
|
|
|
|
|
- hardware engines present in SoC.
|
|
|
|
|
Some legacy OMAP SoC do not have ELM h/w engine thus such
|
|
|
|
|
SoC cannot support BCHx_HW ECC schemes.
|
|
|
|
|
- size of OOB/Spare region
|
|
|
|
|
With higher ECC schemes, more OOB/Spare area is required to
|
|
|
|
|
store ECC. So choice of ECC scheme is limited by NAND oobsize.
|
|
|
|
|
|
|
|
|
|
In general following expression can help:
|
|
|
|
|
NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
|
|
|
|
|
where
|
|
|
|
|
NAND_OOBSIZE = number of bytes available in
|
|
|
|
|
OOB/spare area per NAND page.
|
|
|
|
|
NAND_PAGESIZE = bytes in main-area of NAND page.
|
|
|
|
|
ECC_BYTES = number of ECC bytes generated to
|
|
|
|
|
protect 512 bytes of data, which is:
|
|
|
|
|
3 for HAM1_xx ecc schemes
|
|
|
|
|
7 for BCH4_xx ecc schemes
|
|
|
|
|
14 for BCH8_xx ecc schemes
|
|
|
|
|
26 for BCH16_xx ecc schemes
|
|
|
|
|
|
|
|
|
|
example to check for BCH16 on 2K page NAND
|
|
|
|
|
NAND_PAGESIZE = 2048
|
|
|
|
|
NAND_OOBSIZE = 64
|
|
|
|
|
2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
|
|
|
|
|
Thus BCH16 cannot be supported on 2K page NAND.
|
|
|
|
|
|
|
|
|
|
However, for 4K pagesize NAND
|
|
|
|
|
NAND_PAGESIZE = 4096
|
|
|
|
|
NAND_OOBSIZE = 224
|
|
|
|
|
ECC_BYTES = 26
|
|
|
|
|
2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
|
|
|
|
|
Thus BCH16 can be supported on 4K page NAND.
|
|
|
|
|
|
|
|
|
|
config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
|
|
|
|
|
bool "1-bit Hamming code using software lib"
|
|
|
|
|
|
|
|
|
|
config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
|
|
|
|
|
bool "1-bit Hamming code using GPMC hardware"
|
|
|
|
|
|
|
|
|
|
config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
|
|
|
|
|
bool "8-bit BCH code with HW calculation SW error detection"
|
|
|
|
|
|
|
|
|
|
config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
|
|
|
|
|
bool "8-bit BCH code with HW calculation and error detection"
|
|
|
|
|
|
|
|
|
|
config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
|
|
|
|
|
bool "16-bit BCH code with HW calculation and error detection"
|
|
|
|
|
|
|
|
|
|
endchoice
|
|
|
|
|
|
|
|
|
|
config NAND_OMAP_ECCSCHEME
|
|
|
|
|
int
|
|
|
|
|
default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
|
|
|
|
|
default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
|
|
|
|
|
default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
|
|
|
|
|
default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
|
|
|
|
|
default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
|
|
|
|
|
help
|
|
|
|
|
This must be kept in sync with the enum in
|
|
|
|
|
include/linux/mtd/omap_gpmc.h
|
|
|
|
|
|
|
|
|
|
endif
|
|
|
|
|
|
2018-08-16 15:30:07 +00:00
|
|
|
config NAND_VF610_NFC
|
|
|
|
|
bool "Support for Freescale NFC for VF610"
|
|
|
|
|
select SYS_NAND_SELF_INIT
|
2018-12-06 13:57:09 +00:00
|
|
|
select SYS_NAND_DRIVER_ECC_LAYOUT
|
2018-08-16 15:30:07 +00:00
|
|
|
imply CMD_NAND
|
|
|
|
|
help
|
|
|
|
|
Enables support for NAND Flash Controller on some Freescale
|
|
|
|
|
processors like the VF610, MCF54418 or Kinetis K70.
|
|
|
|
|
The driver supports a maximum 2k page size. The driver
|
|
|
|
|
currently does not support hardware ECC.
|
|
|
|
|
|
2018-12-03 09:24:50 +00:00
|
|
|
if NAND_VF610_NFC
|
|
|
|
|
|
|
|
|
|
config NAND_VF610_NFC_DT
|
|
|
|
|
bool "Support Vybrid's vf610 NAND controller as a DT device"
|
2019-10-03 17:50:04 +00:00
|
|
|
depends on OF_CONTROL && DM_MTD
|
2018-12-03 09:24:50 +00:00
|
|
|
help
|
|
|
|
|
Enable the driver for Vybrid's vf610 NAND flash on platforms
|
|
|
|
|
using device tree.
|
|
|
|
|
|
2018-08-16 15:30:07 +00:00
|
|
|
choice
|
|
|
|
|
prompt "Hardware ECC strength"
|
|
|
|
|
depends on NAND_VF610_NFC
|
|
|
|
|
default SYS_NAND_VF610_NFC_45_ECC_BYTES
|
|
|
|
|
help
|
|
|
|
|
Select the ECC strength used in the hardware BCH ECC block.
|
|
|
|
|
|
|
|
|
|
config SYS_NAND_VF610_NFC_45_ECC_BYTES
|
|
|
|
|
bool "24-error correction (45 ECC bytes)"
|
|
|
|
|
|
|
|
|
|
config SYS_NAND_VF610_NFC_60_ECC_BYTES
|
|
|
|
|
bool "32-error correction (60 ECC bytes)"
|
|
|
|
|
|
|
|
|
|
endchoice
|
|
|
|
|
|
2018-12-03 09:24:50 +00:00
|
|
|
endif
|
|
|
|
|
|
2018-08-16 15:30:07 +00:00
|
|
|
config NAND_PXA3XX
|
|
|
|
|
bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
|
|
|
|
|
select SYS_NAND_SELF_INIT
|
2020-10-29 06:52:18 +00:00
|
|
|
select DM_MTD
|
2020-10-29 06:52:20 +00:00
|
|
|
select REGMAP
|
|
|
|
|
select SYSCON
|
2018-08-16 15:30:07 +00:00
|
|
|
imply CMD_NAND
|
|
|
|
|
help
|
|
|
|
|
This enables the driver for the NAND flash device found on
|
|
|
|
|
PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
|
|
|
|
|
|
|
|
|
|
config NAND_SUNXI
|
|
|
|
|
bool "Support for NAND on Allwinner SoCs"
|
|
|
|
|
default ARCH_SUNXI
|
|
|
|
|
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
|
|
|
|
|
select SYS_NAND_SELF_INIT
|
|
|
|
|
select SYS_NAND_U_BOOT_LOCATIONS
|
|
|
|
|
select SPL_NAND_SUPPORT
|
|
|
|
|
imply CMD_NAND
|
|
|
|
|
---help---
|
|
|
|
|
Enable support for NAND. This option enables the standard and
|
|
|
|
|
SPL drivers.
|
|
|
|
|
The SPL driver only supports reading from the NAND using DMA
|
|
|
|
|
transfers.
|
|
|
|
|
|
|
|
|
|
if NAND_SUNXI
|
|
|
|
|
|
|
|
|
|
config NAND_SUNXI_SPL_ECC_STRENGTH
|
|
|
|
|
int "Allwinner NAND SPL ECC Strength"
|
|
|
|
|
default 64
|
|
|
|
|
|
|
|
|
|
config NAND_SUNXI_SPL_ECC_SIZE
|
|
|
|
|
int "Allwinner NAND SPL ECC Step Size"
|
|
|
|
|
default 1024
|
|
|
|
|
|
|
|
|
|
config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
|
|
|
|
|
int "Allwinner NAND SPL Usable Page Size"
|
|
|
|
|
default 1024
|
|
|
|
|
|
|
|
|
|
endif
|
|
|
|
|
|
|
|
|
|
config NAND_ARASAN
|
|
|
|
|
bool "Configure Arasan Nand"
|
|
|
|
|
select SYS_NAND_SELF_INIT
|
2020-08-19 07:59:52 +00:00
|
|
|
depends on DM_MTD
|
2018-08-16 15:30:07 +00:00
|
|
|
imply CMD_NAND
|
|
|
|
|
help
|
|
|
|
|
This enables Nand driver support for Arasan nand flash
|
|
|
|
|
controller. This uses the hardware ECC for read and
|
|
|
|
|
write operations.
|
|
|
|
|
|
|
|
|
|
config NAND_MXC
|
|
|
|
|
bool "MXC NAND support"
|
|
|
|
|
depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
|
|
|
|
|
imply CMD_NAND
|
|
|
|
|
help
|
|
|
|
|
This enables the NAND driver for the NAND flash controller on the
|
|
|
|
|
i.MX27 / i.MX31 / i.MX5 rocessors.
|
|
|
|
|
|
|
|
|
|
config NAND_MXS
|
|
|
|
|
bool "MXS NAND support"
|
2020-05-04 14:09:00 +00:00
|
|
|
depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
|
2018-08-16 15:30:07 +00:00
|
|
|
select SYS_NAND_SELF_INIT
|
|
|
|
|
imply CMD_NAND
|
|
|
|
|
select APBH_DMA
|
2020-05-04 14:09:00 +00:00
|
|
|
select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
|
|
|
|
|
select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
|
2018-08-16 15:30:07 +00:00
|
|
|
help
|
|
|
|
|
This enables NAND driver for the NAND flash controller on the
|
|
|
|
|
MXS processors.
|
|
|
|
|
|
|
|
|
|
if NAND_MXS
|
|
|
|
|
|
|
|
|
|
config NAND_MXS_DT
|
|
|
|
|
bool "Support MXS NAND controller as a DT device"
|
2019-10-03 17:50:04 +00:00
|
|
|
depends on OF_CONTROL && DM_MTD
|
2018-08-16 15:30:07 +00:00
|
|
|
help
|
|
|
|
|
Enable the driver for MXS NAND flash on platforms using
|
|
|
|
|
device tree.
|
|
|
|
|
|
|
|
|
|
config NAND_MXS_USE_MINIMUM_ECC
|
|
|
|
|
bool "Use minimum ECC strength supported by the controller"
|
|
|
|
|
default false
|
|
|
|
|
|
|
|
|
|
endif
|
|
|
|
|
|
|
|
|
|
config NAND_ZYNQ
|
|
|
|
|
bool "Support for Zynq Nand controller"
|
|
|
|
|
select SYS_NAND_SELF_INIT
|
2019-12-27 11:47:12 +00:00
|
|
|
select DM_MTD
|
2018-08-16 15:30:07 +00:00
|
|
|
imply CMD_NAND
|
|
|
|
|
help
|
|
|
|
|
This enables Nand driver support for Nand flash controller
|
|
|
|
|
found on Zynq SoC.
|
|
|
|
|
|
|
|
|
|
config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
|
|
|
|
|
bool "Enable use of 1st stage bootloader timing for NAND"
|
|
|
|
|
depends on NAND_ZYNQ
|
|
|
|
|
help
|
|
|
|
|
This flag prevent U-boot reconfigure NAND flash controller and reuse
|
|
|
|
|
the NAND timing from 1st stage bootloader.
|
|
|
|
|
|
2020-08-26 12:37:22 +00:00
|
|
|
config NAND_OCTEONTX
|
|
|
|
|
bool "Support for OcteonTX NAND controller"
|
|
|
|
|
select SYS_NAND_SELF_INIT
|
|
|
|
|
imply CMD_NAND
|
|
|
|
|
help
|
|
|
|
|
This enables Nand flash controller hardware found on the OcteonTX
|
|
|
|
|
processors.
|
|
|
|
|
|
|
|
|
|
config NAND_OCTEONTX_HW_ECC
|
|
|
|
|
bool "Support Hardware ECC for OcteonTX NAND controller"
|
|
|
|
|
depends on NAND_OCTEONTX
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
This enables Hardware BCH engine found on the OcteonTX processors to
|
|
|
|
|
support ECC for NAND flash controller.
|
|
|
|
|
|
2019-04-05 09:41:50 +00:00
|
|
|
config NAND_STM32_FMC2
|
|
|
|
|
bool "Support for NAND controller on STM32MP SoCs"
|
|
|
|
|
depends on ARCH_STM32MP
|
|
|
|
|
select SYS_NAND_SELF_INIT
|
|
|
|
|
imply CMD_NAND
|
|
|
|
|
help
|
|
|
|
|
Enables support for NAND Flash chips on SoCs containing the FMC2
|
|
|
|
|
NAND controller. This controller is found on STM32MP SoCs.
|
|
|
|
|
The controller supports a maximum 8k page size and supports
|
|
|
|
|
a maximum 8-bit correction error per sector of 512 bytes.
|
|
|
|
|
|
2020-12-11 21:46:12 +00:00
|
|
|
config CORTINA_NAND
|
|
|
|
|
bool "Support for NAND controller on Cortina-Access SoCs"
|
|
|
|
|
depends on CORTINA_PLATFORM
|
|
|
|
|
select SYS_NAND_SELF_INIT
|
|
|
|
|
select DM_MTD
|
|
|
|
|
imply CMD_NAND
|
|
|
|
|
help
|
|
|
|
|
Enables support for NAND Flash chips on Coartina-Access SoCs platform
|
|
|
|
|
This controller is found on Presidio/Venus SoCs.
|
|
|
|
|
The controller supports a maximum 8k page size and supports
|
|
|
|
|
a maximum 40-bit error correction per sector of 1024 bytes.
|
|
|
|
|
|
2021-06-07 08:40:29 +00:00
|
|
|
config ROCKCHIP_NAND
|
|
|
|
|
bool "Support for NAND controller on Rockchip SoCs"
|
|
|
|
|
depends on ARCH_ROCKCHIP
|
|
|
|
|
select SYS_NAND_SELF_INIT
|
|
|
|
|
select DM_MTD
|
|
|
|
|
imply CMD_NAND
|
|
|
|
|
help
|
|
|
|
|
Enables support for NAND Flash chips on Rockchip SoCs platform.
|
|
|
|
|
This controller is found on Rockchip SoCs.
|
|
|
|
|
There are four different versions of NAND FLASH Controllers,
|
|
|
|
|
including:
|
|
|
|
|
NFC v600: RK2928, RK3066, RK3188
|
|
|
|
|
NFC v622: RK3036, RK3128
|
|
|
|
|
NFC v800: RK3308, RV1108
|
|
|
|
|
NFC v900: PX30, RK3326
|
|
|
|
|
|
2018-08-16 15:30:07 +00:00
|
|
|
comment "Generic NAND options"
|
|
|
|
|
|
|
|
|
|
config SYS_NAND_BLOCK_SIZE
|
|
|
|
|
hex "NAND chip eraseblock size"
|
2021-09-22 18:50:29 +00:00
|
|
|
depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
|
|
|
|
|
depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
|
2018-08-16 15:30:07 +00:00
|
|
|
help
|
|
|
|
|
Number of data bytes in one eraseblock for the NAND chip on the
|
|
|
|
|
board. This is the multiple of NAND_PAGE_SIZE and the number of
|
|
|
|
|
pages.
|
|
|
|
|
|
2021-09-22 18:50:34 +00:00
|
|
|
config SYS_NAND_ONFI_DETECTION
|
|
|
|
|
bool "Enable detection of ONFI compliant devices during probe"
|
|
|
|
|
help
|
|
|
|
|
Enables detection of ONFI compliant devices during probe.
|
|
|
|
|
And fetching device parameters flashed on device, by parsing
|
|
|
|
|
ONFI parameter page.
|
|
|
|
|
|
2021-09-22 18:50:30 +00:00
|
|
|
config SYS_NAND_PAGE_COUNT
|
|
|
|
|
hex "NAND chip page count"
|
|
|
|
|
depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
|
|
|
|
|
SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
|
|
|
|
|
help
|
|
|
|
|
Number of pages in the NAND chip.
|
|
|
|
|
|
2018-08-16 15:30:07 +00:00
|
|
|
config SYS_NAND_PAGE_SIZE
|
|
|
|
|
hex "NAND chip page size"
|
2021-09-22 18:50:29 +00:00
|
|
|
depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
|
|
|
|
|
SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
|
|
|
|
|
(NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
|
|
|
|
|
depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
|
2018-08-16 15:30:07 +00:00
|
|
|
help
|
|
|
|
|
Number of data bytes in one page for the NAND chip on the
|
|
|
|
|
board, not including the OOB area.
|
|
|
|
|
|
|
|
|
|
config SYS_NAND_OOBSIZE
|
|
|
|
|
hex "NAND chip OOB size"
|
2021-09-22 18:50:29 +00:00
|
|
|
depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
|
|
|
|
|
SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
|
|
|
|
|
(NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
|
|
|
|
|
depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
|
2018-08-16 15:30:07 +00:00
|
|
|
help
|
|
|
|
|
Number of bytes in the Out-Of-Band area for the NAND chip on
|
|
|
|
|
the board.
|
|
|
|
|
|
|
|
|
|
# Enhance depends when converting drivers to Kconfig which use this config
|
|
|
|
|
# option (mxc_nand, ndfc, omap_gpmc).
|
|
|
|
|
config SYS_NAND_BUSWIDTH_16BIT
|
|
|
|
|
bool "Use 16-bit NAND interface"
|
|
|
|
|
depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
|
|
|
|
|
help
|
|
|
|
|
Indicates that NAND device has 16-bit wide data-bus. In absence of this
|
|
|
|
|
config, bus-width of NAND device is assumed to be either 8-bit and later
|
|
|
|
|
determined by reading ONFI params.
|
|
|
|
|
Above config is useful when NAND device's bus-width information cannot
|
|
|
|
|
be determined from on-chip ONFI params, like in following scenarios:
|
|
|
|
|
- SPL boot does not support reading of ONFI parameters. This is done to
|
|
|
|
|
keep SPL code foot-print small.
|
|
|
|
|
- In current U-Boot flow using nand_init(), driver initialization
|
|
|
|
|
happens in board_nand_init() which is called before any device probe
|
|
|
|
|
(nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
|
|
|
|
|
not available while configuring controller. So a static CONFIG_NAND_xx
|
|
|
|
|
is needed to know the device's bus-width in advance.
|
|
|
|
|
|
|
|
|
|
if SPL
|
|
|
|
|
|
2021-09-22 18:50:33 +00:00
|
|
|
config SYS_NAND_5_ADDR_CYCLE
|
|
|
|
|
bool "Wait 5 address cycles during NAND commands"
|
|
|
|
|
depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
|
|
|
|
|
(SPL_NAND_SUPPORT && NAND_ATMEL)
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
Some controllers require waiting for 5 address cycles when issuing
|
|
|
|
|
some commands, on NAND chips larger than 128MiB.
|
|
|
|
|
|
2021-09-22 18:50:32 +00:00
|
|
|
choice
|
2021-09-22 18:50:34 +00:00
|
|
|
prompt "NAND bad block marker/indicator position in the OOB"
|
2021-09-22 18:50:32 +00:00
|
|
|
depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
|
|
|
|
|
SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
|
|
|
|
|
default HAS_NAND_LARGE_BADBLOCK_POS
|
|
|
|
|
help
|
|
|
|
|
In the OOB, which position contains the badblock information.
|
|
|
|
|
|
|
|
|
|
config HAS_NAND_LARGE_BADBLOCK_POS
|
|
|
|
|
bool "Set the bad block marker/indicator to the 'large' position"
|
|
|
|
|
|
|
|
|
|
config HAS_NAND_SMALL_BADBLOCK_POS
|
|
|
|
|
bool "Set the bad block marker/indicator to the 'small' position"
|
|
|
|
|
|
|
|
|
|
endchoice
|
|
|
|
|
|
|
|
|
|
config SYS_NAND_BAD_BLOCK_POS
|
|
|
|
|
int
|
|
|
|
|
default 0 if HAS_NAND_LARGE_BADBLOCK_POS
|
|
|
|
|
default 5 if HAS_NAND_SMALL_BADBLOCK_POS
|
|
|
|
|
|
2018-08-16 15:30:07 +00:00
|
|
|
config SYS_NAND_U_BOOT_LOCATIONS
|
|
|
|
|
bool "Define U-boot binaries locations in NAND"
|
|
|
|
|
help
|
|
|
|
|
Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
|
|
|
|
|
This option should not be enabled when compiling U-boot for boards
|
|
|
|
|
defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
|
|
|
|
|
file.
|
|
|
|
|
|
|
|
|
|
config SYS_NAND_U_BOOT_OFFS
|
|
|
|
|
hex "Location in NAND to read U-Boot from"
|
|
|
|
|
default 0x800000 if NAND_SUNXI
|
|
|
|
|
depends on SYS_NAND_U_BOOT_LOCATIONS
|
|
|
|
|
help
|
|
|
|
|
Set the offset from the start of the nand where u-boot should be
|
|
|
|
|
loaded from.
|
|
|
|
|
|
|
|
|
|
config SYS_NAND_U_BOOT_OFFS_REDUND
|
|
|
|
|
hex "Location in NAND to read U-Boot from"
|
|
|
|
|
default SYS_NAND_U_BOOT_OFFS
|
|
|
|
|
depends on SYS_NAND_U_BOOT_LOCATIONS
|
|
|
|
|
help
|
|
|
|
|
Set the offset from the start of the nand where the redundant u-boot
|
|
|
|
|
should be loaded from.
|
|
|
|
|
|
|
|
|
|
config SPL_NAND_AM33XX_BCH
|
|
|
|
|
bool "Enables SPL-NAND driver which supports ELM based"
|
|
|
|
|
depends on NAND_OMAP_GPMC && !OMAP34XX
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default y
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help
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Hardware ECC correction. This is useful for platforms which have ELM
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hardware engine and use NAND boot mode.
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Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
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so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
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SPL-NAND driver with software ECC correction support.
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config SPL_NAND_DENALI
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bool "Support Denali NAND controller for SPL"
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help
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This is a small implementation of the Denali NAND controller
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for use on SPL.
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2020-04-17 07:51:42 +00:00
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config NAND_DENALI_SPARE_AREA_SKIP_BYTES
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int "Number of bytes skipped in OOB area"
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depends on SPL_NAND_DENALI
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range 0 63
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help
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This option specifies the number of bytes to skip from the beginning
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of OOB area before last ECC sector data starts. This is potentially
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used to preserve the bad block marker in the OOB area.
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2018-08-16 15:30:07 +00:00
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config SPL_NAND_SIMPLE
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bool "Use simple SPL NAND driver"
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depends on !SPL_NAND_AM33XX_BCH
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help
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Support for NAND boot using simple NAND drivers that
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expose the cmd_ctrl() interface.
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endif
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endif # if NAND
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