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https://github.com/AsahiLinux/u-boot
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ARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to Kconfig
This commit converts the following items to Kconfig:
CONFIG_ATMEL_NAND_HWECC
CONFIG_ATMEL_NAND_HW_PMECC
CONFIG_PMECC_CAP
CONFIG_PMECC_SECTOR_SIZE
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
[PMECC References]
https://www.at91.com/linux4sam/bin/view/Linux4SAM/PmeccConfigure
https://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91Bootstrap
[Mailing List Thread]
https://lists.denx.de/pipermail/u-boot/2018-December/350666.html
Fixes: 5541543f
("configs: at91: Remove CONFIG_SYS_EXTRA_OPTIONS assignment")
[trini: Make the migration be size neutral and possibly not fix the
above in all cases]
Reported-by: Daniel Evans <photonthunder@gmail.com>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
parent
2acc24fc28
commit
49ad40298c
39 changed files with 80 additions and 69 deletions
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@ -41,6 +41,7 @@ CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -40,6 +40,7 @@ CONFIG_AT91_GPIO=y
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CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND_ATMEL=y
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -41,6 +41,7 @@ CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -43,6 +43,7 @@ CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -43,6 +43,7 @@ CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -42,6 +42,7 @@ CONFIG_AT91_GPIO=y
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CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND_ATMEL=y
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -43,6 +43,7 @@ CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -27,6 +27,7 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard"
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CONFIG_ENV_IS_IN_NAND=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_ATMEL_NAND_HWECC=y
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CONFIG_PHYLIB=y
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CONFIG_TIMER=y
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CONFIG_ATMEL_PIT_TIMER=y
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@ -50,6 +50,7 @@ CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ATMEL=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_ATMEL_NAND_HW_PMECC=y
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CONFIG_DM_ETH=y
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CONFIG_MACB=y
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CONFIG_PINCTRL=y
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@ -49,6 +49,7 @@ CONFIG_DM_MMC=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ATMEL=y
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CONFIG_NAND_ATMEL=y
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CONFIG_ATMEL_NAND_HW_PMECC=y
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CONFIG_DM_ETH=y
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CONFIG_MACB=y
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CONFIG_PINCTRL=y
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@ -43,6 +43,7 @@ CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -42,6 +42,7 @@ CONFIG_AT91_GPIO=y
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CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND_ATMEL=y
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -43,6 +43,7 @@ CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -60,6 +60,7 @@ CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_ETH=y
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CONFIG_MACB=y
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CONFIG_PINCTRL=y
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@ -56,6 +56,8 @@ CONFIG_AT91_GPIO=y
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CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND_ATMEL=y
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CONFIG_PMECC_CAP=4
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_ETH=y
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CONFIG_MACB=y
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CONFIG_PINCTRL=y
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@ -67,6 +67,8 @@ CONFIG_SYS_FLASH_PROTECTION=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_PMECC_CAP=4
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -61,6 +61,8 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_PROTECTION=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_NAND_ATMEL=y
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CONFIG_PMECC_CAP=4
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -62,6 +62,8 @@ CONFIG_SYS_FLASH_PROTECTION=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_PMECC_CAP=4
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -58,6 +58,7 @@ CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -54,6 +54,8 @@ CONFIG_I2C_EEPROM=y
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CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND_ATMEL=y
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CONFIG_PMECC_CAP=8
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -58,6 +58,8 @@ CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_PMECC_CAP=8
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -58,6 +58,7 @@ CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -54,6 +54,8 @@ CONFIG_AT91_GPIO=y
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CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND_ATMEL=y
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CONFIG_PMECC_CAP=8
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -55,6 +55,8 @@ CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_PMECC_CAP=8
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ATMEL=y
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@ -28,5 +28,7 @@ CONFIG_CMD_MTDPARTS=y
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CONFIG_ENV_IS_IN_NAND=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_PMECC_CAP=4
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_LZMA=y
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CONFIG_OF_LIBFDT=y
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@ -27,6 +27,8 @@ CONFIG_ENV_IS_IN_NAND=y
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CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_PMECC_CAP=8
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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@ -20,13 +20,12 @@ To use PMECC in this driver, the user needs to set:
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2. The PMECC sector size: CONFIG_PMECC_SECTOR_SIZE.
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It only can be 512 or 1024.
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Take AT91SAM9X5EK as an example, the board definition file likes:
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Take 'configs/at91sam9x5ek_nandflash_defconfig' as an example, the board
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configuration file has the following entries:
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/* PMECC & PMERRLOC */
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#define CONFIG_ATMEL_NAND_HWECC 1
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#define CONFIG_ATMEL_NAND_HW_PMECC 1
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#define CONFIG_PMECC_CAP 2
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#define CONFIG_PMECC_SECTOR_SIZE 512
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CONFIG_PMECC_CAP=2
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CONFIG_PMECC_SECTOR_SIZE=512
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
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How to enable PMECC header for direct programmable boot.bin
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-----------------------------------------------------------
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@ -40,7 +39,7 @@ sama5d3 SoC spec (as of 03. April 2014) defines how this PMECC header has to
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look like. In order to do so we have a new image type added to mkimage to
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generate this PMECC header and integrated this into the build process of SPL.
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To enable the generation of atmel PMECC header for SPL one need to define
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To enable the generation of atmel PMECC header for SPL one needs to define
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CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER. The required parameters are taken from
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board configuration and compiled into the host tools atmel_pmecc_params. This
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tool will be called in build process to parametrize mkimage for atmelimage
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@ -22,6 +22,44 @@ config NAND_ATMEL
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Enable this driver for NAND flash platforms using an Atmel NAND
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controller.
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if NAND_ATMEL
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config ATMEL_NAND_HWECC
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bool "Atmel Hardware ECC"
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default n
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config ATMEL_NAND_HW_PMECC
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bool "Atmel Programmable Multibit ECC (PMECC)"
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select ATMEL_NAND_HWECC
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default n
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help
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The Programmable Multibit ECC (PMECC) controller is a programmable
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binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
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config PMECC_CAP
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int "PMECC Correctable ECC Bits"
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depends on ATMEL_NAND_HW_PMECC
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default 2
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help
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Correctable ECC bits, can be 2, 4, 8, 12, and 24.
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config PMECC_SECTOR_SIZE
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int "PMECC Sector Size"
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depends on ATMEL_NAND_HW_PMECC
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default 512
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help
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Sector size, in bytes, can be 512 or 1024.
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config SPL_GENERATE_ATMEL_PMECC_HEADER
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bool "Atmel PMECC Header Generation"
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select ATMEL_NAND_HWECC
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select ATMEL_NAND_HW_PMECC
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default n
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help
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Generate Programmable Multibit ECC (PMECC) header for SPL image.
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endif
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config NAND_DAVINCI
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bool "Support TI Davinci NAND controller"
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help
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@ -59,12 +59,6 @@
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#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
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#endif
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/* PMECC & PMERRLOC */
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#define CONFIG_ATMEL_NAND_HWECC
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#define CONFIG_ATMEL_NAND_HW_PMECC
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#define CONFIG_PMECC_CAP 2
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#define CONFIG_PMECC_SECTOR_SIZE 512
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"console=console=ttyS0,115200\0" \
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"mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
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#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
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#endif
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
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#endif
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/* PMECC & PMERRLOC */
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#define CONFIG_ATMEL_NAND_HWECC 1
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#define CONFIG_ATMEL_NAND_HW_PMECC 1
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#define CONFIG_PMECC_CAP 2
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#define CONFIG_PMECC_SECTOR_SIZE 512
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/* USB */
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#ifdef CONFIG_CMD_USB
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#ifndef CONFIG_USB_EHCI_HCD
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
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#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
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#endif
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@ -33,9 +33,6 @@
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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/* PMECC & PMERRLOC */
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#define CONFIG_ATMEL_NAND_HWECC
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#define CONFIG_ATMEL_NAND_HW_PMECC
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#endif
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#endif /* __CONFIG_H */
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@ -43,14 +43,8 @@
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#endif
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/* PMECC & PMERRLOC */
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#define CONFIG_ATMEL_NAND_HWECC
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#define CONFIG_ATMEL_NAND_HW_PMECC
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#define CONFIG_PMECC_CAP 4
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#define CONFIG_PMECC_SECTOR_SIZE 512
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/* USB */
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_ATMEL
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#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
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#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
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#endif
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#endif
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/* PMECC & PMERRLOC */
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#define CONFIG_ATMEL_NAND_HWECC
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#define CONFIG_ATMEL_NAND_HW_PMECC
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#define CONFIG_PMECC_CAP 4
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#define CONFIG_PMECC_SECTOR_SIZE 512
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/* USB */
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#ifdef CONFIG_CMD_USB
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||||
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
|
||||
#define CONFIG_USB_OHCI_NEW
|
||||
|
@ -109,6 +103,5 @@
|
|||
#define CONFIG_SYS_NAND_OOBSIZE 64
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
|
||||
|
||||
#endif
|
||||
|
|
|
@ -37,9 +37,6 @@
|
|||
/* our CLE is AD22 */
|
||||
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
/* PMECC & PMERRLOC */
|
||||
#define CONFIG_ATMEL_NAND_HWECC
|
||||
#define CONFIG_ATMEL_NAND_HW_PMECC
|
||||
#endif
|
||||
|
||||
/* SPL */
|
||||
|
@ -64,8 +61,6 @@
|
|||
#define CONFIG_SPL_NAND_DRIVERS
|
||||
#define CONFIG_SPL_NAND_BASE
|
||||
#endif
|
||||
#define CONFIG_PMECC_CAP 8
|
||||
#define CONFIG_PMECC_SECTOR_SIZE 512
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
|
||||
|
@ -73,6 +68,5 @@
|
|||
#define CONFIG_SYS_NAND_OOBSIZE 224
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
|
||||
|
||||
#endif
|
||||
|
|
|
@ -37,9 +37,6 @@
|
|||
/* our CLE is AD22 */
|
||||
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
/* PMECC & PMERRLOC */
|
||||
#define CONFIG_ATMEL_NAND_HWECC
|
||||
#define CONFIG_ATMEL_NAND_HW_PMECC
|
||||
#endif
|
||||
|
||||
/* SPL */
|
||||
|
@ -63,8 +60,6 @@
|
|||
#define CONFIG_SPL_NAND_DRIVERS
|
||||
#define CONFIG_SPL_NAND_BASE
|
||||
#endif
|
||||
#define CONFIG_PMECC_CAP 8
|
||||
#define CONFIG_PMECC_SECTOR_SIZE 512
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
|
||||
|
@ -72,6 +67,5 @@
|
|||
#define CONFIG_SYS_NAND_OOBSIZE 224
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
|
||||
|
||||
#endif
|
||||
|
|
|
@ -35,7 +35,6 @@
|
|||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
|
||||
|
||||
/* NAND Flash */
|
||||
#define CONFIG_ATMEL_NAND_HWECC
|
||||
#define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
|
||||
|
|
|
@ -48,12 +48,6 @@
|
|||
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
|
||||
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
|
||||
|
||||
/* PMECC & PMERRLOC */
|
||||
#define CONFIG_ATMEL_NAND_HWECC 1
|
||||
#define CONFIG_ATMEL_NAND_HW_PMECC 1
|
||||
#define CONFIG_PMECC_CAP 4
|
||||
#define CONFIG_PMECC_SECTOR_SIZE 512
|
||||
|
||||
#define CONFIG_RBTREE
|
||||
#define CONFIG_LZO
|
||||
|
||||
|
@ -141,6 +135,5 @@
|
|||
#define CONFIG_SYS_NAND_OOBSIZE 64
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
|
||||
|
||||
#endif /* __CONFIG_H__ */
|
||||
|
|
|
@ -57,11 +57,6 @@
|
|||
/* our CLE is AD22 */
|
||||
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
/* PMECC & PMERRLOC */
|
||||
#define CONFIG_ATMEL_NAND_HWECC
|
||||
#define CONFIG_ATMEL_NAND_HW_PMECC
|
||||
#define CONFIG_PMECC_CAP 8
|
||||
#define CONFIG_PMECC_SECTOR_SIZE 512
|
||||
|
||||
/* Ethernet Hardware */
|
||||
#define CONFIG_MACB
|
||||
|
@ -118,6 +113,5 @@
|
|||
#define CONFIG_SYS_NAND_OOBSIZE 64
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
|
||||
|
||||
#endif
|
||||
|
|
|
@ -96,8 +96,6 @@ CONFIG_ATMEL_LCD_BGR555
|
|||
CONFIG_ATMEL_LCD_RGB565
|
||||
CONFIG_ATMEL_LEGACY
|
||||
CONFIG_ATMEL_MCI_8BIT
|
||||
CONFIG_ATMEL_NAND_HWECC
|
||||
CONFIG_ATMEL_NAND_HW_PMECC
|
||||
CONFIG_ATMEL_SPI0
|
||||
CONFIG_AT_TRANS
|
||||
CONFIG_AUTO_ZRELADDR
|
||||
|
@ -1502,8 +1500,6 @@ CONFIG_PLATINUM_PROJECT
|
|||
CONFIG_PM
|
||||
CONFIG_PMC_BR_PRELIM
|
||||
CONFIG_PMC_OR_PRELIM
|
||||
CONFIG_PMECC_CAP
|
||||
CONFIG_PMECC_SECTOR_SIZE
|
||||
CONFIG_PME_PLAT_CLK_DIV
|
||||
CONFIG_PMU
|
||||
CONFIG_PMW_BASE
|
||||
|
@ -1868,7 +1864,6 @@ CONFIG_SPL_FS_LOAD_ARGS_NAME
|
|||
CONFIG_SPL_FS_LOAD_KERNEL_NAME
|
||||
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
|
||||
CONFIG_SPL_GD_ADDR
|
||||
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
|
||||
CONFIG_SPL_INIT_MINIMAL
|
||||
CONFIG_SPL_JR0_LIODN_NS
|
||||
CONFIG_SPL_JR0_LIODN_S
|
||||
|
|
Loading…
Reference in a new issue