2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2015-07-02 05:59:02 +00:00
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/*
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armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.
SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:17:09 +00:00
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* Copyright 2015-2018 NXP
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2015-07-02 05:59:02 +00:00
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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*/
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#ifndef __FSL_STREAM_ID_H
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#define __FSL_STREAM_ID_H
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2016-03-10 16:52:07 +00:00
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/*
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2017-03-22 06:36:26 +00:00
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* Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a)
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* devices are not hardwired and are programmed by sw. There are a limited
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* number of stream IDs available, and the partitioning of them is scenario
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* dependent. This header defines the partitioning between legacy,
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* PCI, and DPAA2 devices.
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2015-07-02 05:59:02 +00:00
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*
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2016-03-10 16:52:07 +00:00
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* This partitioning can be customized in this file depending
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* on the specific hardware config:
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*
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* -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
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* -all legacy devices get a unique stream ID assigned and programmed in
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* their AMQR registers by u-boot
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*
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* -PCIe
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* -there is a range of stream IDs set aside for PCI in this
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* file. U-boot will scan the PCI bus and for each device discovered:
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* -allocate a streamID
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* -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
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* -set a msi-map entry in the PEXn controller node in the
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* device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
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* for more info on the msi-map definition)
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2017-03-22 06:36:26 +00:00
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* -set a iommu-map entry in the PEXn controller node in the
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* device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt
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* for more info on the iommu-map definition)
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2015-07-02 05:59:02 +00:00
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*
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2016-03-10 16:52:07 +00:00
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* -DPAA2
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* -u-boot will allocate a range of stream IDs to be used by the Management
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* Complex for containers and will set these values in the MC DPC image.
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2018-08-20 10:31:14 +00:00
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* -u-boot will fixup the iommu-map property in the fsl-mc node in the
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* device tree (see Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
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* for more info on the msi-map definition)
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2016-03-10 16:52:07 +00:00
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* -the MC is responsible for allocating and setting up 'isolation context
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* IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
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*
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2017-03-22 06:36:26 +00:00
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* On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for
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2015-07-02 05:59:02 +00:00
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* each of the different bus masters. The relationship between
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* the AMQ registers and stream IDs is defined in the table below:
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* AMQ bit streamID bit
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* ---------------------------
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2016-03-10 16:52:07 +00:00
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* PL[18] 9 // privilege bit
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* BMT[17] 8 // bypass translation
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* VA[16] 7 // reserved
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* [15] - // unused
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* ICID[14:7] - // unused
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* ICID[6:0] 6-0 // isolation context id
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2015-07-02 05:59:02 +00:00
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* ----------------------------
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2016-03-10 16:52:07 +00:00
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*
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2015-07-02 05:59:02 +00:00
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*/
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#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */
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#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */
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#define FSL_INVALID_STREAM_ID 0
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#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK)
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/* legacy devices */
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#define FSL_USB1_STREAM_ID 1
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#define FSL_USB2_STREAM_ID 2
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#define FSL_SDMMC_STREAM_ID 3
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#define FSL_SATA1_STREAM_ID 4
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armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:53 +00:00
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armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.
SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:17:09 +00:00
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#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
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2015-07-02 05:59:02 +00:00
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#define FSL_SATA2_STREAM_ID 5
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armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:53 +00:00
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#endif
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armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.
SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:17:09 +00:00
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#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
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2015-07-02 05:59:02 +00:00
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#define FSL_DMA_STREAM_ID 6
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2019-07-30 14:29:59 +00:00
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#elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
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armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:53 +00:00
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#define FSL_DMA_STREAM_ID 5
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#endif
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2015-07-02 05:59:02 +00:00
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2016-03-10 16:52:07 +00:00
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/* PCI - programmed in PEXn_LUT */
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#define FSL_PEX_STREAM_ID_START 7
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armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:53 +00:00
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armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.
SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:17:09 +00:00
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#ifdef CONFIG_ARCH_LX2160A
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#define FSL_PEX_STREAM_ID_NUM (0x100)
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#endif
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armv8: ls1028a: Add NXP LS1028A SoC support
Ls1028a SoC is based on Layerscape Chassis Generation 3.2
architecture with features:
2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN
ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers,
6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc.
Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-04-10 08:43:33 +00:00
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#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A)
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2016-03-10 16:52:07 +00:00
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#define FSL_PEX_STREAM_ID_END 22
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armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:53 +00:00
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#elif defined(CONFIG_ARCH_LS1088A)
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#define FSL_PEX_STREAM_ID_END 18
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#endif
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2015-07-02 05:59:02 +00:00
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/* DPAA2 - set in MC DPC and alloced by MC */
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#define FSL_DPAA2_STREAM_ID_START 23
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#define FSL_DPAA2_STREAM_ID_END 63
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2019-07-30 14:29:58 +00:00
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#define FSL_SEC_STREAM_ID 64
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#define FSL_SEC_JR1_STREAM_ID 65
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#define FSL_SEC_JR2_STREAM_ID 66
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#define FSL_SEC_JR3_STREAM_ID 67
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#define FSL_SEC_JR4_STREAM_ID 68
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2019-07-30 14:29:59 +00:00
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#define FSL_SDMMC2_STREAM_ID 69
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#define FSL_EDMA_STREAM_ID 70
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#define FSL_GPU_STREAM_ID 71
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#define FSL_DISPLAY_STREAM_ID 72
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2019-10-18 09:01:55 +00:00
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#define FSL_SATA3_STREAM_ID 73
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#define FSL_SATA4_STREAM_ID 74
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2019-07-30 14:29:59 +00:00
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2015-07-02 05:59:02 +00:00
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#endif
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