2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2003-10-15 23:53:47 +00:00
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/*
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2011-01-19 07:16:27 +00:00
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* Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
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2009-03-19 07:46:19 +00:00
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*
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2003-10-15 23:53:47 +00:00
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* (C) Copyright 2003 Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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#include <ppc_asm.tmpl>
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2011-02-11 07:25:30 +00:00
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#include <linux/compiler.h>
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2003-10-15 23:53:47 +00:00
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#include <asm/processor.h>
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mpc8[56]xx: Put localbus clock in sysinfo and gd
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.
This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.
The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.
get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.
checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-03 23:16:37 +00:00
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#include <asm/io.h>
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2003-10-15 23:53:47 +00:00
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2006-03-31 16:32:53 +00:00
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DECLARE_GLOBAL_DATA_PTR;
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2013-09-03 05:50:15 +00:00
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#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
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#endif
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2003-10-15 23:53:47 +00:00
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/* --------------------------------------------------------------- */
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2013-08-16 09:22:26 +00:00
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void get_sys_info(sys_info_t *sys_info)
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2003-10-15 23:53:47 +00:00
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{
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2008-10-16 13:01:15 +00:00
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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2009-03-19 07:46:19 +00:00
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#ifdef CONFIG_FSL_CORENET
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volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
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2011-08-05 21:15:24 +00:00
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unsigned int cpu;
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powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4860QDS:
U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
CPU0: B4860E, Version: 2.2, (0x86880022)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
CCB:666.667 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz
Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-19 07:16:54 +00:00
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#ifdef CONFIG_HETROGENOUS_CLUSTERS
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unsigned int dsp_cpu;
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uint rcw_tmp1, rcw_tmp2;
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#endif
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2013-09-03 05:50:15 +00:00
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
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#endif
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2014-10-27 18:31:33 +00:00
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__maybe_unused u32 svr;
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2009-03-19 07:46:19 +00:00
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const u8 core_cplx_PLL[16] = {
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[ 0] = 0, /* CC1 PPL / 1 */
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[ 1] = 0, /* CC1 PPL / 2 */
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[ 2] = 0, /* CC1 PPL / 4 */
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[ 4] = 1, /* CC2 PPL / 1 */
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[ 5] = 1, /* CC2 PPL / 2 */
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[ 6] = 1, /* CC2 PPL / 4 */
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[ 8] = 2, /* CC3 PPL / 1 */
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[ 9] = 2, /* CC3 PPL / 2 */
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[10] = 2, /* CC3 PPL / 4 */
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[12] = 3, /* CC4 PPL / 1 */
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[13] = 3, /* CC4 PPL / 2 */
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[14] = 3, /* CC4 PPL / 4 */
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};
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2013-08-16 09:22:26 +00:00
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const u8 core_cplx_pll_div[16] = {
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2009-03-19 07:46:19 +00:00
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[ 0] = 1, /* CC1 PPL / 1 */
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[ 1] = 2, /* CC1 PPL / 2 */
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[ 2] = 4, /* CC1 PPL / 4 */
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[ 4] = 1, /* CC2 PPL / 1 */
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[ 5] = 2, /* CC2 PPL / 2 */
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[ 6] = 4, /* CC2 PPL / 4 */
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[ 8] = 1, /* CC3 PPL / 1 */
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[ 9] = 2, /* CC3 PPL / 2 */
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[10] = 4, /* CC3 PPL / 4 */
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[12] = 1, /* CC4 PPL / 1 */
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[13] = 2, /* CC4 PPL / 2 */
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[14] = 4, /* CC4 PPL / 4 */
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};
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2013-09-03 05:50:15 +00:00
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uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
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2015-04-22 05:57:40 +00:00
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#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \
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defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
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2013-09-03 05:50:15 +00:00
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uint rcw_tmp;
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#endif
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uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
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2009-03-19 07:46:19 +00:00
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unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
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2010-02-10 09:32:43 +00:00
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uint mem_pll_rat;
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2009-03-19 07:46:19 +00:00
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2013-08-16 09:22:26 +00:00
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sys_info->freq_systembus = sysclk;
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2013-12-17 08:55:52 +00:00
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#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
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2014-04-15 06:04:12 +00:00
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uint ddr_refclk_sel;
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unsigned int porsr1_sys_clk;
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porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
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& FSL_DCFG_PORSR1_SYSCLK_MASK;
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if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
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sys_info->diff_sysclk = 1;
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else
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sys_info->diff_sysclk = 0;
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2013-12-17 08:55:52 +00:00
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/*
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* DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
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* are driven by separate DDR Refclock or single source
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* differential clock.
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*/
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2014-04-15 06:04:12 +00:00
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ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
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2013-12-17 08:55:52 +00:00
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FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
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FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
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/*
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2014-04-15 06:04:12 +00:00
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* For single source clocking, both ddrclock and sysclock
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2013-12-17 08:55:52 +00:00
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* are driven by differential sysclock.
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*/
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2014-04-15 06:04:12 +00:00
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if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
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2013-12-17 08:55:52 +00:00
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sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
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2014-04-15 06:04:12 +00:00
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else
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2013-12-17 08:55:52 +00:00
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#endif
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2012-10-08 07:44:31 +00:00
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#ifdef CONFIG_DDR_CLK_FREQ
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2013-12-17 08:55:52 +00:00
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sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
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2012-10-08 07:44:31 +00:00
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#else
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2013-12-17 08:55:52 +00:00
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sys_info->freq_ddrbus = sysclk;
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2012-10-08 07:44:31 +00:00
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#endif
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2009-03-19 07:46:19 +00:00
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2013-08-16 09:22:26 +00:00
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sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
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2012-10-08 07:44:09 +00:00
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mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
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FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
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& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
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2014-03-28 22:07:27 +00:00
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#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
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if (mem_pll_rat == 0) {
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mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
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FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
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FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
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}
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#endif
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2013-11-28 05:23:37 +00:00
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/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
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* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
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* it uses 6.
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2014-10-27 18:31:33 +00:00
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* T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
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2013-11-28 05:23:37 +00:00
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*/
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2016-11-21 21:35:41 +00:00
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#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
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2016-11-21 21:41:30 +00:00
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defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
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2014-10-27 18:31:33 +00:00
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svr = get_svr();
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switch (SVR_SOC_VER(svr)) {
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case SVR_T4240:
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case SVR_T4160:
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case SVR_T4120:
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case SVR_T4080:
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if (SVR_MAJ(svr) >= 2)
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mem_pll_rat *= 2;
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break;
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case SVR_T2080:
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case SVR_T2081:
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if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))
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mem_pll_rat *= 2;
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break;
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default:
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break;
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}
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2013-11-28 05:23:37 +00:00
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#endif
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2010-02-10 09:32:43 +00:00
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if (mem_pll_rat > 2)
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2013-08-16 09:22:26 +00:00
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sys_info->freq_ddrbus *= mem_pll_rat;
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2010-02-10 09:32:43 +00:00
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else
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2013-08-16 09:22:26 +00:00
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sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
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2009-03-19 07:46:19 +00:00
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2013-09-03 05:50:15 +00:00
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for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
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ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
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2010-02-10 09:32:43 +00:00
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if (ratio[i] > 4)
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2013-09-03 05:50:15 +00:00
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freq_c_pll[i] = sysclk * ratio[i];
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2010-02-10 09:32:43 +00:00
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else
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2013-09-03 05:50:15 +00:00
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freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
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2010-02-10 09:32:43 +00:00
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}
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powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4860QDS:
U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
CPU0: B4860E, Version: 2.2, (0x86880022)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
CCB:666.667 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz
Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-19 07:16:54 +00:00
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2012-10-08 07:44:11 +00:00
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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/*
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2013-09-03 05:50:15 +00:00
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* As per CHASSIS2 architeture total 12 clusters are posible and
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2012-10-08 07:44:11 +00:00
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* Each cluster has up to 4 cores, sharing the same PLL selection.
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2013-09-03 05:50:15 +00:00
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* The cluster clock assignment is SoC defined.
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*
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* Total 4 clock groups are possible with 3 PLLs each.
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* as per array indices, clock group A has 0, 1, 2 numbered PLLs &
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* clock group B has 3, 4, 6 and so on.
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*
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* Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
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* depends upon the SoC architeture. Same applies to other
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* clock groups and clusters.
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*
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2012-10-08 07:44:11 +00:00
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*/
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2011-08-05 21:15:24 +00:00
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for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
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2013-03-25 07:40:07 +00:00
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int cluster = fsl_qoriq_core_to_cluster(cpu);
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u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
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2012-10-08 07:44:11 +00:00
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& 0xf;
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2009-03-19 07:46:19 +00:00
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u32 cplx_pll = core_cplx_PLL[c_pll_sel];
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2013-09-03 05:50:15 +00:00
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cplx_pll += cc_group[cluster] - 1;
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2013-08-16 09:22:26 +00:00
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sys_info->freq_processor[cpu] =
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2013-09-03 05:50:15 +00:00
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freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
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2009-03-19 07:46:19 +00:00
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}
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powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4860QDS:
U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
CPU0: B4860E, Version: 2.2, (0x86880022)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
CCB:666.667 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz
Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-19 07:16:54 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_HETROGENOUS_CLUSTERS
|
|
|
|
|
for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {
|
|
|
|
|
int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
|
|
|
|
|
u32 c_pll_sel = (in_be32
|
|
|
|
|
(&clk->clkcsr[dsp_cluster].clkcncsr) >> 27)
|
|
|
|
|
& 0xf;
|
|
|
|
|
u32 cplx_pll = core_cplx_PLL[c_pll_sel];
|
|
|
|
|
cplx_pll += cc_group[dsp_cluster] - 1;
|
|
|
|
|
sys_info->freq_processor_dsp[dsp_cpu] =
|
|
|
|
|
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2016-11-18 19:56:57 +00:00
|
|
|
#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
|
2016-11-21 20:54:19 +00:00
|
|
|
defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
|
2013-03-25 07:33:09 +00:00
|
|
|
#define FM1_CLK_SEL 0xe0000000
|
|
|
|
|
#define FM1_CLK_SHIFT 29
|
2016-11-18 21:01:34 +00:00
|
|
|
#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
|
2014-11-24 09:11:54 +00:00
|
|
|
#define FM1_CLK_SEL 0x00000007
|
|
|
|
|
#define FM1_CLK_SHIFT 0
|
2013-03-25 07:33:09 +00:00
|
|
|
#else
|
2012-10-08 07:44:11 +00:00
|
|
|
#define PME_CLK_SEL 0xe0000000
|
|
|
|
|
#define PME_CLK_SHIFT 29
|
|
|
|
|
#define FM1_CLK_SEL 0x1c000000
|
|
|
|
|
#define FM1_CLK_SHIFT 26
|
2013-03-25 07:33:09 +00:00
|
|
|
#endif
|
2013-09-03 05:50:15 +00:00
|
|
|
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
|
2016-11-18 21:01:34 +00:00
|
|
|
#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
|
2014-11-24 09:11:54 +00:00
|
|
|
rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
|
|
|
|
|
#else
|
2012-10-08 07:44:11 +00:00
|
|
|
rcw_tmp = in_be32(&gur->rcwsr[7]);
|
2013-09-03 05:50:15 +00:00
|
|
|
#endif
|
2014-11-24 09:11:54 +00:00
|
|
|
#endif
|
2012-10-08 07:44:11 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_SYS_DPAA_PME
|
2013-09-03 05:50:15 +00:00
|
|
|
#ifndef CONFIG_PME_PLAT_CLK_DIV
|
2012-10-08 07:44:11 +00:00
|
|
|
switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
|
|
|
|
|
case 1:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
case 2:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
case 3:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
case 4:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
case 6:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
case 7:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
printf("Error: Unknown PME clock select!\n");
|
|
|
|
|
case 0:
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_pme = sys_info->freq_systembus / 2;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
}
|
2013-09-03 05:50:15 +00:00
|
|
|
#else
|
|
|
|
|
sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
|
|
|
|
|
|
|
|
|
|
#endif
|
2012-10-08 07:44:11 +00:00
|
|
|
#endif
|
|
|
|
|
|
2012-10-11 07:13:39 +00:00
|
|
|
#ifdef CONFIG_SYS_DPAA_QBMAN
|
2014-11-24 09:11:54 +00:00
|
|
|
#ifndef CONFIG_QBMAN_CLK_DIV
|
|
|
|
|
#define CONFIG_QBMAN_CLK_DIV 2
|
|
|
|
|
#endif
|
|
|
|
|
sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
|
2012-10-11 07:13:39 +00:00
|
|
|
#endif
|
|
|
|
|
|
powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4860QDS:
U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
CPU0: B4860E, Version: 2.2, (0x86880022)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
CCB:666.667 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz
Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-19 07:16:54 +00:00
|
|
|
#if defined(CONFIG_SYS_MAPLE)
|
|
|
|
|
#define CPRI_CLK_SEL 0x1C000000
|
|
|
|
|
#define CPRI_CLK_SHIFT 26
|
|
|
|
|
#define CPRI_ALT_CLK_SEL 0x00007000
|
|
|
|
|
#define CPRI_ALT_CLK_SHIFT 12
|
|
|
|
|
|
|
|
|
|
rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/
|
|
|
|
|
rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/
|
|
|
|
|
/* For MAPLE and CPRI frequency */
|
|
|
|
|
switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) {
|
|
|
|
|
case 1:
|
|
|
|
|
sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK];
|
|
|
|
|
sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK];
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
|
|
|
|
|
sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
|
|
|
|
|
sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
|
|
|
|
|
break;
|
|
|
|
|
case 4:
|
|
|
|
|
sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
|
|
|
|
|
sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
|
|
|
|
|
break;
|
|
|
|
|
case 5:
|
|
|
|
|
if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
|
|
|
|
|
>> CPRI_ALT_CLK_SHIFT) == 6) {
|
|
|
|
|
sys_info->freq_maple =
|
|
|
|
|
freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
|
|
|
|
|
sys_info->freq_cpri =
|
|
|
|
|
freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
|
|
|
|
|
}
|
|
|
|
|
if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
|
|
|
|
|
>> CPRI_ALT_CLK_SHIFT) == 7) {
|
|
|
|
|
sys_info->freq_maple =
|
|
|
|
|
freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
|
|
|
|
|
sys_info->freq_cpri =
|
|
|
|
|
freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 6:
|
|
|
|
|
sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
|
|
|
|
|
sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
|
|
|
|
|
break;
|
|
|
|
|
case 7:
|
|
|
|
|
sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
|
|
|
|
|
sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
printf("Error: Unknown MAPLE/CPRI clock select!\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* For MAPLE ULB and eTVPE frequencies */
|
|
|
|
|
#define ULB_CLK_SEL 0x00000038
|
|
|
|
|
#define ULB_CLK_SHIFT 3
|
|
|
|
|
#define ETVPE_CLK_SEL 0x00000007
|
|
|
|
|
#define ETVPE_CLK_SHIFT 0
|
|
|
|
|
|
|
|
|
|
switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) {
|
|
|
|
|
case 1:
|
|
|
|
|
sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK];
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2;
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3;
|
|
|
|
|
break;
|
|
|
|
|
case 4:
|
|
|
|
|
sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4;
|
|
|
|
|
break;
|
|
|
|
|
case 5:
|
|
|
|
|
sys_info->freq_maple_ulb = sys_info->freq_systembus;
|
|
|
|
|
break;
|
|
|
|
|
case 6:
|
|
|
|
|
sys_info->freq_maple_ulb =
|
|
|
|
|
freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2;
|
|
|
|
|
break;
|
|
|
|
|
case 7:
|
|
|
|
|
sys_info->freq_maple_ulb =
|
|
|
|
|
freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
printf("Error: Unknown MAPLE ULB clock select!\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) {
|
|
|
|
|
case 1:
|
|
|
|
|
sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK];
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
sys_info->freq_maple_etvpe =
|
|
|
|
|
freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2;
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
sys_info->freq_maple_etvpe =
|
|
|
|
|
freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3;
|
|
|
|
|
break;
|
|
|
|
|
case 4:
|
|
|
|
|
sys_info->freq_maple_etvpe =
|
|
|
|
|
freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4;
|
|
|
|
|
break;
|
|
|
|
|
case 5:
|
|
|
|
|
sys_info->freq_maple_etvpe = sys_info->freq_systembus;
|
|
|
|
|
break;
|
|
|
|
|
case 6:
|
|
|
|
|
sys_info->freq_maple_etvpe =
|
|
|
|
|
freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2;
|
|
|
|
|
break;
|
|
|
|
|
case 7:
|
|
|
|
|
sys_info->freq_maple_etvpe =
|
|
|
|
|
freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
printf("Error: Unknown MAPLE eTVPE clock select!\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
2012-10-08 07:44:11 +00:00
|
|
|
#ifdef CONFIG_SYS_DPAA_FMAN
|
2013-09-03 05:50:15 +00:00
|
|
|
#ifndef CONFIG_FM_PLAT_CLK_DIV
|
2012-10-08 07:44:11 +00:00
|
|
|
switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
|
|
|
|
|
case 1:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
case 2:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
case 3:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
case 4:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
2013-03-25 07:33:09 +00:00
|
|
|
case 5:
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_fman[0] = sys_info->freq_systembus;
|
2013-03-25 07:33:09 +00:00
|
|
|
break;
|
2012-10-08 07:44:11 +00:00
|
|
|
case 6:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
case 7:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
printf("Error: Unknown FMan1 clock select!\n");
|
|
|
|
|
case 0:
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
#if (CONFIG_SYS_NUM_FMAN) == 2
|
2013-09-03 05:50:15 +00:00
|
|
|
#ifdef CONFIG_SYS_FM2_CLK
|
2012-10-08 07:44:11 +00:00
|
|
|
#define FM2_CLK_SEL 0x00000038
|
|
|
|
|
#define FM2_CLK_SHIFT 3
|
|
|
|
|
rcw_tmp = in_be32(&gur->rcwsr[15]);
|
|
|
|
|
switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
|
|
|
|
|
case 1:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
case 2:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
case 3:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
case 4:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
2013-11-28 05:52:51 +00:00
|
|
|
case 5:
|
|
|
|
|
sys_info->freq_fman[1] = sys_info->freq_systembus;
|
|
|
|
|
break;
|
2012-10-08 07:44:11 +00:00
|
|
|
case 6:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
case 7:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
printf("Error: Unknown FMan2 clock select!\n");
|
|
|
|
|
case 0:
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
}
|
2013-09-03 05:50:15 +00:00
|
|
|
#endif
|
2012-10-08 07:44:11 +00:00
|
|
|
#endif /* CONFIG_SYS_NUM_FMAN == 2 */
|
2013-09-03 05:50:15 +00:00
|
|
|
#else
|
|
|
|
|
sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
|
|
|
|
|
#endif
|
|
|
|
|
#endif
|
2009-03-19 07:46:19 +00:00
|
|
|
|
2015-04-22 05:57:40 +00:00
|
|
|
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
|
2016-11-21 20:54:19 +00:00
|
|
|
#if defined(CONFIG_ARCH_T2080)
|
2015-04-22 05:57:40 +00:00
|
|
|
#define ESDHC_CLK_SEL 0x00000007
|
|
|
|
|
#define ESDHC_CLK_SHIFT 0
|
|
|
|
|
#define ESDHC_CLK_RCWSR 15
|
|
|
|
|
#else /* Support T1040 T1024 by now */
|
|
|
|
|
#define ESDHC_CLK_SEL 0xe0000000
|
|
|
|
|
#define ESDHC_CLK_SHIFT 29
|
|
|
|
|
#define ESDHC_CLK_RCWSR 7
|
|
|
|
|
#endif
|
|
|
|
|
rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]);
|
|
|
|
|
switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) {
|
|
|
|
|
case 1:
|
|
|
|
|
sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK];
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2;
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3;
|
|
|
|
|
break;
|
|
|
|
|
#if defined(CONFIG_SYS_SDHC_CLK_2_PLL)
|
|
|
|
|
case 4:
|
|
|
|
|
sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
|
|
|
|
|
break;
|
2016-11-21 20:54:19 +00:00
|
|
|
#if defined(CONFIG_ARCH_T2080)
|
2015-04-22 05:57:40 +00:00
|
|
|
case 5:
|
|
|
|
|
sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
case 6:
|
|
|
|
|
sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2;
|
|
|
|
|
break;
|
|
|
|
|
case 7:
|
|
|
|
|
sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
default:
|
|
|
|
|
sys_info->freq_sdhc = 0;
|
|
|
|
|
printf("Error: Unknown SDHC peripheral clock select!\n");
|
|
|
|
|
}
|
|
|
|
|
#endif
|
2012-10-08 07:44:11 +00:00
|
|
|
#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
|
|
|
|
|
|
|
|
|
|
for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
|
2013-03-25 07:40:07 +00:00
|
|
|
u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
|
|
|
|
|
& 0xf;
|
2012-10-08 07:44:11 +00:00
|
|
|
u32 cplx_pll = core_cplx_PLL[c_pll_sel];
|
|
|
|
|
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_processor[cpu] =
|
2013-09-03 05:50:15 +00:00
|
|
|
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
|
2012-10-08 07:44:11 +00:00
|
|
|
}
|
2009-03-19 07:46:19 +00:00
|
|
|
#define PME_CLK_SEL 0x80000000
|
|
|
|
|
#define FM1_CLK_SEL 0x40000000
|
|
|
|
|
#define FM2_CLK_SEL 0x20000000
|
2011-02-16 08:03:29 +00:00
|
|
|
#define HWA_ASYNC_DIV 0x04000000
|
|
|
|
|
#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
|
|
|
|
|
#define HWA_CC_PLL 1
|
powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-05 11:09:19 +00:00
|
|
|
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
|
|
|
|
|
#define HWA_CC_PLL 2
|
2011-02-16 08:03:29 +00:00
|
|
|
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
|
2011-05-19 20:21:41 +00:00
|
|
|
#define HWA_CC_PLL 2
|
2011-02-16 08:03:29 +00:00
|
|
|
#else
|
|
|
|
|
#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
|
|
|
|
|
#endif
|
2009-03-19 07:46:19 +00:00
|
|
|
rcw_tmp = in_be32(&gur->rcwsr[7]);
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_SYS_DPAA_PME
|
2011-02-16 08:03:29 +00:00
|
|
|
if (rcw_tmp & PME_CLK_SEL) {
|
|
|
|
|
if (rcw_tmp & HWA_ASYNC_DIV)
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
|
2011-02-16 08:03:29 +00:00
|
|
|
else
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
|
2011-02-16 08:03:29 +00:00
|
|
|
} else {
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_pme = sys_info->freq_systembus / 2;
|
2011-02-16 08:03:29 +00:00
|
|
|
}
|
2009-03-19 07:46:19 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_SYS_DPAA_FMAN
|
2011-02-16 08:03:29 +00:00
|
|
|
if (rcw_tmp & FM1_CLK_SEL) {
|
|
|
|
|
if (rcw_tmp & HWA_ASYNC_DIV)
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
|
2011-02-16 08:03:29 +00:00
|
|
|
else
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
|
2011-02-16 08:03:29 +00:00
|
|
|
} else {
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
|
2011-02-16 08:03:29 +00:00
|
|
|
}
|
2009-03-19 07:46:19 +00:00
|
|
|
#if (CONFIG_SYS_NUM_FMAN) == 2
|
2011-02-16 08:03:29 +00:00
|
|
|
if (rcw_tmp & FM2_CLK_SEL) {
|
|
|
|
|
if (rcw_tmp & HWA_ASYNC_DIV)
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
|
2011-02-16 08:03:29 +00:00
|
|
|
else
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
|
2011-02-16 08:03:29 +00:00
|
|
|
} else {
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
|
2011-02-16 08:03:29 +00:00
|
|
|
}
|
2009-03-19 07:46:19 +00:00
|
|
|
#endif
|
|
|
|
|
#endif
|
|
|
|
|
|
2013-03-25 07:33:25 +00:00
|
|
|
#ifdef CONFIG_SYS_DPAA_QBMAN
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_qman = sys_info->freq_systembus / 2;
|
2013-03-25 07:33:25 +00:00
|
|
|
#endif
|
|
|
|
|
|
2012-10-08 07:44:11 +00:00
|
|
|
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
|
|
|
|
|
|
2014-03-21 08:21:45 +00:00
|
|
|
#ifdef CONFIG_U_QE
|
|
|
|
|
sys_info->freq_qe = sys_info->freq_systembus / 2;
|
|
|
|
|
#endif
|
|
|
|
|
|
2012-10-08 07:44:11 +00:00
|
|
|
#else /* CONFIG_FSL_CORENET */
|
2013-08-16 09:22:26 +00:00
|
|
|
uint plat_ratio, e500_ratio, half_freq_systembus;
|
2009-01-15 16:58:35 +00:00
|
|
|
int i;
|
2009-05-20 16:30:29 +00:00
|
|
|
#ifdef CONFIG_QE
|
2011-02-11 07:25:30 +00:00
|
|
|
__maybe_unused u32 qe_ratio;
|
2009-05-20 16:30:29 +00:00
|
|
|
#endif
|
2003-10-15 23:53:47 +00:00
|
|
|
|
|
|
|
|
plat_ratio = (gur->porpllsr) & 0x0000003e;
|
|
|
|
|
plat_ratio >>= 1;
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
|
2007-04-23 07:37:47 +00:00
|
|
|
|
|
|
|
|
/* Divide before multiply to avoid integer
|
|
|
|
|
* overflow for processor speeds above 2GHz */
|
2013-08-16 09:22:26 +00:00
|
|
|
half_freq_systembus = sys_info->freq_systembus/2;
|
2009-07-31 06:38:14 +00:00
|
|
|
for (i = 0; i < cpu_numcores(); i++) {
|
2009-01-15 16:58:35 +00:00
|
|
|
e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
|
2009-01-15 16:58:35 +00:00
|
|
|
}
|
2008-02-09 00:05:08 +00:00
|
|
|
|
2013-08-16 09:22:26 +00:00
|
|
|
/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
|
|
|
|
|
sys_info->freq_ddrbus = sys_info->freq_systembus;
|
2007-12-07 10:59:26 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_DDR_CLK_FREQ
|
|
|
|
|
{
|
2008-09-27 06:40:57 +00:00
|
|
|
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
|
|
|
|
|
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
|
2007-12-07 10:59:26 +00:00
|
|
|
if (ddr_ratio != 0x7)
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
|
2007-12-07 10:59:26 +00:00
|
|
|
}
|
|
|
|
|
#endif
|
mpc8[56]xx: Put localbus clock in sysinfo and gd
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.
This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.
The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.
get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.
checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-03 23:16:37 +00:00
|
|
|
|
2009-05-20 16:30:29 +00:00
|
|
|
#ifdef CONFIG_QE
|
2016-11-18 19:05:38 +00:00
|
|
|
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_qe = sys_info->freq_systembus;
|
2011-02-11 07:25:30 +00:00
|
|
|
#else
|
2009-05-20 16:30:29 +00:00
|
|
|
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
|
|
|
|
|
>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
|
2009-05-20 16:30:29 +00:00
|
|
|
#endif
|
2011-02-11 07:25:30 +00:00
|
|
|
#endif
|
2009-05-20 16:30:29 +00:00
|
|
|
|
2011-01-20 22:26:31 +00:00
|
|
|
#ifdef CONFIG_SYS_DPAA_FMAN
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_fman[0] = sys_info->freq_systembus;
|
2011-01-20 22:26:31 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#endif /* CONFIG_FSL_CORENET */
|
|
|
|
|
|
2011-01-19 07:16:27 +00:00
|
|
|
#if defined(CONFIG_FSL_LBC)
|
2017-02-02 09:32:00 +00:00
|
|
|
sys_info->freq_localbus = sys_info->freq_systembus /
|
|
|
|
|
CONFIG_SYS_FSL_LBC_CLK_DIV;
|
2011-01-19 07:16:27 +00:00
|
|
|
#endif
|
2012-10-08 07:44:06 +00:00
|
|
|
|
|
|
|
|
#if defined(CONFIG_FSL_IFC)
|
2017-02-02 09:31:26 +00:00
|
|
|
sys_info->freq_localbus = sys_info->freq_systembus /
|
|
|
|
|
CONFIG_SYS_FSL_IFC_CLK_DIV;
|
2012-10-08 07:44:06 +00:00
|
|
|
#endif
|
2003-10-15 23:53:47 +00:00
|
|
|
}
|
|
|
|
|
|
2007-04-23 07:37:47 +00:00
|
|
|
|
2003-10-15 23:53:47 +00:00
|
|
|
int get_clocks (void)
|
|
|
|
|
{
|
|
|
|
|
sys_info_t sys_info;
|
2016-11-15 21:57:15 +00:00
|
|
|
#ifdef CONFIG_ARCH_MPC8544
|
2008-10-16 13:01:15 +00:00
|
|
|
volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
2008-04-04 16:15:58 +00:00
|
|
|
#endif
|
2005-07-23 15:37:35 +00:00
|
|
|
#if defined(CONFIG_CPM2)
|
2008-10-16 13:01:15 +00:00
|
|
|
volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
|
2003-10-15 23:53:47 +00:00
|
|
|
uint sccr, dfbrg;
|
|
|
|
|
|
|
|
|
|
/* set VCO = 4 * BRG */
|
2007-11-28 06:36:33 +00:00
|
|
|
cpm->im_cpm_intctl.sccr &= 0xfffffffc;
|
|
|
|
|
sccr = cpm->im_cpm_intctl.sccr;
|
2003-10-15 23:53:47 +00:00
|
|
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dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
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|
|
|
|
#endif
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|
|
|
|
get_sys_info (&sys_info);
|
2013-08-16 09:22:26 +00:00
|
|
|
gd->cpu_clk = sys_info.freq_processor[0];
|
|
|
|
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gd->bus_clk = sys_info.freq_systembus;
|
|
|
|
|
gd->mem_clk = sys_info.freq_ddrbus;
|
|
|
|
|
gd->arch.lbc_clk = sys_info.freq_localbus;
|
2008-04-04 16:15:58 +00:00
|
|
|
|
2009-05-20 16:30:29 +00:00
|
|
|
#ifdef CONFIG_QE
|
2013-08-16 09:22:26 +00:00
|
|
|
gd->arch.qe_clk = sys_info.freq_qe;
|
2012-12-13 20:48:50 +00:00
|
|
|
gd->arch.brg_clk = gd->arch.qe_clk / 2;
|
2009-05-20 16:30:29 +00:00
|
|
|
#endif
|
2008-04-04 16:15:58 +00:00
|
|
|
/*
|
|
|
|
|
* The base clock for I2C depends on the actual SOC. Unfortunately,
|
|
|
|
|
* there is no pattern that can be used to determine the frequency, so
|
|
|
|
|
* the only choice is to look up the actual SOC number and use the value
|
|
|
|
|
* for that SOC. This information is taken from application note
|
|
|
|
|
* AN2919.
|
|
|
|
|
*/
|
2016-11-16 19:18:31 +00:00
|
|
|
#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
|
2016-11-16 19:26:45 +00:00
|
|
|
defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
|
2016-11-16 23:23:52 +00:00
|
|
|
defined(CONFIG_ARCH_P1022)
|
2013-08-16 09:22:26 +00:00
|
|
|
gd->arch.i2c1_clk = sys_info.freq_systembus;
|
2016-11-15 21:57:15 +00:00
|
|
|
#elif defined(CONFIG_ARCH_MPC8544)
|
2008-04-04 16:15:58 +00:00
|
|
|
/*
|
|
|
|
|
* On the 8544, the I2C clock is the same as the SEC clock. This can be
|
|
|
|
|
* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
|
|
|
|
|
* 4.4.3.3 of the 8544 RM. Note that this might actually work for all
|
|
|
|
|
* 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
|
|
|
|
|
* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
|
|
|
|
|
*/
|
|
|
|
|
if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
|
2013-08-16 09:22:26 +00:00
|
|
|
gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
|
2008-10-17 02:58:49 +00:00
|
|
|
else
|
2013-08-16 09:22:26 +00:00
|
|
|
gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
|
2008-04-04 16:15:58 +00:00
|
|
|
#else
|
|
|
|
|
/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
|
2013-08-16 09:22:26 +00:00
|
|
|
gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
|
2008-04-04 16:15:58 +00:00
|
|
|
#endif
|
2012-12-13 20:48:49 +00:00
|
|
|
gd->arch.i2c2_clk = gd->arch.i2c1_clk;
|
2008-01-09 20:35:26 +00:00
|
|
|
|
2009-09-01 11:57:00 +00:00
|
|
|
#if defined(CONFIG_FSL_ESDHC)
|
2015-04-22 05:57:40 +00:00
|
|
|
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
|
|
|
|
|
gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
|
|
|
|
|
#else
|
2016-11-17 00:02:09 +00:00
|
|
|
#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010)
|
2012-12-13 20:49:05 +00:00
|
|
|
gd->arch.sdhc_clk = gd->bus_clk;
|
2009-10-15 13:47:06 +00:00
|
|
|
#else
|
2012-12-13 20:49:05 +00:00
|
|
|
gd->arch.sdhc_clk = gd->bus_clk / 2;
|
2008-08-12 16:14:19 +00:00
|
|
|
#endif
|
2015-04-22 05:57:40 +00:00
|
|
|
#endif
|
2009-10-15 13:47:06 +00:00
|
|
|
#endif /* defined(CONFIG_FSL_ESDHC) */
|
2008-08-12 16:14:19 +00:00
|
|
|
|
2005-07-23 15:37:35 +00:00
|
|
|
#if defined(CONFIG_CPM2)
|
2013-08-16 09:22:26 +00:00
|
|
|
gd->arch.vco_out = 2*sys_info.freq_systembus;
|
2012-12-13 20:48:46 +00:00
|
|
|
gd->arch.cpm_clk = gd->arch.vco_out / 2;
|
|
|
|
|
gd->arch.scc_clk = gd->arch.vco_out / 4;
|
|
|
|
|
gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
|
2003-10-15 23:53:47 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
if(gd->cpu_clk != 0) return (0);
|
|
|
|
|
else return (1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/********************************************
|
|
|
|
|
* get_bus_freq
|
|
|
|
|
* return system bus freq in Hz
|
|
|
|
|
*********************************************/
|
|
|
|
|
ulong get_bus_freq (ulong dummy)
|
|
|
|
|
{
|
2008-02-09 00:05:08 +00:00
|
|
|
return gd->bus_clk;
|
2003-10-15 23:53:47 +00:00
|
|
|
}
|
2007-12-07 10:59:26 +00:00
|
|
|
|
|
|
|
|
/********************************************
|
|
|
|
|
* get_ddr_freq
|
|
|
|
|
* return ddr bus freq in Hz
|
|
|
|
|
*********************************************/
|
|
|
|
|
ulong get_ddr_freq (ulong dummy)
|
|
|
|
|
{
|
2008-02-09 00:05:08 +00:00
|
|
|
return gd->mem_clk;
|
2007-12-07 10:59:26 +00:00
|
|
|
}
|
