2003-10-15 23:53:47 +00:00
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/*
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2011-01-19 07:16:27 +00:00
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* Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
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2009-03-19 07:46:19 +00:00
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*
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2003-10-15 23:53:47 +00:00
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* (C) Copyright 2003 Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2003-10-15 23:53:47 +00:00
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*/
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#include <common.h>
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#include <ppc_asm.tmpl>
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2011-02-11 07:25:30 +00:00
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#include <linux/compiler.h>
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2003-10-15 23:53:47 +00:00
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#include <asm/processor.h>
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mpc8[56]xx: Put localbus clock in sysinfo and gd
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.
This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.
The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.
get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.
checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-03 23:16:37 +00:00
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#include <asm/io.h>
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2003-10-15 23:53:47 +00:00
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2006-03-31 16:32:53 +00:00
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DECLARE_GLOBAL_DATA_PTR;
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2013-09-03 05:50:15 +00:00
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#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
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#endif
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2003-10-15 23:53:47 +00:00
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/* --------------------------------------------------------------- */
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2013-08-16 09:22:26 +00:00
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void get_sys_info(sys_info_t *sys_info)
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2003-10-15 23:53:47 +00:00
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{
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2008-10-16 13:01:15 +00:00
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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2012-10-08 07:44:06 +00:00
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#ifdef CONFIG_FSL_IFC
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struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
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u32 ccr;
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#endif
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2009-03-19 07:46:19 +00:00
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#ifdef CONFIG_FSL_CORENET
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volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
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2011-08-05 21:15:24 +00:00
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unsigned int cpu;
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2013-09-03 05:50:15 +00:00
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
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#endif
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2009-03-19 07:46:19 +00:00
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const u8 core_cplx_PLL[16] = {
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[ 0] = 0, /* CC1 PPL / 1 */
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[ 1] = 0, /* CC1 PPL / 2 */
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[ 2] = 0, /* CC1 PPL / 4 */
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[ 4] = 1, /* CC2 PPL / 1 */
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[ 5] = 1, /* CC2 PPL / 2 */
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[ 6] = 1, /* CC2 PPL / 4 */
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[ 8] = 2, /* CC3 PPL / 1 */
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[ 9] = 2, /* CC3 PPL / 2 */
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[10] = 2, /* CC3 PPL / 4 */
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[12] = 3, /* CC4 PPL / 1 */
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[13] = 3, /* CC4 PPL / 2 */
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[14] = 3, /* CC4 PPL / 4 */
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};
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2013-08-16 09:22:26 +00:00
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const u8 core_cplx_pll_div[16] = {
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2009-03-19 07:46:19 +00:00
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[ 0] = 1, /* CC1 PPL / 1 */
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[ 1] = 2, /* CC1 PPL / 2 */
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[ 2] = 4, /* CC1 PPL / 4 */
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[ 4] = 1, /* CC2 PPL / 1 */
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[ 5] = 2, /* CC2 PPL / 2 */
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[ 6] = 4, /* CC2 PPL / 4 */
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[ 8] = 1, /* CC3 PPL / 1 */
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[ 9] = 2, /* CC3 PPL / 2 */
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[10] = 4, /* CC3 PPL / 4 */
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[12] = 1, /* CC4 PPL / 1 */
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[13] = 2, /* CC4 PPL / 2 */
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[14] = 4, /* CC4 PPL / 4 */
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};
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2013-09-03 05:50:15 +00:00
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uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
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#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
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uint rcw_tmp;
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#endif
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uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
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2009-03-19 07:46:19 +00:00
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unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
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2010-02-10 09:32:43 +00:00
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uint mem_pll_rat;
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2009-03-19 07:46:19 +00:00
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2013-08-16 09:22:26 +00:00
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sys_info->freq_systembus = sysclk;
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2012-10-08 07:44:31 +00:00
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#ifdef CONFIG_DDR_CLK_FREQ
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2013-08-16 09:22:26 +00:00
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sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
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2012-10-08 07:44:31 +00:00
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#else
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2013-08-16 09:22:26 +00:00
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sys_info->freq_ddrbus = sysclk;
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2012-10-08 07:44:31 +00:00
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#endif
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2009-03-19 07:46:19 +00:00
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2013-08-16 09:22:26 +00:00
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sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
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2012-10-08 07:44:09 +00:00
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mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
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FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
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& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
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2010-02-10 09:32:43 +00:00
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if (mem_pll_rat > 2)
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2013-08-16 09:22:26 +00:00
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sys_info->freq_ddrbus *= mem_pll_rat;
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2010-02-10 09:32:43 +00:00
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else
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2013-08-16 09:22:26 +00:00
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sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
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2009-03-19 07:46:19 +00:00
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2013-09-03 05:50:15 +00:00
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for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
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ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
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2010-02-10 09:32:43 +00:00
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if (ratio[i] > 4)
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2013-09-03 05:50:15 +00:00
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freq_c_pll[i] = sysclk * ratio[i];
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2010-02-10 09:32:43 +00:00
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else
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2013-09-03 05:50:15 +00:00
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freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
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2010-02-10 09:32:43 +00:00
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}
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2012-10-08 07:44:11 +00:00
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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/*
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2013-09-03 05:50:15 +00:00
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* As per CHASSIS2 architeture total 12 clusters are posible and
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2012-10-08 07:44:11 +00:00
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* Each cluster has up to 4 cores, sharing the same PLL selection.
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2013-09-03 05:50:15 +00:00
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* The cluster clock assignment is SoC defined.
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*
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* Total 4 clock groups are possible with 3 PLLs each.
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* as per array indices, clock group A has 0, 1, 2 numbered PLLs &
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* clock group B has 3, 4, 6 and so on.
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*
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* Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
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* depends upon the SoC architeture. Same applies to other
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* clock groups and clusters.
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*
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2012-10-08 07:44:11 +00:00
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*/
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2011-08-05 21:15:24 +00:00
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for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
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2013-03-25 07:40:07 +00:00
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int cluster = fsl_qoriq_core_to_cluster(cpu);
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u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
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2012-10-08 07:44:11 +00:00
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& 0xf;
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2009-03-19 07:46:19 +00:00
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u32 cplx_pll = core_cplx_PLL[c_pll_sel];
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2013-09-03 05:50:15 +00:00
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cplx_pll += cc_group[cluster] - 1;
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2013-08-16 09:22:26 +00:00
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sys_info->freq_processor[cpu] =
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2013-09-03 05:50:15 +00:00
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freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
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2009-03-19 07:46:19 +00:00
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}
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2013-11-22 09:39:10 +00:00
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#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080)
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2013-03-25 07:33:09 +00:00
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#define FM1_CLK_SEL 0xe0000000
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#define FM1_CLK_SHIFT 29
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#else
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2012-10-08 07:44:11 +00:00
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#define PME_CLK_SEL 0xe0000000
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#define PME_CLK_SHIFT 29
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#define FM1_CLK_SEL 0x1c000000
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#define FM1_CLK_SHIFT 26
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2013-03-25 07:33:09 +00:00
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#endif
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2013-09-03 05:50:15 +00:00
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#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
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2012-10-08 07:44:11 +00:00
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rcw_tmp = in_be32(&gur->rcwsr[7]);
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2013-09-03 05:50:15 +00:00
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#endif
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2012-10-08 07:44:11 +00:00
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#ifdef CONFIG_SYS_DPAA_PME
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2013-09-03 05:50:15 +00:00
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#ifndef CONFIG_PME_PLAT_CLK_DIV
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2012-10-08 07:44:11 +00:00
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switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
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case 1:
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2013-09-03 05:50:15 +00:00
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sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
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2012-10-08 07:44:11 +00:00
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break;
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case 2:
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2013-09-03 05:50:15 +00:00
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sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
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2012-10-08 07:44:11 +00:00
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break;
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case 3:
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2013-09-03 05:50:15 +00:00
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sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
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2012-10-08 07:44:11 +00:00
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break;
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case 4:
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2013-09-03 05:50:15 +00:00
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sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
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2012-10-08 07:44:11 +00:00
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break;
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case 6:
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2013-09-03 05:50:15 +00:00
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sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
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2012-10-08 07:44:11 +00:00
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break;
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case 7:
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2013-09-03 05:50:15 +00:00
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sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
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2012-10-08 07:44:11 +00:00
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break;
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default:
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printf("Error: Unknown PME clock select!\n");
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case 0:
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2013-08-16 09:22:26 +00:00
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sys_info->freq_pme = sys_info->freq_systembus / 2;
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2012-10-08 07:44:11 +00:00
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break;
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}
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2013-09-03 05:50:15 +00:00
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#else
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sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
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#endif
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2012-10-08 07:44:11 +00:00
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#endif
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2012-10-11 07:13:39 +00:00
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#ifdef CONFIG_SYS_DPAA_QBMAN
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2013-08-16 09:22:26 +00:00
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sys_info->freq_qman = sys_info->freq_systembus / 2;
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2012-10-11 07:13:39 +00:00
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#endif
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2012-10-08 07:44:11 +00:00
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#ifdef CONFIG_SYS_DPAA_FMAN
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2013-09-03 05:50:15 +00:00
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#ifndef CONFIG_FM_PLAT_CLK_DIV
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2012-10-08 07:44:11 +00:00
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switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
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case 1:
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2013-09-03 05:50:15 +00:00
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sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
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2012-10-08 07:44:11 +00:00
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break;
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case 2:
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2013-09-03 05:50:15 +00:00
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sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
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2012-10-08 07:44:11 +00:00
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break;
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case 3:
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2013-09-03 05:50:15 +00:00
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sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
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2012-10-08 07:44:11 +00:00
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break;
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case 4:
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2013-09-03 05:50:15 +00:00
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sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
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2012-10-08 07:44:11 +00:00
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break;
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2013-03-25 07:33:09 +00:00
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case 5:
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2013-08-16 09:22:26 +00:00
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sys_info->freq_fman[0] = sys_info->freq_systembus;
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2013-03-25 07:33:09 +00:00
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break;
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2012-10-08 07:44:11 +00:00
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case 6:
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2013-09-03 05:50:15 +00:00
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sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
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2012-10-08 07:44:11 +00:00
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break;
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case 7:
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2013-09-03 05:50:15 +00:00
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sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
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2012-10-08 07:44:11 +00:00
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break;
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default:
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printf("Error: Unknown FMan1 clock select!\n");
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case 0:
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2013-08-16 09:22:26 +00:00
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sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
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2012-10-08 07:44:11 +00:00
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break;
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}
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#if (CONFIG_SYS_NUM_FMAN) == 2
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2013-09-03 05:50:15 +00:00
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#ifdef CONFIG_SYS_FM2_CLK
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2012-10-08 07:44:11 +00:00
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#define FM2_CLK_SEL 0x00000038
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#define FM2_CLK_SHIFT 3
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rcw_tmp = in_be32(&gur->rcwsr[15]);
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switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
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case 1:
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2013-09-03 05:50:15 +00:00
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sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
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2012-10-08 07:44:11 +00:00
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break;
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case 2:
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2013-09-03 05:50:15 +00:00
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sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
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2012-10-08 07:44:11 +00:00
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break;
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case 3:
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2013-09-03 05:50:15 +00:00
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sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
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2012-10-08 07:44:11 +00:00
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break;
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case 4:
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2013-09-03 05:50:15 +00:00
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sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
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2012-10-08 07:44:11 +00:00
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break;
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case 6:
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2013-09-03 05:50:15 +00:00
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|
|
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
case 7:
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
printf("Error: Unknown FMan2 clock select!\n");
|
|
|
|
|
case 0:
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
|
2012-10-08 07:44:11 +00:00
|
|
|
break;
|
|
|
|
|
}
|
2013-09-03 05:50:15 +00:00
|
|
|
#endif
|
2012-10-08 07:44:11 +00:00
|
|
|
#endif /* CONFIG_SYS_NUM_FMAN == 2 */
|
2013-09-03 05:50:15 +00:00
|
|
|
#else
|
|
|
|
|
sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
|
|
|
|
|
#endif
|
|
|
|
|
#endif
|
2009-03-19 07:46:19 +00:00
|
|
|
|
2012-10-08 07:44:11 +00:00
|
|
|
#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
|
|
|
|
|
|
|
|
|
|
for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
|
2013-03-25 07:40:07 +00:00
|
|
|
u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
|
|
|
|
|
& 0xf;
|
2012-10-08 07:44:11 +00:00
|
|
|
u32 cplx_pll = core_cplx_PLL[c_pll_sel];
|
|
|
|
|
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_processor[cpu] =
|
2013-09-03 05:50:15 +00:00
|
|
|
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
|
2012-10-08 07:44:11 +00:00
|
|
|
}
|
2009-03-19 07:46:19 +00:00
|
|
|
#define PME_CLK_SEL 0x80000000
|
|
|
|
|
#define FM1_CLK_SEL 0x40000000
|
|
|
|
|
#define FM2_CLK_SEL 0x20000000
|
2011-02-16 08:03:29 +00:00
|
|
|
#define HWA_ASYNC_DIV 0x04000000
|
|
|
|
|
#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
|
|
|
|
|
#define HWA_CC_PLL 1
|
powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-05 11:09:19 +00:00
|
|
|
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
|
|
|
|
|
#define HWA_CC_PLL 2
|
2011-02-16 08:03:29 +00:00
|
|
|
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
|
2011-05-19 20:21:41 +00:00
|
|
|
#define HWA_CC_PLL 2
|
2011-02-16 08:03:29 +00:00
|
|
|
#else
|
|
|
|
|
#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
|
|
|
|
|
#endif
|
2009-03-19 07:46:19 +00:00
|
|
|
rcw_tmp = in_be32(&gur->rcwsr[7]);
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_SYS_DPAA_PME
|
2011-02-16 08:03:29 +00:00
|
|
|
if (rcw_tmp & PME_CLK_SEL) {
|
|
|
|
|
if (rcw_tmp & HWA_ASYNC_DIV)
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
|
2011-02-16 08:03:29 +00:00
|
|
|
else
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
|
2011-02-16 08:03:29 +00:00
|
|
|
} else {
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_pme = sys_info->freq_systembus / 2;
|
2011-02-16 08:03:29 +00:00
|
|
|
}
|
2009-03-19 07:46:19 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_SYS_DPAA_FMAN
|
2011-02-16 08:03:29 +00:00
|
|
|
if (rcw_tmp & FM1_CLK_SEL) {
|
|
|
|
|
if (rcw_tmp & HWA_ASYNC_DIV)
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
|
2011-02-16 08:03:29 +00:00
|
|
|
else
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
|
2011-02-16 08:03:29 +00:00
|
|
|
} else {
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
|
2011-02-16 08:03:29 +00:00
|
|
|
}
|
2009-03-19 07:46:19 +00:00
|
|
|
#if (CONFIG_SYS_NUM_FMAN) == 2
|
2011-02-16 08:03:29 +00:00
|
|
|
if (rcw_tmp & FM2_CLK_SEL) {
|
|
|
|
|
if (rcw_tmp & HWA_ASYNC_DIV)
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
|
2011-02-16 08:03:29 +00:00
|
|
|
else
|
2013-09-03 05:50:15 +00:00
|
|
|
sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
|
2011-02-16 08:03:29 +00:00
|
|
|
} else {
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
|
2011-02-16 08:03:29 +00:00
|
|
|
}
|
2009-03-19 07:46:19 +00:00
|
|
|
#endif
|
|
|
|
|
#endif
|
|
|
|
|
|
2013-03-25 07:33:25 +00:00
|
|
|
#ifdef CONFIG_SYS_DPAA_QBMAN
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_qman = sys_info->freq_systembus / 2;
|
2013-03-25 07:33:25 +00:00
|
|
|
#endif
|
|
|
|
|
|
2012-10-08 07:44:11 +00:00
|
|
|
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
|
|
|
|
|
|
|
|
|
|
#else /* CONFIG_FSL_CORENET */
|
2013-08-16 09:22:26 +00:00
|
|
|
uint plat_ratio, e500_ratio, half_freq_systembus;
|
2009-01-15 16:58:35 +00:00
|
|
|
int i;
|
2009-05-20 16:30:29 +00:00
|
|
|
#ifdef CONFIG_QE
|
2011-02-11 07:25:30 +00:00
|
|
|
__maybe_unused u32 qe_ratio;
|
2009-05-20 16:30:29 +00:00
|
|
|
#endif
|
2003-10-15 23:53:47 +00:00
|
|
|
|
|
|
|
|
plat_ratio = (gur->porpllsr) & 0x0000003e;
|
|
|
|
|
plat_ratio >>= 1;
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
|
2007-04-23 07:37:47 +00:00
|
|
|
|
|
|
|
|
/* Divide before multiply to avoid integer
|
|
|
|
|
* overflow for processor speeds above 2GHz */
|
2013-08-16 09:22:26 +00:00
|
|
|
half_freq_systembus = sys_info->freq_systembus/2;
|
2009-07-31 06:38:14 +00:00
|
|
|
for (i = 0; i < cpu_numcores(); i++) {
|
2009-01-15 16:58:35 +00:00
|
|
|
e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
|
2009-01-15 16:58:35 +00:00
|
|
|
}
|
2008-02-09 00:05:08 +00:00
|
|
|
|
2013-08-16 09:22:26 +00:00
|
|
|
/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
|
|
|
|
|
sys_info->freq_ddrbus = sys_info->freq_systembus;
|
2007-12-07 10:59:26 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_DDR_CLK_FREQ
|
|
|
|
|
{
|
2008-09-27 06:40:57 +00:00
|
|
|
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
|
|
|
|
|
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
|
2007-12-07 10:59:26 +00:00
|
|
|
if (ddr_ratio != 0x7)
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
|
2007-12-07 10:59:26 +00:00
|
|
|
}
|
|
|
|
|
#endif
|
mpc8[56]xx: Put localbus clock in sysinfo and gd
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.
This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.
The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.
get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.
checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-03 23:16:37 +00:00
|
|
|
|
2009-05-20 16:30:29 +00:00
|
|
|
#ifdef CONFIG_QE
|
2012-08-10 11:07:26 +00:00
|
|
|
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_qe = sys_info->freq_systembus;
|
2011-02-11 07:25:30 +00:00
|
|
|
#else
|
2009-05-20 16:30:29 +00:00
|
|
|
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
|
|
|
|
|
>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
|
2009-05-20 16:30:29 +00:00
|
|
|
#endif
|
2011-02-11 07:25:30 +00:00
|
|
|
#endif
|
2009-05-20 16:30:29 +00:00
|
|
|
|
2011-01-20 22:26:31 +00:00
|
|
|
#ifdef CONFIG_SYS_DPAA_FMAN
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_fman[0] = sys_info->freq_systembus;
|
2011-01-20 22:26:31 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#endif /* CONFIG_FSL_CORENET */
|
|
|
|
|
|
2011-01-19 07:16:27 +00:00
|
|
|
#if defined(CONFIG_FSL_LBC)
|
2012-10-08 07:44:11 +00:00
|
|
|
uint lcrr_div;
|
mpc8[56]xx: Put localbus clock in sysinfo and gd
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.
This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.
The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.
get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.
checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-03 23:16:37 +00:00
|
|
|
#if defined(CONFIG_SYS_LBC_LCRR)
|
|
|
|
|
/* We will program LCRR to this value later */
|
|
|
|
|
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
|
|
|
|
|
#else
|
2010-06-17 16:37:20 +00:00
|
|
|
lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
|
mpc8[56]xx: Put localbus clock in sysinfo and gd
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.
This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.
The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.
get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.
checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-03 23:16:37 +00:00
|
|
|
#endif
|
|
|
|
|
if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
|
2009-11-17 12:49:05 +00:00
|
|
|
#if defined(CONFIG_FSL_CORENET)
|
|
|
|
|
/* If this is corenet based SoC, bit-representation
|
|
|
|
|
* for four times the clock divider values.
|
|
|
|
|
*/
|
|
|
|
|
lcrr_div *= 4;
|
|
|
|
|
#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
|
mpc8[56]xx: Put localbus clock in sysinfo and gd
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.
This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.
The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.
get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.
checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-03 23:16:37 +00:00
|
|
|
!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
|
|
|
|
|
/*
|
|
|
|
|
* Yes, the entire PQ38 family use the same
|
|
|
|
|
* bit-representation for twice the clock divider values.
|
|
|
|
|
*/
|
|
|
|
|
lcrr_div *= 2;
|
|
|
|
|
#endif
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
|
mpc8[56]xx: Put localbus clock in sysinfo and gd
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.
This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.
The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.
get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.
checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-03 23:16:37 +00:00
|
|
|
} else {
|
|
|
|
|
/* In case anyone cares what the unknown value is */
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_localbus = lcrr_div;
|
mpc8[56]xx: Put localbus clock in sysinfo and gd
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.
This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.
The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.
get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.
checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-03 23:16:37 +00:00
|
|
|
}
|
2011-01-19 07:16:27 +00:00
|
|
|
#endif
|
2012-10-08 07:44:06 +00:00
|
|
|
|
|
|
|
|
#if defined(CONFIG_FSL_IFC)
|
|
|
|
|
ccr = in_be32(&ifc_regs->ifc_ccr);
|
|
|
|
|
ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
|
|
|
|
|
|
2013-08-16 09:22:26 +00:00
|
|
|
sys_info->freq_localbus = sys_info->freq_systembus / ccr;
|
2012-10-08 07:44:06 +00:00
|
|
|
#endif
|
2003-10-15 23:53:47 +00:00
|
|
|
}
|
|
|
|
|
|
2007-04-23 07:37:47 +00:00
|
|
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2003-10-15 23:53:47 +00:00
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int get_clocks (void)
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{
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sys_info_t sys_info;
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2008-04-04 16:15:58 +00:00
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#ifdef CONFIG_MPC8544
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2008-10-16 13:01:15 +00:00
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volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
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2008-04-04 16:15:58 +00:00
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#endif
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2005-07-23 15:37:35 +00:00
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#if defined(CONFIG_CPM2)
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2008-10-16 13:01:15 +00:00
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volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
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2003-10-15 23:53:47 +00:00
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uint sccr, dfbrg;
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/* set VCO = 4 * BRG */
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2007-11-28 06:36:33 +00:00
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cpm->im_cpm_intctl.sccr &= 0xfffffffc;
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sccr = cpm->im_cpm_intctl.sccr;
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2003-10-15 23:53:47 +00:00
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dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
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#endif
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get_sys_info (&sys_info);
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2013-08-16 09:22:26 +00:00
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gd->cpu_clk = sys_info.freq_processor[0];
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gd->bus_clk = sys_info.freq_systembus;
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gd->mem_clk = sys_info.freq_ddrbus;
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gd->arch.lbc_clk = sys_info.freq_localbus;
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2008-04-04 16:15:58 +00:00
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2009-05-20 16:30:29 +00:00
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#ifdef CONFIG_QE
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2013-08-16 09:22:26 +00:00
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gd->arch.qe_clk = sys_info.freq_qe;
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2012-12-13 20:48:50 +00:00
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gd->arch.brg_clk = gd->arch.qe_clk / 2;
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2009-05-20 16:30:29 +00:00
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#endif
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2008-04-04 16:15:58 +00:00
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/*
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* The base clock for I2C depends on the actual SOC. Unfortunately,
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* there is no pattern that can be used to determine the frequency, so
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* the only choice is to look up the actual SOC number and use the value
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* for that SOC. This information is taken from application note
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* AN2919.
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*/
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#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
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2013-09-06 02:45:40 +00:00
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defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
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defined(CONFIG_P1022)
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2013-08-16 09:22:26 +00:00
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gd->arch.i2c1_clk = sys_info.freq_systembus;
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2008-04-04 16:15:58 +00:00
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#elif defined(CONFIG_MPC8544)
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/*
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* On the 8544, the I2C clock is the same as the SEC clock. This can be
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* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
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* 4.4.3.3 of the 8544 RM. Note that this might actually work for all
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* 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
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* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
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*/
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if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
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2013-08-16 09:22:26 +00:00
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gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
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2008-10-17 02:58:49 +00:00
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else
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2013-08-16 09:22:26 +00:00
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gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
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2008-04-04 16:15:58 +00:00
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#else
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/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
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2013-08-16 09:22:26 +00:00
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gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
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2008-04-04 16:15:58 +00:00
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#endif
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2012-12-13 20:48:49 +00:00
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gd->arch.i2c2_clk = gd->arch.i2c1_clk;
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2008-01-09 20:35:26 +00:00
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2009-09-01 11:57:00 +00:00
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#if defined(CONFIG_FSL_ESDHC)
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2011-02-08 10:15:25 +00:00
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#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
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defined(CONFIG_P1014)
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2012-12-13 20:49:05 +00:00
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gd->arch.sdhc_clk = gd->bus_clk;
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2009-10-15 13:47:06 +00:00
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#else
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2012-12-13 20:49:05 +00:00
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gd->arch.sdhc_clk = gd->bus_clk / 2;
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2008-08-12 16:14:19 +00:00
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#endif
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2009-10-15 13:47:06 +00:00
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#endif /* defined(CONFIG_FSL_ESDHC) */
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2008-08-12 16:14:19 +00:00
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2005-07-23 15:37:35 +00:00
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#if defined(CONFIG_CPM2)
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2013-08-16 09:22:26 +00:00
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gd->arch.vco_out = 2*sys_info.freq_systembus;
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2012-12-13 20:48:46 +00:00
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gd->arch.cpm_clk = gd->arch.vco_out / 2;
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gd->arch.scc_clk = gd->arch.vco_out / 4;
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gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
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2003-10-15 23:53:47 +00:00
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#endif
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if(gd->cpu_clk != 0) return (0);
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else return (1);
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}
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/********************************************
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* get_bus_freq
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* return system bus freq in Hz
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*********************************************/
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ulong get_bus_freq (ulong dummy)
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{
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2008-02-09 00:05:08 +00:00
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return gd->bus_clk;
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2003-10-15 23:53:47 +00:00
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}
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2007-12-07 10:59:26 +00:00
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/********************************************
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* get_ddr_freq
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* return ddr bus freq in Hz
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*********************************************/
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ulong get_ddr_freq (ulong dummy)
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{
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2008-02-09 00:05:08 +00:00
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return gd->mem_clk;
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2007-12-07 10:59:26 +00:00
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}
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