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u-boot/arch/arm/cpu/armv7/ls102xa/Kconfig

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Convert CONFIG_SYS_FSL_ERRATUM_A010315 to Kconfig option Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2016-09-26 15:09:27 +00:00
config ARCH_LS1021A
arm: Fix Kconfig for proper display menu Some config options should not have prompt. They are selected by choosing target. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-04 21:31:47 +00:00
bool
Convert CONFIG_FSL_DEVICE_DISABLE to Kconfig This converts the following to Kconfig: CONFIG_FSL_DEVICE_DISABLE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-11-19 23:45:10 +00:00
select FSL_DEVICE_DISABLE
Convert CONFIG_FSL_IFC to Kconfig This converts the following to Kconfig: CONFIG_FSL_IFC This is done via select statements to match previous logic. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-11 19:55:49 +00:00
select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
arm: ls102xa: Migrate LS102XA_STREAM_ID This symbol appears to be globally used in the architecture, select it. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-11-19 23:45:25 +00:00
select LS102XA_STREAM_ID
Kconfig: Sort bool, default, select and imply options Another round of sorting Kconfig entries aplhabetically. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-23 13:55:15 +00:00
select SYS_FSL_DDR_BE if SYS_FSL_DDR
select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
Convert CONFIG_SYS_FSL_CCSR_GUR_BE et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_FSL_CCSR_GUR_BE CONFIG_SYS_FSL_CCSR_SCFG_BE CONFIG_SYS_FSL_ESDHC_BE CONFIG_SYS_FSL_IFC_BE CONFIG_SYS_FSL_PEX_LUT_BE CONFIG_SYS_FSL_CCSR_GUR_LE CONFIG_SYS_FSL_CCSR_SCFG_LE CONFIG_SYS_FSL_ESDHC_LE CONFIG_SYS_FSL_IFC_LE CONFIG_SYS_FSL_PEX_LUT_LE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-23 17:05:09 +00:00
select SYS_FSL_IFC_BE
arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig Use Kconfig to select errata workaround. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:41 +00:00
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008407
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-02-25 16:19:53 +00:00
select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR
arm: ls102xa: select USB PHY erratum's only if USB is enabled The USB support is not by default enabled on all designs, so it does not make seance to have USB specific erratum's enabled on such a designs. On our internal Hitachi-Powergrids design not using the USB controller there is a crash when accessing those specific memory locations selected by the erratum flags. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-11-26 10:52:41 +00:00
select SYS_FSL_ERRATUM_A008997 if USB
select SYS_FSL_ERRATUM_A009008 if USB
arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig Use Kconfig to select errata workaround. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:41 +00:00
select SYS_FSL_ERRATUM_A009663
arm: ls102xa: select USB PHY erratum's only if USB is enabled The USB support is not by default enabled on all designs, so it does not make seance to have USB specific erratum's enabled on such a designs. On our internal Hitachi-Powergrids design not using the USB controller there is a crash when accessing those specific memory locations selected by the erratum flags. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-11-26 10:52:41 +00:00
select SYS_FSL_ERRATUM_A009798 if USB
arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig Use Kconfig to select errata workaround. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:41 +00:00
select SYS_FSL_ERRATUM_A009942
Convert CONFIG_SYS_FSL_ERRATUM_A010315 to Kconfig option Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2016-09-26 15:09:27 +00:00
select SYS_FSL_ERRATUM_A010315
Convert CONFIG_SYS_FSL_CCSR_GUR_BE et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_FSL_CCSR_GUR_BE CONFIG_SYS_FSL_CCSR_SCFG_BE CONFIG_SYS_FSL_ESDHC_BE CONFIG_SYS_FSL_IFC_BE CONFIG_SYS_FSL_PEX_LUT_BE CONFIG_SYS_FSL_CCSR_GUR_LE CONFIG_SYS_FSL_CCSR_SCFG_LE CONFIG_SYS_FSL_ESDHC_LE CONFIG_SYS_FSL_IFC_LE CONFIG_SYS_FSL_PEX_LUT_LE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-23 17:05:09 +00:00
select SYS_FSL_ESDHC_BE
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-11 05:39:14 +00:00
select SYS_FSL_HAS_CCI400
fsl_ddr: Move DDR config options to driver Kconfig Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-28 16:43:40 +00:00
select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC and ARM SoCs, move it to Kconfig under the driver. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:30 +00:00
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to Kconfig Use Kconfig option to set little- or big-endian access to secure boot and trust architecture. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:31 +00:00
select SYS_FSL_SEC_LE
Kconfig: Sort bool, default, select and imply options Another round of sorting Kconfig entries aplhabetically. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-23 13:55:15 +00:00
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
Convert CONFIG_SYS_I2C_MXC et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_I2C_MXC CONFIG_SYS_I2C_MXC_I2C1 CONFIG_SYS_I2C_MXC_I2C2 CONFIG_SYS_I2C_MXC_I2C3 CONFIG_SYS_I2C_MXC_I2C4 Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-19 03:12:33 +00:00
select SYS_I2C_MXC
Kconfig: Sort bool, default, select and imply options Another round of sorting Kconfig entries aplhabetically. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-23 13:55:15 +00:00
imply CMD_PCI
Convert CONFIG_SCSI to Kconfig This converts the following to Kconfig: CONFIG_SCSI Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-06-15 03:28:21 +00:00
imply SCSI
ata: Migrate CONFIG_SCSI_AHCI to Kconfig And use 'imply' liberally. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-12-08 13:36:19 +00:00
imply SCSI_AHCI
armv7: ls1021a: Convert CONFIG_LS1_DEEP_SLEEP to Kconfig option Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-26 15:09:29 +00:00
arm: Move FSL_LSCH2 FSL_LSCH3 to Kconfig Move these options to Kconfig and create a sub-menu to avoid name conflict with other architectures. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-04 21:31:48 +00:00
menu "LS102xA architecture"
depends on ARCH_LS1021A
Convert CONFIG_FSL_DEVICE_DISABLE to Kconfig This converts the following to Kconfig: CONFIG_FSL_DEVICE_DISABLE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-11-19 23:45:10 +00:00
config FSL_DEVICE_DISABLE
bool
armv7: ls1021a: Convert CONFIG_LS1_DEEP_SLEEP to Kconfig option Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-26 15:09:29 +00:00
config LS1_DEEP_SLEEP
arm: Fix Kconfig for proper display menu Some config options should not have prompt. They are selected by choosing target. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-04 21:31:47 +00:00
bool "Deep sleep"
arm: Move FSL_LSCH2 FSL_LSCH3 to Kconfig Move these options to Kconfig and create a sub-menu to avoid name conflict with other architectures. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-04 21:31:48 +00:00
arm: ls102xa: Migrate LS102XA_STREAM_ID This symbol appears to be globally used in the architecture, select it. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-11-19 23:45:25 +00:00
config LS102XA_STREAM_ID
bool
arm: Move MAX_CPUS to Kconfig Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This option is used by Freescale Layerscape SoCs. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-04 21:45:01 +00:00
config MAX_CPUS
int "Maximum number of CPUs permitted for LS102xA"
default 2
help
Set this number to the maximum number of possible CPUs in the SoC.
SoCs may have multiple clusters with each cluster may have multiple
ports. If some ports are reserved but higher ports are used for
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
Convert CONFIG_PEN_ADDR_BIG_ENDIAN to Kconfig This converts the following to Kconfig: CONFIG_PEN_ADDR_BIG_ENDIAN Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-02 21:42:40 +00:00
config PEN_ADDR_BIG_ENDIAN
bool
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-11 05:39:14 +00:00
config SYS_CCI400_OFFSET
hex "Offset for CCI400 base"
depends on SYS_FSL_HAS_CCI400
default 0x180000
help
Offset for CCI400 base.
CCI400 base addr = CCSRBAR + CCI400_OFFSET
armv7: ls102xa: Add workaround for DDR erratum A-008850 Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-06 06:49:14 +00:00
config SYS_FSL_ERRATUM_A008850
bool
help
Workaround for DDR erratum A008850
armv7: Add workaround for USB erratum A-008997 Low Frequency Periodic Singaling (LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-04 10:46:54 +00:00
config SYS_FSL_ERRATUM_A008997
bool
help
Workaround for USB PHY erratum A008997
armv7: Add workaround for USB erratum A-009007 Rx Compliance tests may fail intermittently at high jitter frequencies using default register values Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-04 10:46:55 +00:00
config SYS_FSL_ERRATUM_A009007
bool
help
Workaround for USB PHY erratum A009007
armv7: Add workaround for USB erratum A-009008 USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-04 10:46:52 +00:00
config SYS_FSL_ERRATUM_A009008
bool
help
Workaround for USB PHY erratum A009008
armv7: Add workaround for USB erratum A-009798 The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receive Compliance test failure for a 100mV threshold. Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-04 10:46:53 +00:00
config SYS_FSL_ERRATUM_A009798
bool
help
Workaround for USB PHY erratum A009798
arm: Move FSL_LSCH2 FSL_LSCH3 to Kconfig Move these options to Kconfig and create a sub-menu to avoid name conflict with other architectures. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-04 21:31:48 +00:00
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
fsl-layerscape: Consolidate registers space defination for CCI-400 bus CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-11 05:39:14 +00:00
config SYS_FSL_HAS_CCI400
bool
arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig Use Kconfig to select errata workaround. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:41 +00:00
config SYS_FSL_ERRATUM_A008407
bool
armv7: ls102xa: make QSPI clock selection optional during SoC init To improve startup times when booting from QSPI flash, the QSPI frequency can be configured very early in the boot process [1] to reduce loading times of U-Boot itself. This patch adds an option to disable setting the frequency to a default value during SoC initialization. [1] https://www.nxp.com/docs/en/application-note/AN12279.pdf Signed-off-by: Mario Kicherer <dev@kicherer.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-02-01 06:16:22 +00:00
config SYS_FSL_QSPI_SKIP_CLKSEL
bool "Skip setting QSPI clock during SoC init"
default 0
help
To improve startup times when booting from QSPI flash, the QSPI
frequency can be set very early in the boot process. If this option
is enabled, the QSPI frequency will not be changed by U-Boot during
SoC initialization.
arm: Move FSL_LSCH2 FSL_LSCH3 to Kconfig Move these options to Kconfig and create a sub-menu to avoid name conflict with other architectures. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-04 21:31:48 +00:00
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