2016-09-26 15:09:27 +00:00
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config ARCH_LS1021A
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2016-10-04 21:31:47 +00:00
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bool
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2016-12-28 16:43:41 +00:00
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select SYS_FSL_ERRATUM_A008378
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select SYS_FSL_ERRATUM_A008407
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select SYS_FSL_ERRATUM_A009663
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select SYS_FSL_ERRATUM_A009942
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2016-09-26 15:09:27 +00:00
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select SYS_FSL_ERRATUM_A010315
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2017-08-11 05:39:14 +00:00
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select SYS_FSL_HAS_CCI400
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2016-10-05 01:01:34 +00:00
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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2016-12-28 16:43:40 +00:00
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select SYS_FSL_DDR_BE if SYS_FSL_DDR
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select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
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select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
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select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
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2016-12-28 16:43:30 +00:00
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_COMPAT_5
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2016-12-28 16:43:31 +00:00
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select SYS_FSL_SEC_LE
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2017-06-15 03:28:21 +00:00
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imply SCSI
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2017-08-04 22:34:34 +00:00
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imply CMD_PCI
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2016-09-26 15:09:29 +00:00
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2016-10-04 21:31:48 +00:00
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menu "LS102xA architecture"
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depends on ARCH_LS1021A
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2016-12-13 06:54:24 +00:00
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config FSL_PCIE_COMPAT
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string "PCIe compatible of Kernel DT"
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depends on PCIE_LAYERSCAPE
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default "fsl,ls1021a-pcie" if ARCH_LS1021A
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help
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This compatible is used to find pci controller node in Kernel DT
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to complete fixup.
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2016-09-26 15:09:29 +00:00
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config LS1_DEEP_SLEEP
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2016-10-04 21:31:47 +00:00
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bool "Deep sleep"
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depends on ARCH_LS1021A
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2016-10-04 21:31:48 +00:00
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2016-10-04 21:45:01 +00:00
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config MAX_CPUS
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int "Maximum number of CPUs permitted for LS102xA"
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depends on ARCH_LS1021A
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default 2
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help
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Set this number to the maximum number of possible CPUs in the SoC.
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SoCs may have multiple clusters with each cluster may have multiple
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ports. If some ports are reserved but higher ports are used for
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cores, count the reserved ports. This will allocate enough memory
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in spin table to properly handle all cores.
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2016-12-02 17:31:43 +00:00
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config SECURE_BOOT
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bool "Secure Boot"
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help
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Enable Freescale Secure Boot feature. Normally selected
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by defconfig. If unsure, do not change.
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2017-08-11 05:39:14 +00:00
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config SYS_CCI400_OFFSET
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hex "Offset for CCI400 base"
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depends on SYS_FSL_HAS_CCI400
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default 0x180000
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help
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Offset for CCI400 base.
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CCI400 base addr = CCSRBAR + CCI400_OFFSET
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2016-10-04 21:31:48 +00:00
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config SYS_FSL_ERRATUM_A010315
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bool "Workaround for PCIe erratum A010315"
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2017-08-11 05:39:14 +00:00
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config SYS_FSL_HAS_CCI400
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bool
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2016-10-05 01:01:34 +00:00
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config SYS_FSL_SRDS_1
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bool
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config SYS_FSL_SRDS_2
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bool
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config SYS_HAS_SERDES
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bool
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2016-10-04 21:45:54 +00:00
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config SYS_FSL_IFC_BANK_COUNT
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int "Maximum banks of Integrated flash controller"
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depends on ARCH_LS1021A
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default 8
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2016-12-28 16:43:41 +00:00
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config SYS_FSL_ERRATUM_A008407
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bool
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2016-10-04 21:31:48 +00:00
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endmenu
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