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https://github.com/AsahiLinux/u-boot
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ba89878d70
To improve startup times when booting from QSPI flash, the QSPI frequency can be configured very early in the boot process [1] to reduce loading times of U-Boot itself. This patch adds an option to disable setting the frequency to a default value during SoC initialization. [1] https://www.nxp.com/docs/en/application-note/AN12279.pdf Signed-off-by: Mario Kicherer <dev@kicherer.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
108 lines
2.5 KiB
Text
108 lines
2.5 KiB
Text
config ARCH_LS1021A
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bool
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select FSL_DEVICE_DISABLE
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select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
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select LS102XA_STREAM_ID
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select SYS_FSL_DDR_BE if SYS_FSL_DDR
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select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
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select SYS_FSL_IFC_BE
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select SYS_FSL_ERRATUM_A008378
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select SYS_FSL_ERRATUM_A008407
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select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR
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select SYS_FSL_ERRATUM_A008997 if USB
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select SYS_FSL_ERRATUM_A009008 if USB
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select SYS_FSL_ERRATUM_A009663
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select SYS_FSL_ERRATUM_A009798 if USB
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select SYS_FSL_ERRATUM_A009942
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select SYS_FSL_ERRATUM_A010315
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select SYS_FSL_ESDHC_BE
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select SYS_FSL_HAS_CCI400
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select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
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select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_COMPAT_5
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select SYS_FSL_SEC_LE
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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select SYS_I2C_MXC
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imply CMD_PCI
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imply SCSI
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imply SCSI_AHCI
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menu "LS102xA architecture"
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depends on ARCH_LS1021A
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config FSL_DEVICE_DISABLE
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bool
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config LS1_DEEP_SLEEP
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bool "Deep sleep"
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config LS102XA_STREAM_ID
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bool
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config MAX_CPUS
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int "Maximum number of CPUs permitted for LS102xA"
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default 2
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help
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Set this number to the maximum number of possible CPUs in the SoC.
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SoCs may have multiple clusters with each cluster may have multiple
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ports. If some ports are reserved but higher ports are used for
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cores, count the reserved ports. This will allocate enough memory
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in spin table to properly handle all cores.
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config PEN_ADDR_BIG_ENDIAN
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bool
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config SYS_CCI400_OFFSET
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hex "Offset for CCI400 base"
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depends on SYS_FSL_HAS_CCI400
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default 0x180000
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help
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Offset for CCI400 base.
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CCI400 base addr = CCSRBAR + CCI400_OFFSET
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config SYS_FSL_ERRATUM_A008850
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bool
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help
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Workaround for DDR erratum A008850
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config SYS_FSL_ERRATUM_A008997
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bool
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help
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Workaround for USB PHY erratum A008997
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config SYS_FSL_ERRATUM_A009007
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bool
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help
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Workaround for USB PHY erratum A009007
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config SYS_FSL_ERRATUM_A009008
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bool
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help
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Workaround for USB PHY erratum A009008
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config SYS_FSL_ERRATUM_A009798
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bool
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help
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Workaround for USB PHY erratum A009798
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config SYS_FSL_ERRATUM_A010315
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bool "Workaround for PCIe erratum A010315"
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config SYS_FSL_HAS_CCI400
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bool
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config SYS_FSL_ERRATUM_A008407
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bool
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config SYS_FSL_QSPI_SKIP_CLKSEL
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bool "Skip setting QSPI clock during SoC init"
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default 0
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help
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To improve startup times when booting from QSPI flash, the QSPI
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frequency can be set very early in the boot process. If this option
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is enabled, the QSPI frequency will not be changed by U-Boot during
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SoC initialization.
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endmenu
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