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54 commits

Author SHA1 Message Date
Asahi Lina
d6d72b6398 hv_exc: Pass through TLBI OS instructions 
Gues VM TLBI OS instructions don't work. Trap them and pass them through
as the host.

Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-10-17 22:14:21 +09:00
Asahi Lina
4274c9d74a hv: Log memory attribute & sharability info in mmiotrace 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-10-17 22:14:21 +09:00
Janne Grunau
0f0ddf3397 hv_exc: Add s3_7_c15_c3_1 sysreg passthroughs for t8112/macos 12.4 
Boot panics due to what appears a timeout without ignoring this sys_reg
in m1n1.

Signed-off-by: Janne Grunau <j@jannau.net>
 2022-08-30 22:30:22 +09:00
Asahi Lina
b6d2cc127c hv_exc: Add support for resetting stolen time delta 
This is useful to re-sync AGX, since it shares the same timebase as the
CPU.

Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-08-17 14:01:49 +09:00
Akihiko Odaki
bcbe26d79b m1n1.hv: Always continue on the stepped thread 
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
 2022-06-04 20:20:21 +09:00
Hector Martin
8eeb7966aa hv: Refactor CPU switch logic, make hv.cpu() not exit shell 
Get rid of the hv_rearm() thing (which was always a bit dodgy) and
instead properly make sure that all CPUs rendezvous when needed and
switch the active proxy thread without ever exiting exception context.

The Python side can now switch proxy context (by waiting directly for
a proxy boot) without having to exit out of the hypervisor callback,
so cpu() now works as a normal Python method.

Add a cpus() iterator so you can do things like:

>>> for i in cpus(): bt()

Signed-off-by: Hector Martin <marcan@marcan.st>
 2022-05-30 22:33:44 +09:00
Hector Martin
01a1a0f597 hv: Make time stealing run-time configurable 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2022-05-30 19:37:23 +09:00
Hector Martin
52bb64b86c hv_exc: Do not forget to arm tick in fast path 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2022-04-20 00:38:22 +09:00
Hector Martin
e750dfcca1 hv_exc: Improve multi-core scalability 
The HV tick polling now only runs on CPU#0. All CPUs have the 1000Hz
HV tick, but secondaries only use it to poll the FIQ state and that path
does not take the BHL if no other FIQ was pending.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2022-04-20 00:20:58 +09:00
Hector Martin
33d09cc7c0 hv_exc: Filter out CYC_OVRD_DISABLE_WFI_RET 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-11-16 17:26:39 +09:00
Hector Martin
84acf60c24 Fix warnings when building/linking with clang/llvm 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-11-08 13:53:04 +09:00
Hector Martin
f5af1caee5 hv_exc: Forward more sysregs 
We don't normally trap these, but for experiments using TIDCP they are
useful to avoid.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-11-04 03:55:09 +09:00
Hector Martin
0005b6533b hv_exc: Add more sysreg passthroughs for t600x spam 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-11-04 03:52:43 +09:00
Hector Martin
5787eb2d64 hv_exc: Fix global IPIs 
Reported-by: Joey Gouly <joey.gouly@arm.com>

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-10-18 13:26:28 +09:00
Hector Martin
5eed8f674d hv_vm: Fix guest SError handling 
This was broken, but somewhat masked by another bug in hv_vm.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 22:17:52 +09:00
Hector Martin
56c3d93787 hv_exc: Enable SErrors in the hypervisor 
This finally works properly now

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 21:18:13 +09:00
Hector Martin
78cf104b1f hv_vm: Guard emulated read/writes to catch SErrors/aborts 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 21:18:13 +09:00
Hector Martin
25bc815821 hv: Store exception info regs on entry, and use it 
This is the second part of allowing nested exceptions

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 21:18:13 +09:00
Hector Martin
bce239b36f exception: Make space in the stack for full exception context 
This is step 1 of the rework to make reentrant exceptions work

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 20:29:19 +09:00
Hector Martin
a16731e8b3 hv_exc: Avoid delivering spurious HV-triggered IPIs to the guest 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 17:13:03 +09:00
Hector Martin
0e3770ca47 hv, m1n1.hv: Add cpu() command to switch CPU contexts 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 13:18:06 +09:00
Hector Martin
977cbdf4f8 hv_exc: New time accounting around Python callbacks 
This does an explicit hypervisor rendezvous. It's not great because it
introduces spurious guest IPIs, but xnu doesn't seem to care...

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-21 13:17:00 +09:00
Hector Martin
c3ba77ce16 hv_exc: Handle SYS_IMP_APL_CYC_OVRD in the fast path 
m1n1 now uses this for SMP, and due to wfi FIQ leakage from the HV
timer this gets spammed thousands of times per second. Handle it in
the HV directly.

Fixes: #107

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-18 22:33:28 +09:00
Hector Martin
09a44e5a92 hv_exc: Disable stolen time accounting 
This doesn't work with SMP.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-15 23:32:57 +09:00
Hector Martin
184a516367 hv_exc: Make IPI/IRQ/timer/PMC emulation storage per-CPU 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-15 23:26:14 +09:00
Hector Martin
56b54a6641 hv_vm/hv_exc: Add cpu_id to exception & mmiotrace structs 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-15 23:24:37 +09:00
Hector Martin
787c46e8c7 hv_exc: Add a Big Hypervisor Lock 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-09-15 23:24:37 +09:00
Hector Martin
f8110dd409 hv_exc: Handle M1RACLES mitigation here due to 12.0 spam 
macOS 12.0 added a silly ineffective "mitigation" that clears the
register on every context switch. This doesn't actually mitigate
anything, but it does make this sysreg trap performance-critical,
so we have to move its handling into the C side.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-08-14 16:30:18 +09:00
Sven Peter
e0d889fac1 hv: add proper single stepping support 
Signed-off-by: Sven Peter <sven@svenpeter.dev>
 2021-07-09 15:52:40 +09:00
Janne Grunau
4b5c016368 hv: disable PMU counters inside the hypervisor 
Signed-off-by: Janne Grunau <j@jannau.net>
 2021-06-09 19:47:20 +09:00
Janne Grunau
d61bf13cb0 hv: shadow perf monitor IRQ mode and state 
The development Mac OS kernel panics if the PMCR0 sysreg is in an
unexpected state. To avoid that the hypervisor needs to shadow the
interrupt mode and interrupt active flag after it mask the PM FIQ.
Mac OS reads and writes frequently from PMCR0 and PMC 0/1 so handling
in m1n1 is preferred over Python.

Signed-off-by: Janne Grunau <j@jannau.net>
 2021-06-09 19:47:20 +09:00
Hector Martin
393089f076 hv_exc: Also pass through (E)HID4, since it's noisy 
This seems to be poked every time the kernel does a specific kind of
dcache flush...

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-30 03:37:12 +09:00
Hector Martin
f1cfe27e31 hv: Use AFSR_GL1 when in guarded mode. 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-30 03:34:17 +09:00
Hector Martin
775902112d hv.py: Add M1RACLES mitigation 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-28 02:41:17 +09:00
Hector Martin
12a7a0f1bb hv_exc: Allow the guest to see a bit of stolen time 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-28 02:13:23 +09:00
Hector Martin
fe2e89573e hv: Move break handling to hv_tick(), properly poll 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-28 02:13:23 +09:00
Hector Martin
db0252a1d6 hv_exc: Steal time from the guest during HV exceptions 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-28 00:38:42 +09:00
Hector Martin
dd443d2c2c cpu_regs: Fix missing IMP_APL prefixes 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-28 00:38:11 +09:00
Hector Martin
0265edebba hv_exc: Add ACTLR_EL1 sysreg forwarding 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-28 00:37:48 +09:00
Hector Martin
bfe8c94c47 hv_wdt: Add hypervisor watchdog on secondary core 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-27 21:28:43 +09:00
Hector Martin
a5a974791b hv: Support handling GL2 exceptions 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-27 21:28:43 +09:00
Hector Martin
81808da562 hv_exc: Set the step timer to 100 cycles 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-25 20:12:20 +09:00
Hector Martin
e92e075fba hv_exc: Add IPI and guest timer FIQ virtualization 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-25 20:12:20 +09:00
Hector Martin
75f206e65c hv_exc, hv.py: Add support for interrupting guest with ^C 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-25 20:12:20 +09:00
Hector Martin
2e014f58fa hv: Implement a periodic hypervisor ptimer and use vtimer for stepping 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-25 20:12:20 +09:00
Hector Martin
1b1653dfe9 hv_vm: Simplify r31 handling, move LR adjustment to hv_exc.c 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-25 20:12:20 +09:00
Hector Martin
afc088840d hv: Add Python-side MMIO emulation hooks 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-15 23:57:48 +09:00
Hector Martin
ed32cf6328 hv_exc: Add a hacky STEP feature to interrupt guest after a while 
This should eventually be a proper single step feature or something, but
for now...

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-09 03:25:51 +09:00
Hector Martin
9407dba2e0 hv_vm: Initial data abort handling 
Supports software-mapping for a subset of ldr/str instructions.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-05 04:03:44 +09:00
Hector Martin
8a64441bcd hv_vm: Extend hv_translate() for stage1 and write modes 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-05 03:27:19 +09:00