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hv_exc: Pass through TLBI OS instructions

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Gues VM TLBI OS instructions don't work. Trap them and pass them through
as the host.

Signed-off-by: Asahi Lina <lina@asahilina.net>
This commit is contained in:
Asahi Lina 2022-10-15 21:26:30 +09:00 committed by Hector Martin
parent d8c2d68ebf
commit d6d72b6398
2 changed files with 7 additions and 3 deletions
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4
proxyclient/m1n1/hv/__init__.py
View file

@ -111,7 +111,6 @@ class HV(Reloadable):
self.hvcall_handlers = {}
self.switching_context = False
self.show_timestamps = False
self.trace_tlbos = False
def _reloadme(self):
super()._reloadme()
@ -1313,8 +1312,7 @@ class HV(Reloadable):
hcr.TVM = 0
hcr.FMO = 1
hcr.IMO = 0
if self.trace_tlbos:
hcr.TTLBOS = 1
hcr.TTLBOS = 1
self.u.msr(HCR_EL2, hcr.value)
# Trap dangerous things

6
src/hv_exc.c
View file

@ -254,6 +254,12 @@ static bool hv_handle_msr(struct exc_info *ctx, u64 iss)
SYSREG_PASS(SYS_IMP_APL_PMC8)
SYSREG_PASS(SYS_IMP_APL_PMC9)
/* Outer Sharable TLB maintenance instructions */
SYSREG_PASS(sys_reg(1, 0, 8, 1, 0)) // TLBI VMALLE1OS
SYSREG_PASS(sys_reg(1, 0, 8, 1, 1)) // TLBI VAE1OS
SYSREG_PASS(sys_reg(1, 0, 8, 1, 2)) // TLBI ASIDE1OS
SYSREG_PASS(sys_reg(1, 0, 8, 5, 1)) // TLBI RVAE1OS
/*
* Handle this one here because m1n1/Linux (will) use it for explicit cpuidle.
* We can pass it through; going into deep sleep doesn't break the HV since we