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u-boot/arch/riscv/cpu
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Tom Rini ac897385bb Merge branch 'next' 
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-02 10:55:44 -04:00
..
andesv5 riscv: Rename Andes cpu and board names 2023-02-17 19:07:48 +08:00
fu540 common: return type board_get_usable_ram_top 2023-08-15 18:21:17 +02:00
fu740 common: return type board_get_usable_ram_top 2023-08-15 18:21:17 +02:00
generic common: return type board_get_usable_ram_top 2023-08-15 18:21:17 +02:00
jh7110 riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT 2023-09-05 10:53:46 +08:00
cpu.c riscv: Correct event usage for riscv_cpu_probe/setup 2023-09-06 13:47:24 -04:00
Makefile riscv: Move trap handler codes to mtrap.S 2018-12-18 09:56:27 +08:00
mtrap.S riscv: Add option to print registers on exception 2020-02-10 14:51:08 +08:00
start.S riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation 2023-08-10 10:58:12 +08:00
u-boot-spl.lds riscv: Update alignment for some sections in linker scripts 2023-04-20 20:45:08 +08:00
u-boot.lds riscv: Fix alignment of RELA sections in the linker scripts 2023-06-27 10:09:51 +08:00