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For 2 GB LPDDR4 single-rank RAM with 16 rows, the Rockchip ddr init bin prints: "Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB" U-Boot TPL prints: "BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB" Add missing high row detection so that U-Boot TPL prints Row=16, same as the Rockchip ddr init bin: "BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB" Signed-off-by: Jonathan Liu <net147@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
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.. | ||
aspeed | ||
k3-ddrss | ||
mediatek | ||
octeon | ||
rockchip | ||
sifive | ||
stm32mp1 | ||
bmips_ram.c | ||
imxrt_sdram.c | ||
k3-am654-ddrss.c | ||
k3-am654-ddrss.h | ||
Kconfig | ||
Makefile | ||
mpc83xx_sdram.c | ||
ram-uclass.c | ||
sandbox_ram.c | ||
stm32_sdram.c |