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426230a65f
For DDR4, command/address delay in mode registers and parity latency in timing config register are only needed for UDIMMs, but not RDIMMs. Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Fix calculation of timing config registers. Use hexadecimal format for printing RCW (register control word) registers. Signed-off-by: York Sun <york.sun@nxp.com> |
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.. | ||
arm_ddr_gen3.c | ||
ctrl_regs.c | ||
ddr1_dimm_params.c | ||
ddr2_dimm_params.c | ||
ddr3_dimm_params.c | ||
ddr4_dimm_params.c | ||
fsl_ddr_gen4.c | ||
fsl_mmdc.c | ||
interactive.c | ||
Kconfig | ||
lc_common_dimm_params.c | ||
main.c | ||
Makefile | ||
mpc85xx_ddr_gen1.c | ||
mpc85xx_ddr_gen2.c | ||
mpc85xx_ddr_gen3.c | ||
mpc86xx_ddr.c | ||
options.c | ||
util.c |