York Sun 426230a65f drivers/ddr/fsl: Fix DDR4 RDIMM support ... For DDR4, command/address delay in mode registers and parity latency in timing config register are only needed for UDIMMs, but not RDIMMs. Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Fix calculation of timing config registers. Use hexadecimal format for printing RCW (register control word) registers. Signed-off-by: York Sun <york.sun@nxp.com>		2018-01-30 09:14:06 -08:00
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altera	ddr: altera: silence PHY calibration unless in debug mode	2018-01-25 09:59:37 +01:00
fsl	drivers/ddr/fsl: Fix DDR4 RDIMM support	2018-01-30 09:14:06 -08:00
marvell	ddr: marvell: update ddr controller init and freq	2018-01-19 16:30:29 +01:00
microchip	wait_bit: use wait_for_bit_le32 and remove wait_for_bit	2018-01-24 12:03:43 +05:30
Kconfig	arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig	2017-04-14 14:06:57 +02:00