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067a4c001d
Update DDR configuration with the latest update: - PUBL_regs: DXnGCR[0]= according to ddr_width to disable Byte lane 2/3 in 16bit - fix LPDDR2/3 timing_calc to step RL/WL in relaxed timings mode - remove LPDDR3 RL3 (optional) support vs MR0[7] because MR0[7] can't be read instead always apply worse RL/WL for LPDDR3 when freq < 166MHz) - change MR3 to 48ohm drive for LPDDR2/3 - change default ZPROG[7:4] = 0x1 for LPDDR2/3 , '0' is not allowed even when ODT not used - use DQSTRN for LPDDR2/3 (it was not set in PIR) - LPDDR3: set dqsge/dwsgx gate extension to 2,2 like LPDDR2 -DDRCTRL.dfitmg0: + for LPDDR3 tphy_wrlat = WL (as LPDDR2) + improvement for relaxed mode vs RL/Wl at corner case. For example @533MHz RL/WL (relaxed) = 9/5 for LPDDR2/3 and correction to MR2 accordingly - DDR_PCFGQOS1_1: port1 timeout relaxed from 0x00 to 0x40, for LTDC. - DDR_PCFGWQOS0_0: change vpr level from 11 to 12 in order to include the CPU on the variable priority queue. - DDR_SCHED: fix to consider 13 levels (13 levels - 1 = 0xC) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
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.. | ||
cpu | ||
dts | ||
include | ||
lib | ||
mach-aspeed | ||
mach-at91 | ||
mach-bcm283x | ||
mach-bcmstb | ||
mach-davinci | ||
mach-exynos | ||
mach-highbank | ||
mach-imx | ||
mach-integrator | ||
mach-k3 | ||
mach-keystone | ||
mach-kirkwood | ||
mach-mediatek | ||
mach-meson | ||
mach-mvebu | ||
mach-omap2 | ||
mach-orion5x | ||
mach-owl | ||
mach-qemu | ||
mach-rmobile | ||
mach-rockchip | ||
mach-s5pc1xx | ||
mach-snapdragon | ||
mach-socfpga | ||
mach-sti | ||
mach-stm32 | ||
mach-stm32mp | ||
mach-sunxi | ||
mach-tegra | ||
mach-uniphier | ||
mach-versal | ||
mach-versatile | ||
mach-zynq | ||
mach-zynqmp | ||
mach-zynqmp-r5 | ||
thumb1/include/asm/proc-armv | ||
config.mk | ||
Kconfig | ||
Kconfig.debug | ||
Makefile |