This helps in a multiple bus master environment which
is why I also added a wait for bus idle.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
imx_reset is only referenced once so
move to that location.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
imx_start is only referenced once so
move to that location.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
wait_for_sr_state returns i2sr on success
so no need to read again.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Not using udelay gives a more accurate timeout. The current implementation of udelay
in imx-common does not seem to wait at all for a udelay(1).
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
----
V2: Added WATCHDOG_RESET as suggested by Marek Vasut
add error message when stop fails
mxc_i2c: code i2c_probe as a 0 length i2c_write
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Initial code of i2c_read and i2c_write
is identical, move to subroutine.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Let's clear the sr register before waiting for
bit to be set, instead of clearing it after
hardware sets it. No real operational difference here,
but allows combining of i2c_imx_trx_complete and
i2c_imx_bus_busy in later patches.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Use tx_byte function instead of having 3 copies
of the code.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
This is always selected when CONFIG_I2C_MXC is
selected, so it adds no value.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Instead of clearing 2 bits, all the other
bits were set because '|=' was used instead
of '&='.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Other then being very weird, this code was also wrong.
For example, say I set speed to 100K. I'll read back the speed
as 85937. But the speed is really 85937.5, so we I reset
the speed to 85937, I'll get 73660.7. After a couple of transactions
my speed is now exactly 68750 so it will remain there.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
The following platforms had their config files changed
flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd
and mx53loco.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
The problem was caused by a global variable being used early in the boot
process.
The symptoms were on imx31_phycore board, reading the environment from I2C
EEPROM didn't work correctly and causes default environment to be loaded.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Rewrite the mxc_i2c driver.
* This version is much closer to Linux implementation.
* Fixes IPG_PERCLK being incorrectly used as clock source
* Fixes behaviour of the driver on iMX51
* Clean up coding style a bit ;-)
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Jason Hui <jason.hui@linaro.org>
Acked-by: Jason Liu <jason.hui@linro.org>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Jason Liu <jason.hui@linro.org>
As exception among the i.MX processors, the i.MX31 has headers
without general names (mx31-regs.h, mx31.h instead of imx-regs.h and
clock.h). This requires several nasty #ifdef in the drivers to
include the correct header. The patch cleans up the driver and
renames the header files as for the other i.MX processors.
Signed-off-by: Stefano Babic <sbabic@denx.de>
There is sporadic failures when more as one I2C slave
is on the bus and the processor tries to communicate
with more as one slave.
The problem was seen on a mx35pdk (two I2C slaves,
PMIC controller and CAN/RTC chip).
The current driver uses the IIF bit in the status register
to check if the bus is busy or not. According to the manual,
this is not correct, because the IIB bit should be checked.
Not only, to check if a transfer is finished must be checked
the ICF bit, and this is not tested at all.
This patch comes from analyse with a corresponding driver
provided by Freescale as part of the LTIB tool. Comparing
the two drivers, it appears that the current u-boot driver checks
the wrong bits, and depending on race condition, the transfer
can be successful or not.
The patch gets rid also of own debug function (DPRINTF),
replaced with the general debug().
Tested on Freescale mx35pdk.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
This driver accesses to processor's register
via __REG macros, that are removed (or are planned
to be removed) and replaced by C structures.
This patches replaces all occurrencies of __REG macros.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
i.MX31 powers on with most clocks running, so, after a power on this explicit
clock start up is not required. However, as Linux boots it disables most clocks
to save power. This includes the I2C clock. If we then soft reboot from Linux
the I2C clock stays off. This breaks the phycore, which has its environment in
I2C EEPROM. Fix the problem by explicitly starting the clock in I2C driver
initialisation routine.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Ack-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
