mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 06:00:43 +00:00
Removes all board specific code from the arch. part for DM644x (DaVinci) boards
Signed-off-by: Pieter Voorthuijsen <pv@prodrive.nl>
This commit is contained in:
Pieter Voorthuijsen
Peter Pearse
parent
1704dc2091
commit
1377b5583a
6 changed files with 130 additions and 73 deletions
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@ -3,6 +3,11 @@
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Copyright (C) 2008 Prodrive BV <pv@prodrive.nl>
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* Changed:
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* Made board specific defines such as DDR timing and PLL
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* dividers. These should be set in the board config file
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*
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* Partially based on TI sources, original copyrights follow:
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*/
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@ -156,17 +161,17 @@ WaitPPL2Loop:
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/* Program the PLL Multiplier */
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ldr r6, PLL2_PLLM
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mov r2, $0x17 /* 162 MHz */
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mov r2, $CFG_DAVINCI_PLL2_PLLM
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str r2, [r6]
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/* Program the PLL2 Divisor Value */
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ldr r6, PLL2_DIV2
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mov r3, $0x01
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mov r3, $CFG_DAVINCI_PLL2_DIV2
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str r3, [r6]
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/* Program the PLL2 Divisor Value */
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ldr r6, PLL2_DIV1
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mov r4, $0x0b /* 54 MHz */
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mov r4, $CFG_DAVINCI_PLL2_DIV1
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str r4, [r6]
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/* PLL2 DIV2 MMR */
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@ -273,7 +278,7 @@ checkDDRStatClkStop:
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bne checkDDRStatClkStop
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/*------------------------------------------------------*
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* Program DDR2 MMRs for 162MHz Setting *
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* Program DDR2 MMRs *
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*------------------------------------------------------*/
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/* Program PHY Control Register */
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@ -288,12 +293,12 @@ checkDDRStatClkStop:
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/* Program SDRAM TIM-0 Config Register */
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ldr r6, SDTIM0
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ldr r7, SDTIM0_VAL_162MHz
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ldr r7, SDTIM0_VAL
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str r7, [r6]
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/* Program SDRAM TIM-1 Config Register */
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ldr r6, SDTIM1
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ldr r7, SDTIM1_VAL_162MHz
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ldr r7, SDTIM1_VAL
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str r7, [r6]
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/* Program the SDRAM Bank Config Control Register */
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@ -435,7 +440,7 @@ WaitLoop:
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/* Program the PLL Multiplier */
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ldr r6, PLL1_PLLM
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mov r3, $0x15 /* For 594MHz */
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mov r3, $CFG_DAVINCI_PLL1_PLLM
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str r3, [r6]
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/* Wait for PLL to Reset Properly */
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@ -467,7 +472,7 @@ PLL1Lock:
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nop
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/*------------------------------------------------------*
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* AEMIF configuration for NOR Flash (double check) *
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* AEMIF configuration for NAND/NOR Flash *
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*------------------------------------------------------*/
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ldr r0, _PINMUX0
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ldr r1, _DEV_SETTING
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@ -479,6 +484,12 @@ PLL1Lock:
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orr r2, r2, r1
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str r2, [r0]
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ldr r0, ACFG2
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ldr r1, ACFG2_VAL
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ldr r2, [r0]
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and r1, r2, r1
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str r1, [r0]
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ldr r0, ACFG3
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ldr r1, ACFG3_VAL
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ldr r2, [r0]
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@ -497,6 +508,12 @@ PLL1Lock:
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and r1, r2, r1
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str r1, [r0]
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ldr r0, NANDFCR
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ldr r1, NANDFCR_VAL
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ldr r2, [r0]
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and r1, r2, r1
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str r1, [r0]
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/*--------------------------------------*
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* VTP manual Calibration *
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*--------------------------------------*/
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@ -560,24 +577,36 @@ _PINMUX1:
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.word 0x01c40004 /* Device Configuration Registers */
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_DEV_SETTING:
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.word 0x00000c1f
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.word CFG_DAVINCI_PINMUX_0
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WAITCFG:
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.word 0x01e00004
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WAITCFG_VAL:
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.word 0
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.word CFG_DAVINCI_WAITCFG
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ACFG2:
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.word 0x01e00010
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ACFG2_VAL:
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.word CFG_DAVINCI_ACFG2
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ACFG3:
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.word 0x01e00014
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ACFG3_VAL:
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.word 0x3ffffffd
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.word CFG_DAVINCI_ACFG3
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ACFG4:
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.word 0x01e00018
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ACFG4_VAL:
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.word 0x3ffffffd
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.word CFG_DAVINCI_ACFG4
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ACFG5:
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.word 0x01e0001c
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ACFG5_VAL:
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.word 0x3ffffffd
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.word CFG_DAVINCI_ACFG5
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NANDFCR:
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.word 0x01e00060
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NANDFCR_VAL:
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#ifdef CFG_DAVINCI_NANDCE
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.word (1 << (CFG_DAVINCI_NANDCE - 2))
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#else
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.word 0x00000000
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#endif
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MDCTL_DDR2:
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.word 0x01c41a34
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@ -599,33 +628,27 @@ PSC_FLAG_CLEAR:
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PSC_GEM_FLAG_CLEAR:
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.word 0xfffffeff
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/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
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/* DDR2 MMR & CONFIGURATION VALUES */
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DDRCTL:
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.word 0x200000e4
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DDRCTL_VAL:
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.word 0x50006405
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.word CFG_DAVINCI_DDRCTL
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SDREF:
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.word 0x2000000c
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SDREF_VAL:
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.word 0x000005c3
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.word CFG_DAVINCI_SDREF
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SDCFG:
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.word 0x20000008
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SDCFG_VAL:
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#ifdef DDR_4BANKS
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.word 0x00178622
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#elif defined DDR_8BANKS
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.word 0x00178632
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#else
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#error "Unknown DDR configuration!!!"
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#endif
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.word CFG_DAVINCI_SDCFG
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SDTIM0:
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.word 0x20000010
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SDTIM0_VAL_162MHz:
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.word 0x28923211
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SDTIM0_VAL:
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.word CFG_DAVINCI_SDTIM0
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SDTIM1:
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.word 0x20000014
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SDTIM1_VAL_162MHz:
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.word 0x0016c722
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SDTIM1_VAL:
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.word CFG_DAVINCI_SDTIM1
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VTPIOCR:
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.word 0x200000f0 /* VTP IO Control register */
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DDRVTPR:
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@ -699,7 +722,7 @@ PLL2_DIV_MASK:
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MMARG_BRF0:
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.word 0x01c42010 /* BRF margin mode 0 (R/W)*/
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MMARG_BRF0_VAL:
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.word 0x00444400
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.word CFG_DAVINCI_MMARG_BRF0
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DDR2_START_ADDR:
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.word 0x80000000
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@ -117,7 +117,7 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
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dummy = emif_addr->NANDF3ECC;
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dummy = emif_addr->NANDF4ECC;
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emif_addr->NANDFCR |= (1 << 8);
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emif_addr->NANDFCR |= (1 << (CFG_DAVINCI_NANDCE + 6));
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}
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static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
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@ -147,7 +147,7 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u
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n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1;
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region = 1;
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region = (CFG_DAVINCI_NANDCE - 1);
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while (n--) {
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tmp = nand_davinci_readecc(mtd, region);
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*ecc_code++ = tmp;
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@ -311,40 +311,9 @@ static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this, i
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static void nand_flash_init(void)
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{
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u_int32_t acfg1 = 0x3ffffffc;
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u_int32_t acfg2 = 0x3ffffffc;
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u_int32_t acfg3 = 0x3ffffffc;
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u_int32_t acfg4 = 0x3ffffffc;
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emifregs emif_regs;
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/*------------------------------------------------------------------*
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* NAND FLASH CHIP TIMEOUT @ 459 MHz *
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* *
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* AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
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* AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
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* *
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*------------------------------------------------------------------*/
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acfg1 = 0
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| (0 << 31 ) /* selectStrobe */
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| (0 << 30 ) /* extWait */
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| (1 << 26 ) /* writeSetup 10 ns */
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| (3 << 20 ) /* writeStrobe 40 ns */
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| (1 << 17 ) /* writeHold 10 ns */
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| (1 << 13 ) /* readSetup 10 ns */
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| (5 << 7 ) /* readStrobe 60 ns */
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| (1 << 4 ) /* readHold 10 ns */
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| (3 << 2 ) /* turnAround ?? ns */
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| (0 << 0 ) /* asyncSize 8-bit bus */
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;
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emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
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emif_regs->AWCCR |= 0x10000000;
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emif_regs->AB1CR = acfg1; /* 0x08244128 */;
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emif_regs->AB2CR = acfg2;
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emif_regs->AB3CR = acfg3;
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emif_regs->AB4CR = acfg4;
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emif_regs->NANDFCR = 0x00000101;
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/* All EMIF initialization is done in lowlevel_init.S
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* and config values are in the board config files
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*/
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}
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int board_nand_init(struct nand_chip *nand)
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@ -150,6 +150,8 @@ typedef volatile unsigned int * dv_reg_p;
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#define VDD3P3V_PWDN (0x01c40048)
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#define UART0_PWREMU_MGMT (0x01c20030)
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#define UART1_PWREMU_MGMT (0x01c20430)
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#define UART2_PWREMU_MGMT (0x01c20830)
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#define PSC_SILVER_BULLET (0x01c41a20)
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@ -52,6 +52,9 @@
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#define DV_EVM
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#define CFG_NAND_SMALLPAGE
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#define CFG_USE_NOR
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#define CFG_USE_INTEL_NOR /* Define this when your DVEVM has Intel
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* flash instead of AMD flash
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*/
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/*===================*/
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/* SoC Configuration */
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/*===================*/
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@ -60,6 +63,24 @@
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#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
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#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
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#define CFG_HZ 1000
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#define CFG_DAVINCI_PINMUX_0 0x00000c1f
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#define CFG_DAVINCI_WAITCFG 0x00000000
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#define CFG_DAVINCI_ACFG2 0x3ffffffd /* CE configs */
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#define CFG_DAVINCI_ACFG3 0x3ffffffd
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#define CFG_DAVINCI_ACFG4 0x3ffffffd
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#define CFG_DAVINCI_ACFG5 0x3ffffffd
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#undef CFG_DAVINCI_NANDCE /* When using NAND, define 2,3 or 4 */
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#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
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#define CFG_DAVINCI_SDREF 0x000005c3
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#define CFG_DAVINCI_SDCFG 0x00178632 /* 8 banks */
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#define CFG_DAVINCI_SDTIM0 0x28923211
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#define CFG_DAVINCI_SDTIM1 0x0016c722
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#define CFG_DAVINCI_MMARG_BRF0 0x00444400
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/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
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#define CFG_DAVINCI_PLL1_PLLM 0x15
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#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
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#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
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#define CFG_DAVINCI_PLL2_DIV2 0x01
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/*====================================================*/
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/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
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/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
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@ -114,7 +135,7 @@
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#ifdef CFG_USE_NAND
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#undef CFG_ENV_IS_IN_FLASH
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#define CFG_NO_FLASH
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#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
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#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
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#ifdef CFG_NAND_SMALLPAGE
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#define CFG_ENV_SECT_SIZE 512 /* Env sector Size */
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#define CFG_ENV_SIZE SZ_16K
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@ -139,24 +160,31 @@
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#undef CONFIG_SKIP_RELOCATE_UBOOT
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#endif
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#define CFG_ENV_IS_IN_FLASH
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#undef CFG_NO_FLASH
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#undef CFG_NO_FLASH
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#define CFG_FLASH_CFI_DRIVER
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#define CFG_FLASH_CFI
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#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
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#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
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#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*3)
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#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
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#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
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#define CFG_ENV_OFFSET (CFG_ENV_ADDR)
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
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#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
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#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
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#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
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#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
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#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
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#ifdef CFG_USE_INTEL_NOR
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#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size INTEL Flash */
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#define CFG_FLASH_PROTECTION 1
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#else
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#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
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#endif
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#endif
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/*==============================*/
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/* U-Boot general configuration */
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/*==============================*/
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#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
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#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
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#define CONFIG_MISC_INIT_R
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#undef CONFIG_BOOTDELAY
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#undef CONFIG_BOOTDELAY
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#define CONFIG_BOOTFILE "uImage" /* Boot file name */
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#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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@ -35,6 +35,24 @@
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#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
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#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
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#define CFG_HZ 1000
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#define CFG_DAVINCI_PINMUX_0 0x00000c1f
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#define CFG_DAVINCI_WAITCFG 0x00000000
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#define CFG_DAVINCI_ACFG2 0x0432229c /* CE configs */
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#define CFG_DAVINCI_ACFG3 0x3ffffffd
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#define CFG_DAVINCI_ACFG4 0x3ffffffd
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#define CFG_DAVINCI_ACFG5 0x3ffffffd
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#define CFG_DAVINCI_NANDCE 2 /* When using NAND, define 2,3 or 4 */
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#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
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#define CFG_DAVINCI_SDREF 0x000005c3
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#define CFG_DAVINCI_SDCFG 0x00178622 /* 4 banks */
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#define CFG_DAVINCI_SDTIM0 0x28923211
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#define CFG_DAVINCI_SDTIM1 0x0016c722
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#define CFG_DAVINCI_MMARG_BRF0 0x00444400
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/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
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#define CFG_DAVINCI_PLL1_PLLM 0x15
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#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
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#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
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#define CFG_DAVINCI_PLL2_DIV2 0x01
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/*=============*/
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/* Memory Info */
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/*=============*/
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@ -46,7 +64,6 @@
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#define CONFIG_STACKSIZE (256*1024) /* regular stack */
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#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
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#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
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#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
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/*====================*/
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/* Serial Driver info */
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/*====================*/
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@ -60,6 +60,24 @@
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#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
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#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
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#define CFG_HZ 1000
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#define CFG_DAVINCI_PINMUX_0 0x00000c1f
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#define CFG_DAVINCI_WAITCFG 0x00000000
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#define CFG_DAVINCI_ACFG2 0x3ffffffd /* CE configs */
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#define CFG_DAVINCI_ACFG3 0x3ffffffd
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#define CFG_DAVINCI_ACFG4 0x3ffffffd
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#define CFG_DAVINCI_ACFG5 0x3ffffffd
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#undef CFG_DAVINCI_NANDCE /* When using NAND, define 2,3 or 4 */
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#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
|
||||
#define CFG_DAVINCI_SDREF 0x000005c3
|
||||
#define CFG_DAVINCI_SDCFG 0x00178632 /* 8 banks */
|
||||
#define CFG_DAVINCI_SDTIM0 0x28923211
|
||||
#define CFG_DAVINCI_SDTIM1 0x0016c722
|
||||
#define CFG_DAVINCI_MMARG_BRF0 0x00444400
|
||||
/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
|
||||
#define CFG_DAVINCI_PLL1_PLLM 0x15
|
||||
#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
|
||||
#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
|
||||
#define CFG_DAVINCI_PLL2_DIV2 0x01
|
||||
/*====================================================*/
|
||||
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
|
||||
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
|
||||
|
|
|
|||
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Reference in a new issue