mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-21 07:01:57 +00:00
Adds support for the Prodrive PMDRA board, based on a DM6441
Signed-off-by: Pieter Voorthuijsen <pv@prodrive.nl>
This commit is contained in:
Pieter Voorthuijsen
Peter Pearse
parent
1377b5583a
commit
a574a73852
7 changed files with 548 additions and 0 deletions
3
Makefile
3
Makefile
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@ -2377,6 +2377,9 @@ davinci_schmoogie_config : unconfig
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davinci_sonata_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci
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pmdra_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm926ejs pmdra prodrive davinci
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omap1610inn_config \
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omap1610inn_cs0boot_config \
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omap1610inn_cs3boot_config \
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50
board/prodrive/pmdra/Makefile
Normal file
50
board/prodrive/pmdra/Makefile
Normal file
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@ -0,0 +1,50 @@
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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||||
# along with this program; if not, write to the Free Software
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||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := pmdra.o
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SOBJS := board_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak *~ .depend
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#########################################################################
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# This is for $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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29
board/prodrive/pmdra/board_init.S
Normal file
29
board/prodrive/pmdra/board_init.S
Normal file
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@ -0,0 +1,29 @@
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/*
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* Copyright (C) 2008 Prodrive B.V.
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*
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* Board-specific low level initialization code. Called at the very end
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* of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
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* initialization required.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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.globl dv_board_init
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dv_board_init:
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mov pc, lr
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39
board/prodrive/pmdra/config.mk
Normal file
39
board/prodrive/pmdra/config.mk
Normal file
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@ -0,0 +1,39 @@
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#
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# (C) Copyright 2002
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# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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#
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# (C) Copyright 2003
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# Texas Instruments, <www.ti.com>
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# Swaminathan <swami.iyer@ti.com>
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#
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# Davinci EVM board (ARM925EJS) cpu
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# see http://www.ti.com/ for more information on Texas Instruments
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#
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# Davinci EVM has 1 bank of 256 MB DDR RAM
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# Physical Address:
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# 8000'0000 to 9000'0000
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#
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# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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#
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# Visioneering Corp. Sonata board (ARM926EJS) cpu
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#
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# Sonata board has 1 bank of 128 MB DDR RAM
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# Physical Address:
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# 8000'0000 to 8800'0000
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#
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# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
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#
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# Schmoogie board has 1 bank of 128 MB DDR RAM
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# Physical Address:
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# 8000'0000 to 8800'0000
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#
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# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
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# (mem base + reserved)
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#
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# we load ourself to 8108 '0000
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#
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#
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#Provide at least 16MB spacing between us and the Linux Kernel image
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TEXT_BASE = 0x81080000
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189
board/prodrive/pmdra/pmdra.c
Normal file
189
board/prodrive/pmdra/pmdra.c
Normal file
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@ -0,0 +1,189 @@
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/*
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* Copyright (C) 2008 Prodrive BV <pv@prodrive.nl>
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Parts are shamelessly stolen from various TI sources, original copyright
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* follows:
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* ---------------------------------------------------------------------------
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*
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* Copyright (C) 2004 Texas Instruments.
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*
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* ---------------------------------------------------------------------------
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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||||
* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ---------------------------------------------------------------------------
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/emac_defs.h>
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#define MACH_TYPE_DAVINCI_EVM 901
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DECLARE_GLOBAL_DATA_PTR;
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extern void timer_init(void);
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extern int eth_hw_init(void);
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extern phy_t phy;
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/* Works on Always On power domain only (no PD argument) */
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void lpsc_on(unsigned int id)
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{
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dv_reg_p mdstat, mdctl;
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if (id >= DAVINCI_LPSC_GEM)
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return; /* Don't work on DSP Power Domain */
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mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
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mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
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while (REG(PSC_PTSTAT) & 0x01) {; }
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if ((*mdstat & 0x1f) == 0x03)
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return; /* Already on and enabled */
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*mdctl |= 0x03;
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/* Special treatment for some modules as for sprue14 p.7.4.2 */
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if ((id == DAVINCI_LPSC_VPSSSLV) ||
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(id == DAVINCI_LPSC_EMAC) ||
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(id == DAVINCI_LPSC_EMAC_WRAPPER) ||
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(id == DAVINCI_LPSC_MDIO) ||
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(id == DAVINCI_LPSC_USB) ||
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(id == DAVINCI_LPSC_ATA) ||
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(id == DAVINCI_LPSC_VLYNQ) ||
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(id == DAVINCI_LPSC_UHPI) ||
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(id == DAVINCI_LPSC_DDR_EMIF) ||
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(id == DAVINCI_LPSC_AEMIF) ||
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(id == DAVINCI_LPSC_MMC_SD) ||
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(id == DAVINCI_LPSC_MEMSTICK) ||
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(id == DAVINCI_LPSC_McBSP) ||
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(id == DAVINCI_LPSC_GPIO))
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*mdctl |= 0x200;
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REG(PSC_PTCMD) = 0x01;
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while (REG(PSC_PTSTAT) & 0x03) {; }
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while ((*mdstat & 0x1f) != 0x03) {; } /* Probably an overkill... */
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}
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void dsp_on(void)
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{
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int i;
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if (REG(PSC_PDSTAT1) & 0x1f)
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return; /* Already on */
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REG(PSC_GBLCTL) |= 0x01;
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REG(PSC_PDCTL1) |= 0x01;
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REG(PSC_PDCTL1) &= ~0x100;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
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REG(PSC_PTCMD) = 0x02;
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for (i = 0; i < 100; i++) {
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if (REG(PSC_EPCPR) & 0x02)
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break;
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}
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REG(PSC_CHP_SHRTSW) = 0x01;
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REG(PSC_PDCTL1) |= 0x100;
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REG(PSC_EPCCR) = 0x02;
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for (i = 0; i < 100; i++) {
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if (!(REG(PSC_PTSTAT) & 0x02))
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break;
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}
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REG(PSC_GBLCTL) &= ~0x1f;
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}
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int board_init(void)
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{
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/* arch number of the board */
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gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
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/* address of boot parameters */
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
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/* Workaround for TMS320DM6446 errata 1.3.22 */
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REG(PSC_SILVER_BULLET) = 0;
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/* Power on required peripherals */
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lpsc_on(DAVINCI_LPSC_EMAC);
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lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
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lpsc_on(DAVINCI_LPSC_MDIO);
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lpsc_on(DAVINCI_LPSC_I2C);
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lpsc_on(DAVINCI_LPSC_UART0);
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lpsc_on(DAVINCI_LPSC_UART2);
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lpsc_on(DAVINCI_LPSC_TIMER1);
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lpsc_on(DAVINCI_LPSC_GPIO);
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/* Powerup the DSP */
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dsp_on();
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/* Bringup UART0 and 2 out of reset */
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REG(UART0_PWREMU_MGMT) = 0x00006001;
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REG(UART2_PWREMU_MGMT) = 0x00006001;
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/* Enable GIO3.3V cells used for EMAC */
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REG(VDD3P3V_PWDN) = 0;
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/* Enable UART0 and 2 MUX lines */
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REG(PINMUX1) |= 1;
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REG(PINMUX1) |= 4;
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/* Enable EMAC and AEMIF pins */
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REG(PINMUX0) = 0x80000c1f;
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/* Enable I2C pin Mux */
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REG(PINMUX1) |= (1 << 7);
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/* Set the Bus Priority Register to appropriate value */
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REG(VBPR) = 0x20;
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timer_init();
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return(0);
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}
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int misc_init_r(void)
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{
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int clk = 0;
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clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
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printf("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27)/2);
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printf("DDR Clock : %dMHz\n", (clk / 2));
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if (!eth_hw_init())
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printf("ethernet init failed!\n");
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else
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printf("ETH PHY : %s\n", phy.name);
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return(0);
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}
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int dram_init(void)
|
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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|
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return(0);
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}
|
||||
52
board/prodrive/pmdra/u-boot.lds
Normal file
52
board/prodrive/pmdra/u-boot.lds
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/arm926ejs/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
||||
186
include/configs/pmdra.h
Normal file
186
include/configs/pmdra.h
Normal file
|
|
@ -0,0 +1,186 @@
|
|||
/*
|
||||
* Copyright (C) 2008 Prodrive BV <pieter.voorthijsen@prodrive.nl>
|
||||
*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
#include <asm/sizes.h>
|
||||
|
||||
/*=======*/
|
||||
/* Board */
|
||||
/*=======*/
|
||||
#define CFG_PMDRA
|
||||
#define CFG_NAND_LARGEPAGE
|
||||
/*===================*/
|
||||
/* SoC Configuration */
|
||||
/*===================*/
|
||||
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
|
||||
#define CONFIG_SYS_CLK_FREQ ((CFG_HZ_CLOCK * (CFG_DAVINCI_PLL1_PLLM + 1))/2)
|
||||
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
|
||||
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
|
||||
#define CFG_HZ 1000
|
||||
#define CFG_DAVINCI_PINMUX_0 0x00000c1f
|
||||
#define CFG_DAVINCI_WAITCFG 0x10000000
|
||||
#define CFG_DAVINCI_ACFG2 0x00460385 /* NOR CE Config */
|
||||
#define CFG_DAVINCI_ACFG3 0x0822218c /* NAND CE Config */
|
||||
#define CFG_DAVINCI_ACFG4 0x3ffffffd
|
||||
#define CFG_DAVINCI_ACFG5 0x3ffffffd
|
||||
#define CFG_DAVINCI_NANDCE 3 /* Use CE3 for NAND */
|
||||
#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
|
||||
#define CFG_DAVINCI_SDREF 0x000005c3
|
||||
#define CFG_DAVINCI_SDCFG 0x00178832 /* 8 banks , CAS = 4*/
|
||||
#define CFG_DAVINCI_SDTIM0 0x28923211
|
||||
#define CFG_DAVINCI_SDTIM1 0x0016c722
|
||||
#define CFG_DAVINCI_MMARG_BRF0 0x00444400
|
||||
/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
|
||||
#define CFG_DAVINCI_PLL1_PLLM 0x12
|
||||
#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
|
||||
#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
|
||||
#define CFG_DAVINCI_PLL2_DIV2 0x01
|
||||
/*====================================================*/
|
||||
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
|
||||
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
|
||||
/*====================================================*/
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 6
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
|
||||
/*=============*/
|
||||
/* Memory Info */
|
||||
/*=============*/
|
||||
#define CFG_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
|
||||
#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */
|
||||
#define CFG_MEMTEST_START 0x80000000 /* memtest start address */
|
||||
#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define CONFIG_STACKSIZE (256*1024) /* regular stack */
|
||||
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
|
||||
#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */
|
||||
#define DDR_8BANKS /* 8-bank DDR2 (256MB) */
|
||||
/*====================*/
|
||||
/* Serial Driver info */
|
||||
/*====================*/
|
||||
#define CFG_NS16550
|
||||
#define CFG_NS16550_SERIAL
|
||||
#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */
|
||||
#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */
|
||||
#define CFG_NS16550_COM2 0x01c20800 /* Base address of UART2 */
|
||||
#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */
|
||||
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
|
||||
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
/*===================*/
|
||||
/* I2C Configuration */
|
||||
/*===================*/
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_DRIVER_DAVINCI_I2C
|
||||
#define CFG_I2C_SPEED 50000 /* 100Kbps won't work, silicon bug */
|
||||
#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
|
||||
/*==================================*/
|
||||
/* Network & Ethernet Configuration */
|
||||
/*==================================*/
|
||||
#define CONFIG_DRIVER_TI_EMAC
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_BOOTP_DEFAULT
|
||||
#define CONFIG_BOOTP_DNS
|
||||
#define CONFIG_BOOTP_DNS2
|
||||
#define CONFIG_BOOTP_SEND_HOSTNAME
|
||||
#define CONFIG_NET_RETRY_COUNT 10
|
||||
/*=====================*/
|
||||
/* Flash & Environment */
|
||||
/*=====================*/
|
||||
#define CFG_USE_NAND
|
||||
#define CFG_NAND_BASE 0x04000000
|
||||
#undef CFG_NAND_HW_ECC
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define DEF_BOOTM ""
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_FLASH_CFI_DRIVER
|
||||
#define CFG_FLASH_CFI
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
|
||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
|
||||
#define CFG_ENV_OFFSET (CFG_ENV_ADDR)
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster)*/
|
||||
#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
|
||||
#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
|
||||
#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
|
||||
#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
|
||||
#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
|
||||
#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size INTEL Flash */
|
||||
#define CFG_FLASH_PROTECTION 1
|
||||
/*==============================*/
|
||||
/* U-Boot general configuration */
|
||||
/*==============================*/
|
||||
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
|
||||
#define CONFIG_MISC_INIT_R
|
||||
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
|
||||
#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
|
||||
#define CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CFG_LONGHELP
|
||||
#define CONFIG_CRC32_VERIFY
|
||||
#define CONFIG_MX_CYCLIC
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
/*===================*/
|
||||
/* Linux Information */
|
||||
/*===================*/
|
||||
#define LINUX_BOOT_PARAM_ADDR 0x80000100
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_BOOTDELAY 2
|
||||
#define CONFIG_BOOTARGS \
|
||||
"mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
|
||||
#define CONFIG_BOOTCOMMAND "run nand"
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS "ethaddr=00:11:22:33:44:55\n"
|
||||
/*=================*/
|
||||
/* U-Boot commands */
|
||||
/*=================*/
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SAVES
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#undef CONFIG_CMD_BDI
|
||||
#undef CONFIG_CMD_FPGA
|
||||
#undef CONFIG_CMD_SETGETDCR
|
||||
#define CONFIG_CMD_FLASH
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#define CONFIG_CMD_NAND
|
||||
/*=======================*/
|
||||
/* KGDB support (if any) */
|
||||
/*=======================*/
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
|
||||
#endif
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in a new issue