Fix a bug that failed to read/write eeprom on ls1021atsn
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Fixes: commit 8ec619f8fd ("pci: layerscape: Fixup PCIe EP
mode DT nodes for LX2160A rev2")
This added the PCIe EP nodes fixup of LX2160A, but it
didn't update the condition value when there isn't a
property 'apio-wins'.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Fixed checkpatch error]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Enable support to compile OPTEE driver, access AVB TA
and RPMB API's access via RPC from OPTEE for lx2162
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.
LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module,
microSD card, eMMC support, serial console, qspi nor flash, qsgmii,
sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes
interface to support three PCIe gen3 interface.
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
[Fixed whitespace errors]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Move CORTINA_NO_FW_UPLOAD to Kconfig file so that it can
be controlled via defconfig files.
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
resource "config" is required to have minimum 4KB space
to access all config space of PCI Express EP.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
resource "config" is required to have minimum 8KB space
as per hardware documentation.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add label to pcie nodes in dts so that these nodes
are easy to refer.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
- Update ARM STI and ARM STM STM32MP Arch maintainers emails
- Enable internal pull-ups for SDMMC1 on DHCOM SoM
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Merge tag 'u-boot-stm32-20201209' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board
- Update ARM STI and ARM STM STM32MP Arch maintainers emails
- Enable internal pull-ups for SDMMC1 on DHCOM SoM
Add USB OTG ID pin mux and switch the USB OTG port
from peripheral to OTG mode.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
The DH DRC02 board has an on-board microSD slot,
add DT properties to enable the slot.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
The STM32MP1 DHCOM SoM can be built with either bus voltage level shifter
or without one on the SDMMC1 interface. Because the SDMMC1 interface is
limited to 50 MHz and hence SD high-speed anyway, disable the SD feedback
clock to permit operation of the same U-Boot image on both SoM with and
without voltage level shifter.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
The default state of SD bus and clock line is logical HI. SD card IO is
open-drain and pulls the bus lines LO. Always enable the SD bus pull ups
to guarantee this behavior on DHCOM SoM. Note that on SoMs with SD bus
voltage level shifter, the pull ups are built into the level shifter,
however that has no negative impact.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Update Patrick and my email address with the one dedicated to
upstream activities.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Update Patrick and my email address with the one dedicated to
upstream activities.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Check whether user has explicitly defined device and partition where
environment file will be located before using 'auto' i.e. bootable
partition
Voids the need to set such partition as bootable to work with the
'dev:auto' tuple
Signed-off-by: Manuel Reis <mluis.reis@gmail.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Tested-by: Michael Opdenacker <michael.opdenacker@bootlin.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
- Espressobin: Simplify DT handling of board variants (Pali)
- Add Luka Perkov to maintainers of Puzzle-M801 (Luka)
- Armada 38x: Enable board specific USB2 high-speed impedance
threshold configuration (Joshua)
Use the full name of firmware self extracting file to make it run.
Also, don't use sudo when not needed.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Try to initialize emmc in board_late_init() and if it fails then we know
that emmc device is not connected.
This allows to use in U-Boot just one DTS file for all Espressobin variants
and also to correctly set fdtfile env variable for Linux kernel.
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Gérald Kerma <gerald@gk2.net>
Reviewed-by: Andre Heider <a.heider@gmail.com>
To simplify setup, configuration and compilation of u-boot, define emmc
node for all Espressobin boards. Espressobin boards without populated emmc
works correctly, just detection and initialization of emmc obviously fails.
Code for emmc is extracted from commit f1a43c84a9 ("arm64: dts: a3720:
add support for espressobin with populated emmc").
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Gérald Kerma <gerald@gk2.net>
Hardware testing of a board using the Armada 385 has shown that an
impedance threshold setting of 0x7 performs better in an eye-diagram
test than with Marvell's recommended value 0x6.
As other boards may still perform better with Marvell's reccomended value,
a configuration option is added with a default value of 0x6.
Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz>
Reviewed-by: Stefan Roese <sr@denx.de>
Add Luka Perkov to Puzzle-M801 BOARD MAINTAINERS.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Add implementation of board_mem_get_layout for overriding the memory
layout.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Introduce weak function board_mem_get_layout() which allows overriding
the memory layout from board code in runtime, useful for handling
different SKU versions.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
This documents the u-boot build and deployment procedure.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
This commit adds initial support for the Toradex Apalis iMX8X 2GB WB
IT V1.1A System on Module support [1].
Boot log:
U-Boot 2020.10-02940-g894aebb7e8-dirty (Oct 22 2020 - 09:43:57 +0300)
CPU: NXP i.MX8QXP RevB A35 at 1200 MHz at 30C
DRAM: 2 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... OK
In: serial@5a070000
Out: serial@5a070000
Err: serial@5a070000
Model: Toradex Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT V1.1A,
Serial# 06617018
Net: eth0: ethernet@5b040000 [PRIME]
Hit any key to stop autoboot: 0
Functionality wise the following is known to be working:
- eMMC and MMC/SD card
- Ethernet (*)
- GPIOs
- I2C
Unfortunately, there is no USB functionality for the i.MX 8QXP as of
yet.
* With the SCU FW from the latest Toradex BSP 5.0.0 (SCU FW 1.5.1)
ETH PHY encounters bring up problems after reset, this will be fixed
soon on SCU FW side.
[1] https://www.toradex.com/computer-on-modules/apalis-arm-family/nxp-imx-8x
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Introduce initial hierarchy of device trees for Apalis iMX8X
System on Module.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
the mem_map structure containing the size of SDRAM is used in various
cache functions in cache_v8.c thus we need to update it with the
sdram size the board is configured with as well. Without this
the cache functions do not get setup properly and can hang
in the case where a board reports more SDRAM than defined in
PHYS_SDRAM_SIZE.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Implement board_phys_sdram_size() to automatically detect Verdin iMX8M
Mini DualLite 1GB vs. Verdin iMX8M Mini Quad 2GB.
Note: This only works if we keep using similar RAM chips!
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
