The clock enable bits for UMC are more SoC-specific than for
the other hardware blocks. Separate the UMC clocks and the other
clocks for better code reuse across SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
At first, we thought the LD20 PLL setting would be board dependent,
but this argument turned out unneeded after all.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
It is useful to name each method so that we can print out this name when
using the method. Currently this happens using a separate function. In
preparation for unifying this, add a name to each method.
The name is only available if we have libcommon support (i.e can use
printf()).
Signed-off-by: Simon Glass <sjg@chromium.org>
Add the LD11 SoC data and adjuts the printf() format because this is
a 64-bit SoC. Otherwise, 16-digits pointer addresses would break
the log format.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Do not hard-code the number of DX blocks because it is a different
value for LD11 SoC.
Move the macro NR_DATX8_PER_DDRPHY to ddrphy-training.c since it
is the last user.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The DDR PHY register view of LD11 is slightly different from that
of LD4/Pro4/sLD8, but it will be possible to share the register
macros (and I want to re-use as much code as possible). Change
the code in the more flexible form.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The USB boot without the stand-by MPU is available on ES3 or later
of LD11 SoC, but the code in this if-conditional block must not be
run when booting from USB. Check if the boot device is USB, and
skip the code in the case.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
At the moment, the clk driver is not clever enough to automatically
enable parent clocks like Linux. Enable the STDMAC clock explicitly
if USB is enabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This PHY might be used for other SoCs in the future.
Avoid including the SoC name in the header name.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The environment fdt_file is useful to remember the appropriate DTB
file name. Adjust it to the recent renaming in the upstream kernel.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
These have now landed upstream. The naming is different and in one case the
function signature has changed. Update the code to match.
This applies the following upstream commits by
Thierry Reding <treding@nvidia.com> :
604e61e fdt: Add functions to retrieve strings
8702bd1 fdt: Add a function to get the index of a string
2218387 fdt: Add a function to count strings
Signed-off-by: Simon Glass <sjg@chromium.org>
As for LD11/LD20, we can no longer rely on the udelay() in the PLL
init functions. udelay(200) is needed here to keep the ethernet
device in the reset state for enough time. Anyway, 200 usec is
quite short for humans, so nobody cares it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Raise the VDD09 voltage line to 1.0V to suppress VBO noise.
This errata work-around code is needed only for ES1.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
- Do not reference CONFIG_DDR_FREQ; now the DDR frequency
is passed from the uniphier_board_data structure
- Constify parameter arrays
- Tidy up cluttered macros
- Lots of code cleanups
- Lots of coding style fixes
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
For LD11 and LD20 SoCs, the System Bus and NAND are multiplexed
in the same I/O pins. When booting from a NAND device, pin-mux
for the System Bus must not be set-up because they are exclusive
with each other.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Rather than having a global variable, pass the spl_image as a parameter.
This avoids BSS use, and makes it clearer what the function is actually
doing.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add a linker list declaration for this method and remove the explicit
switch() code. Update existing users.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
At present some spl_xxx_load_image() functions take a parameter and some
don't. Of those that do, most take an integer but one takes a string.
Convert this parameter into a struct so that we can pass all functions the
same thing. This will allow us to use a common function signature.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Instead of using the global spl_image variable, pass the required struct in
as an argument.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
- Initialize PLLs (SPL initializes only DPLL to save the precious
SPL memory footprint)
- Adjust CPLL/MPLL to the final tape-out frequency
- Set the Cortex-A53 clock to the maximum frequency since it is
running at 500MHz (SPLL/4) on startup
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
As I repeated in the ML, I am unhappy with config entries with bare
defaults. Kick them out of arch/arm/mach-uniphier/Kconfig.
Currently, CONFIG_SPL_SERIAL_SUPPORT is not user-configurable
(build fails without it), but it should be fixed later anyway,
so I am moving CONFIG_SPL_SERIAL_SUPPORT to defconfigs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Import the latest version from the Diag software.
- Support LD21 SoC (including DDR chips in the package)
- Per-board granule adjustment for both reference and TV boards
- Misc cleanups
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot
proper. Split the common code into pll-base-ld20.c for easier
re-use.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Now PLLs for DRAM controller are initialized in SPL, and the others
in U-Boot proper. Setting up all of them in a single directory will
be helpful when we want to share code between SPL and U-Boot proper.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The PLL for the DRAM interface must be initialized in SPL, but the
others can be delayed until U-Boot proper. Move them from SPL to
U-Boot proper to save the precious SPL memory footprint.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This is the last code in the mach-uniphier/pinctrl/ directory.
Push the remaining code out to delete the directory entirely.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Use the pin-mux data in the pinctrl drivers by directly calling
pinctrl_generic_set_state().
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The NAND subsystem has not supported the Driver Model yet, but the
NAND pin-mux data are already in the pinctrl drivers. Use them by
calling pinctrl_generic_set_state() directly.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Unfortunately, this SoC needs per-board adjustment between clock
and address/command lines. This flag will be passed to the DRAM
init function and used for compensating the difference of DRAM
timing parameters.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, the UniPhier platform calls several init functions in the
following order:
[1] spl_board_init()
[2] board_early_init_f()
[3] board_init()
[4] board_early_init_r()
[5] board_late_init()
The serial console is not ready at the point of [2], so we want to
avoid using [2] from the view point of debuggability. Fortunately,
all of the initialization in [2] can be delayed until [3]. I see no
good reason to split into [3] and [4]. So, merge [2] through [4].
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
We can use checkboard() stub to show additional board information,
so misc_init_f() should not be used for this purpose.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Add ARCH_SUPPORT_PSCI as a non-configurable option that platforms
can select. Then, move CONFIG_ARMV7_PSCI, which is automatically
enabled if both ARMV7_NONSEC and ARCH_SUPPORT_PSCI are enabled.
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The revision of the original support card (rev 3.5, rev 3.6) fits in
the 8 bit width revision register. When it was extended in a weird
way, it was versioned in the format of "3.6.x" (where it should have
been "3.7", of course). What is worse, only the sub-level version
"6.x" was recorded in the 8 bit width register, completely ignoring
the compatibility of the revision register format.
This patch saves madly-versioned support cards by assuming the major
version "3" when the MSB 4 bit of the register is read as "6". With
this, the support card revision that were displayed as "6.10" is now
corrected to "3.6.10".
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This supports the system reset via PSCI for ARMv7 SoCs.
Because the system reset is not supported on PSCI 0.1, let's define
CONFIG_ARMV7_PSCI_1_0. (it is supported since PSCI 0.2, but there
is no CONFIG to enable it in U-Boot for now.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all
cases we are mirroring the values used by the Linux Kernel here. Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Stefan Roese <sr@denx.de>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Steve Rae <steve.rae@raedomain.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: "Pali Rohár" <pali.rohar@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: David Feng <fenghua@phytium.com.cn>
Cc: Alison Wang <b18965@freescale.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: York Sun <york.sun@nxp.com>
Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
Cc: Saksham Jain <saksham.jain@nxp.com>
Cc: Qianyu Gong <qianyu.gong@nxp.com>
Cc: Wang Dongsheng <dongsheng.wang@nxp.com>
Cc: Alex Porosanu <alexandru.porosanu@freescale.com>
Cc: Hongbo Zhang <hongbo.zhang@nxp.com>
Cc: tang yuantian <Yuantian.Tang@freescale.com>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Cc: Josh Wu <josh.wu@atmel.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Christophe Ricard <christophe-h.ricard@st.com>
Cc: Anand Moon <linux.amoon@gmail.com>
Cc: Beniamino Galvani <b.galvani@gmail.com>
Cc: Carlo Caione <carlo@endlessm.com>
Cc: huang lin <hl@rock-chips.com>
Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Cc: Xu Ziyuan <xzy.xu@rock-chips.com>
Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Bernhard Nortmann <bernhard.nortmann@web.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Ben Whitten <ben.whitten@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: "Andrew F. Davis" <afd@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Carlos Hernandez <ceh@ti.com>
Cc: Ladislav Michl <ladis@linux-mips.org>
Cc: Ash Charles <ashcharles@gmail.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Daniel Allred <d-allred@ti.com>
Cc: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Chin Liang See <clsee@altera.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
This outer cache allows to control active ways independently for
each CPU, so this function will be useful to set up active ways
for a specific CPU.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Move this option to Kconfig, renaming it into CONFIG_CACHE_UNIPHIER.
The new option name makes sense enough, and the same as Linux has.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Now, all of these macros are only used in cache-uniphier.c, so
there is no need to export them in a header file.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The DRAM is available at this point, so setup the temporary stack
and call the C function to reduce the code duplication a bit.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The System Cache (outer cache) is used not only as L2 cache,
but also as locked SRAM. The functions for turning on/off it
is necessary whether the L2 cache is enabled or not.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
As the sLD3 Boot ROM has a complex page table, it is difficult to
set up the debug UART with enabling it. It will be much easier to
initialize the UART port after switching over to the straight-mapped
page table.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Commit 4b50369fb5 ("ARM: uniphier: create early page table at
run-time") broke the ROM boot mode for PH1-sLD3 SoC, because the
run-time page table creation requires the outer cache register
access but the page table in the sLD3 Boot ROM does not straight-map
virtual/physical addresses.
The idea here is to check the current page table to determine if
it is a straight map table. If not, adjust the outer cache register
base.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Here, the ldr pseudo-instruction falls into the ldr + data set.
The register access by [r1, #offset] produces shorter code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
If CONFIG_UNIPHIER_L2CACHE_ON is undefined, the L2 cache is never
enabled, so there is no need for v7_outer_cache_disable(). The weak
stub avoids the compile error anyway.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as
SRAM by locking ways.
These functions will be used to transfer the trampoline code for SMP
into the locked SRAM.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Unify the range/all operation routines into the common function,
uniphier_cache_maint_common(), and sync code with Linux a bit more.
This reduces the code duplication.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Deassert resets and enable clock signals of xHCI blocks if the
corresponding CONFIG is enabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
I need to add more board attributes, so the "flags" member will be
handier than separate boolean ones.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Sync register macros with Linux code. This will be helpful to
develop the counterpart of Linux.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This does not have much impact on behavior, but makes code look more
more like Linux. The use of devm_ioremap() often helps to delete
.remove callbacks entirely.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Introduce virtual and physical addresses in the mapping table. This change
have no impact on existing boards because they all use idential mapping.
Signed-off-by: York Sun <york.sun@nxp.com>
I will carry this work-around until it is cared in the kernel.
This looks up the AIDET node and sets up a register to handle
active low interrupt signals.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The SPL code already knows which boot device it calls the spl_boot_mode()
on, so pass that information into the function. This allows the code of
spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets
board_boot_order() correctly alter the behavior of the boot process.
The later one is important, since in certain cases, it is desired that
spl_boot_device() return value be overriden using board_boot_order().
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[add newly introduced zynq variant]
Signed-aff-by: Andreas Bießmann <andreas@biessmann.org>
The DRAM PHY layer on PH1-LD20 is able to calibrate PHY parameters
periodically. This compensates for the voltage and temperature
deviation and improves the PHY parameter adjustment. Instead, it
requires 64 byte scratch memory in each DRAM channel for the dynamic
training. The memory regions must be reserved in DT before jumping
to the kernel.
The scratch area can be anywhere in each DRAM channel, but the DRAM
init code in SPL currently assigns it at the end of each channel.
So, it makes sense to reserve the regions on run-time by U-Boot
instead of statically embedding it in the DT in Linux. Anyway,
a boot-loader should know much more about memory initialization
than the kernel.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This will make it easier to select config options specific to
particular ARM processor generation.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
I noticed secondary CPUs sometimes fail to wake up, and the root
cause is that the sev instruction wakes up slave CPUs before the
preceding the register write is observed by them.
The read-back of the accessed register does not guarantee the order.
In order to ensure the order between the register write and the sev
instruction, a dsb instruction should be executed prior to the sev.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This code auto-detects the best-match FDT file name, but it should
respect the user's choice if "fdt_file" environment is found in a
saved set of environments.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This function is shared between PH1-LD11 and PH1-LD20. The difference
is the boot-mode latch for the USB boot mode.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The Boot ROM on PH1-LD11/LD20 exports built-in APIs to load images
from an eMMC device. They are useful to reduce the memory footprint
of SPL, rather than compiling the whole MMC framework.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This header will be shared between PH1-LD11 and PH1-LD20
(and hopefully new ARMv8 SoCs developed in the future),
so umc64-regs.h would be a better fit.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The Boot ROM has enabled D-cache and MMU setting DDR memory area
as Normal Memory in its page table. Disable D-cache and MMU
before jumping to U-Boot proper.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
