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ARM: uniphier: rename outer-cache register macros

Browse source 
Sync register macros with Linux code.  This will be helpful to
develop the counterpart of Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2016-07-22 13:38:31 +09:00
parent ebab100a98
commit 4bab70a77d
6 changed files with 230 additions and 216 deletions
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2
arch/arm/mach-uniphier/arm32/Makefile
View file

@ -7,7 +7,7 @@ obj-y += lowlevel_init.o
obj-$(CONFIG_DEBUG_LL) += debug_ll.o
else
obj-y += late_lowlevel_init.o
obj-y += cache_uniphier.o
obj-y += cache-uniphier.o
endif
obj-y += timer.o

165
arch/arm/mach-uniphier/arm32/cache-uniphier.c Normal file
View file

@ -0,0 +1,165 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include <asm/armv7.h>
#include "ssc-regs.h"
#ifdef CONFIG_UNIPHIER_L2CACHE_ON
static void uniphier_cache_sync(void)
{
/* drain internal buffers */
writel(UNIPHIER_SSCOPE_CM_SYNC, UNIPHIER_SSCOPE);
/* need a read back to confirm */
readl(UNIPHIER_SSCOPE);
}
static void uniphier_cache_maint_all(u32 operation)
{
/* clear the complete notification flag */
writel(UNIPHIER_SSCOLPQS_EF, UNIPHIER_SSCOLPQS);
/* try until the command is successfully set */
do {
writel(UNIPHIER_SSCOQM_S_ALL | UNIPHIER_SSCOQM_CE | operation,
UNIPHIER_SSCOQM);
} while (readl(UNIPHIER_SSCOPPQSEF) &
(UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE));
/* wait until the operation is completed */
while (readl(UNIPHIER_SSCOLPQS) != UNIPHIER_SSCOLPQS_EF)
;
uniphier_cache_sync();
}
void v7_outer_cache_flush_all(void)
{
uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_FLUSH);
}
void v7_outer_cache_inval_all(void)
{
uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_INV);
}
static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation)
{
/* clear the complete notification flag */
writel(UNIPHIER_SSCOLPQS_EF, UNIPHIER_SSCOLPQS);
/* try until the command is successfully set */
do {
writel(UNIPHIER_SSCOQM_S_RANGE | UNIPHIER_SSCOQM_CE | operation,
UNIPHIER_SSCOQM);
writel(start, UNIPHIER_SSCOQAD);
writel(size, UNIPHIER_SSCOQSZ);
} while (readl(UNIPHIER_SSCOPPQSEF) &
(UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE));
/* wait until the operation is completed */
while (readl(UNIPHIER_SSCOLPQS) != UNIPHIER_SSCOLPQS_EF)
;
}
static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
{
u32 size;
/*
* If start address is not aligned to cache-line,
* do cache operation for the first cache-line
*/
start = start & ~(UNIPHIER_SSC_LINE_SIZE - 1);
size = end - start;
if (unlikely(size >= (u32)(-UNIPHIER_SSC_LINE_SIZE))) {
/* this means cache operation for all range */
uniphier_cache_maint_all(operation);
return;
}
/*
* If end address is not aligned to cache-line,
* do cache operation for the last cache-line
*/
size = ALIGN(size, UNIPHIER_SSC_LINE_SIZE);
while (size) {
u32 chunk_size = size > UNIPHIER_SSC_RANGE_OP_MAX_SIZE ?
UNIPHIER_SSC_RANGE_OP_MAX_SIZE : size;
__uniphier_cache_maint_range(start, chunk_size, operation);
start += chunk_size;
size -= chunk_size;
}
uniphier_cache_sync();
}
void v7_outer_cache_flush_range(u32 start, u32 end)
{
uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_FLUSH);
}
void v7_outer_cache_inval_range(u32 start, u32 end)
{
if (start & (UNIPHIER_SSC_LINE_SIZE - 1)) {
start &= ~(UNIPHIER_SSC_LINE_SIZE - 1);
__uniphier_cache_maint_range(start, UNIPHIER_SSC_LINE_SIZE,
UNIPHIER_SSCOQM_CM_FLUSH);
start += UNIPHIER_SSC_LINE_SIZE;
}
if (start >= end) {
uniphier_cache_sync();
return;
}
if (end & (UNIPHIER_SSC_LINE_SIZE - 1)) {
end &= ~(UNIPHIER_SSC_LINE_SIZE - 1);
__uniphier_cache_maint_range(end, UNIPHIER_SSC_LINE_SIZE,
UNIPHIER_SSCOQM_CM_FLUSH);
}
if (start >= end) {
uniphier_cache_sync();
return;
}
uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_INV);
}
void v7_outer_cache_enable(void)
{
u32 tmp;
writel(U32_MAX, UNIPHIER_SSCLPDAWCR); /* activate all ways */
tmp = readl(UNIPHIER_SSCC);
tmp |= UNIPHIER_SSCC_ON;
writel(tmp, UNIPHIER_SSCC);
}
#endif
void v7_outer_cache_disable(void)
{
u32 tmp;
tmp = readl(UNIPHIER_SSCC);
tmp &= ~UNIPHIER_SSCC_ON;
writel(tmp, UNIPHIER_SSCC);
}
void enable_caches(void)
{
dcache_enable();
}

156
arch/arm/mach-uniphier/arm32/cache_uniphier.c
View file

@ -1,156 +0,0 @@
/*
* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include <asm/armv7.h>
#include "ssc-regs.h"
#ifdef CONFIG_UNIPHIER_L2CACHE_ON
static void uniphier_cache_sync(void)
{
writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
readl(SSCOPE); /* need a read back to confirm */
}
static void uniphier_cache_maint_all(u32 operation)
{
/* clear the complete notification flag */
writel(SSCOLPQS_EF, SSCOLPQS);
/* try until the command is successfully set */
do {
writel(SSCOQM_S_ALL | SSCOQM_CE | operation, SSCOQM);
} while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
/* wait until the operation is completed */
while (readl(SSCOLPQS) != SSCOLPQS_EF)
;
uniphier_cache_sync();
}
void v7_outer_cache_flush_all(void)
{
uniphier_cache_maint_all(SSCOQM_CM_WB_INV);
}
void v7_outer_cache_inval_all(void)
{
uniphier_cache_maint_all(SSCOQM_CM_INV);
}
static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation)
{
/* clear the complete notification flag */
writel(SSCOLPQS_EF, SSCOLPQS);
/* try until the command is successfully set */
do {
writel(SSCOQM_S_ADDRESS | SSCOQM_CE | operation, SSCOQM);
writel(start, SSCOQAD);
writel(size, SSCOQSZ);
} while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
/* wait until the operation is completed */
while (readl(SSCOLPQS) != SSCOLPQS_EF)
;
}
static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
{
u32 size;
/*
* If start address is not aligned to cache-line,
* do cache operation for the first cache-line
*/
start = start & ~(SSC_LINE_SIZE - 1);
size = end - start;
if (unlikely(size >= (u32)(-SSC_LINE_SIZE))) {
/* this means cache operation for all range */
uniphier_cache_maint_all(operation);
return;
}
/*
* If end address is not aligned to cache-line,
* do cache operation for the last cache-line
*/
size = ALIGN(size, SSC_LINE_SIZE);
while (size) {
u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ?
SSC_RANGE_OP_MAX_SIZE : size;
__uniphier_cache_maint_range(start, chunk_size, operation);
start += chunk_size;
size -= chunk_size;
}
uniphier_cache_sync();
}
void v7_outer_cache_flush_range(u32 start, u32 end)
{
uniphier_cache_maint_range(start, end, SSCOQM_CM_WB_INV);
}
void v7_outer_cache_inval_range(u32 start, u32 end)
{
if (start & (SSC_LINE_SIZE - 1)) {
start &= ~(SSC_LINE_SIZE - 1);
__uniphier_cache_maint_range(start, SSC_LINE_SIZE,
SSCOQM_CM_WB_INV);
start += SSC_LINE_SIZE;
}
if (start >= end) {
uniphier_cache_sync();
return;
}
if (end & (SSC_LINE_SIZE - 1)) {
end &= ~(SSC_LINE_SIZE - 1);
__uniphier_cache_maint_range(end, SSC_LINE_SIZE,
SSCOQM_CM_WB_INV);
}
if (start >= end) {
uniphier_cache_sync();
return;
}
uniphier_cache_maint_range(start, end, SSCOQM_CM_INV);
}
void v7_outer_cache_enable(void)
{
u32 tmp;
writel(U32_MAX, SSCLPDAWCR); /* activate all ways */
tmp = readl(SSCC);
tmp |= SSCC_ON;
writel(tmp, SSCC);
}
#endif
void v7_outer_cache_disable(void)
{
u32 tmp;
tmp = readl(SSCC);
tmp &= ~SSCC_ON;
writel(tmp, SSCC);
}
void enable_caches(void)
{
dcache_enable();
}

4
arch/arm/mach-uniphier/arm32/late_lowlevel_init.S
View file

@ -10,9 +10,9 @@
#include "ssc-regs.h"
ENTRY(lowlevel_init)
ldr r1, = SSCC
ldr r1, = UNIPHIER_SSCC
ldr r0, [r1]
bic r0, r0, #SSCC_ON @ L2 disable
bic r0, r0, #UNIPHIER_SSCC_ON @ L2 disable
str r0, [r1]
mov pc, lr
ENDPROC(lowlevel_init)

18
arch/arm/mach-uniphier/arm32/lowlevel_init.S
View file

@ -1,5 +1,7 @@
/*
* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2012-2015 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -94,26 +96,26 @@ ENTRY(setup_init_ram)
*/
0:
/*
* set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
* set UNIPHIER_SSCOQM, UNIPHIER_SSCOQAD, UNIPHIER_SSCOQSZ, UNIPHIER_SSCOQWN in this order
*/
ldr r0, = 0x00408006 @ touch to zero with address range
ldr r1, = SSCOQM
ldr r1, = UNIPHIER_SSCOQM
str r0, [r1]
ldr r0, = BOOT_RAM_BASE
ldr r1, = SSCOQAD
ldr r1, = UNIPHIER_SSCOQAD
str r0, [r1]
ldr r0, = BOOT_RAM_SIZE
ldr r1, = SSCOQSZ
ldr r1, = UNIPHIER_SSCOQSZ
str r0, [r1]
ldr r0, = BOOT_WAY_BITS
ldr r1, = SSCOQWN
ldr r1, = UNIPHIER_SSCOQWN
str r0, [r1]
ldr r1, = SSCOPPQSEF
ldr r1, = UNIPHIER_SSCOPPQSEF
ldr r0, [r1]
cmp r0, #0 @ check if the command is successfully set
bne 0b @ try again if an error occurs
ldr r1, = SSCOLPQS
ldr r1, = UNIPHIER_SSCOLPQS
1:
ldr r0, [r1]
cmp r0, #0x4

101
arch/arm/mach-uniphier/arm32/ssc-regs.h
View file

@ -2,6 +2,7 @@
* UniPhier System Cache (L2 Cache) registers
*
* Copyright (C) 2011-2014 Panasonic Corporation
* Copyright (C) 2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -9,57 +10,59 @@
#ifndef ARCH_SSC_REGS_H
#define ARCH_SSC_REGS_H
#define SSCC 0x500c0000
#define SSCC_BST (0x1 << 20)
#define SSCC_ACT (0x1 << 19)
#define SSCC_WTG (0x1 << 18)
#define SSCC_PRD (0x1 << 17)
#define SSCC_WBWA (0x1 << 16)
#define SSCC_EX (0x1 << 13)
#define SSCC_ON (0x1 << 0)
/* control registers */
#define UNIPHIER_SSCC 0x500c0000 /* Control Register */
#define UNIPHIER_SSCC_BST (0x1 << 20) /* UCWG burst read */
#define UNIPHIER_SSCC_ACT (0x1 << 19) /* Inst-Data separate */
#define UNIPHIER_SSCC_WTG (0x1 << 18) /* WT gathering on */
#define UNIPHIER_SSCC_PRD (0x1 << 17) /* enable pre-fetch */
#define UNIPHIER_SSCC_ON (0x1 << 0) /* enable cache */
#define UNIPHIER_SSCLPDAWCR 0x500c0030 /* Unified/Data Active Way Control */
#define UNIPHIER_SSCLPIAWCR 0x500c0034 /* Instruction Active Way Control */
#define SSCLPDAWCR 0x500c0030
/* revision registers */
#define UNIPHIER_SSCID 0x503c0100 /* ID Register */
#define SSCOPE 0x506c0244
#define SSCOPE_CM_SYNC 0x00000008
/* operation registers */
#define UNIPHIER_SSCOPE 0x506c0244 /* Cache Operation Primitive Entry */
#define UNIPHIER_SSCOPE_CM_INV 0x0 /* invalidate */
#define UNIPHIER_SSCOPE_CM_CLEAN 0x1 /* clean */
#define UNIPHIER_SSCOPE_CM_FLUSH 0x2 /* flush */
#define UNIPHIER_SSCOPE_CM_SYNC 0x8 /* sync (drain bufs) */
#define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */
#define UNIPHIER_SSCOQM 0x506c0248
#define UNIPHIER_SSCOQM_TID_MASK (0x3 << 21)
#define UNIPHIER_SSCOQM_TID_LRU_DATA (0x0 << 21)
#define UNIPHIER_SSCOQM_TID_LRU_INST (0x1 << 21)
#define UNIPHIER_SSCOQM_TID_WAY (0x2 << 21)
#define UNIPHIER_SSCOQM_S_MASK (0x3 << 17)
#define UNIPHIER_SSCOQM_S_RANGE (0x0 << 17)
#define UNIPHIER_SSCOQM_S_ALL (0x1 << 17)
#define UNIPHIER_SSCOQM_S_WAY (0x2 << 17)
#define UNIPHIER_SSCOQM_CE (0x1 << 15) /* notify completion */
#define UNIPHIER_SSCOQM_CW (0x1 << 14)
#define UNIPHIER_SSCOQM_CM_MASK (0x7)
#define UNIPHIER_SSCOQM_CM_INV 0x0 /* invalidate */
#define UNIPHIER_SSCOQM_CM_CLEAN 0x1 /* clean */
#define UNIPHIER_SSCOQM_CM_FLUSH 0x2 /* flush */
#define UNIPHIER_SSCOQM_CM_PREFETCH 0x3 /* prefetch to cache */
#define UNIPHIER_SSCOQM_CM_PREFETCH_BUF 0x4 /* prefetch to pf-buf */
#define UNIPHIER_SSCOQM_CM_TOUCH 0x5 /* touch */
#define UNIPHIER_SSCOQM_CM_TOUCH_ZERO 0x6 /* touch to zero */
#define UNIPHIER_SSCOQM_CM_TOUCH_DIRTY 0x7 /* touch with dirty */
#define UNIPHIER_SSCOQAD 0x506c024c /* Cache Operation Queue Address */
#define UNIPHIER_SSCOQSZ 0x506c0250 /* Cache Operation Queue Size */
#define UNIPHIER_SSCOQMASK 0x506c0254 /* Cache Operation Queue Address Mask */
#define UNIPHIER_SSCOQWN 0x506c0258 /* Cache Operation Queue Way Number */
#define UNIPHIER_SSCOPPQSEF 0x506c025c /* Cache Operation Queue Set Complete */
#define UNIPHIER_SSCOPPQSEF_FE (0x1 << 1)
#define UNIPHIER_SSCOPPQSEF_OE (0x1 << 0)
#define UNIPHIER_SSCOLPQS 0x506c0260 /* Cache Operation Queue Status */
#define UNIPHIER_SSCOLPQS_EF (0x1 << 2)
#define UNIPHIER_SSCOLPQS_EST (0x1 << 1)
#define UNIPHIER_SSCOLPQS_QST (0x1 << 0)
#define SSCOQM 0x506c0248
#define SSCOQM_TID_MASK (0x3 << 21)
#define SSCOQM_TID_BY_WAY (0x2 << 21)
#define SSCOQM_TID_BY_INST_WAY (0x1 << 21)
#define SSCOQM_TID_BY_DATA_WAY (0x0 << 21)
#define SSCOQM_S_MASK (0x3 << 17)
#define SSCOQM_S_WAY (0x2 << 17)
#define SSCOQM_S_ALL (0x1 << 17)
#define SSCOQM_S_ADDRESS (0x0 << 17)
#define SSCOQM_CE (0x1 << 15)
#define SSCOQM_CW (0x1 << 14)
#define SSCOQM_CM_MASK (0x7)
#define SSCOQM_CM_DIRT_TOUCH (0x7)
#define SSCOQM_CM_ZERO_TOUCH (0x6)
#define SSCOQM_CM_NORM_TOUCH (0x5)
#define SSCOQM_CM_PREF_FETCH (0x4)
#define SSCOQM_CM_SSC_FETCH (0x3)
#define SSCOQM_CM_WB_INV (0x2)
#define SSCOQM_CM_WB (0x1)
#define SSCOQM_CM_INV (0x0)
#define SSCOQAD 0x506c024c
#define SSCOQSZ 0x506c0250
#define SSCOQWN 0x506c0258
#define SSCOPPQSEF 0x506c025c
#define SSCOPPQSEF_FE (0x1 << 1)
#define SSCOPPQSEF_OE (0x1 << 0)
#define SSCOLPQS 0x506c0260
#define SSCOLPQS_EF (0x1 << 2)
#define SSCOLPQS_EST (0x1 << 1)
#define SSCOLPQS_QST (0x1 << 0)
#define SSCOQCE0 0x506c0270
#define SSC_LINE_SIZE 128
#define SSC_RANGE_OP_MAX_SIZE (0x00400000 - (SSC_LINE_SIZE))
#define UNIPHIER_SSC_LINE_SIZE 128
#define UNIPHIER_SSC_RANGE_OP_MAX_SIZE (0x00400000 - (UNIPHIER_SSC_LINE_SIZE))
#endif /* ARCH_SSC_REGS_H */