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https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
ARM: uniphier: refactor DDR PHY parameter dump command
Do not hard-code the number of DX blocks because it is a different value for LD11 SoC. Move the macro NR_DATX8_PER_DDRPHY to ddrphy-training.c since it is the last user. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada
parent
6dd34ae4c4
commit
adf55f63ae
3 changed files with 50 additions and 44 deletions
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@ -11,7 +11,6 @@
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#include <linux/sizes.h>
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#include "../soc-info.h"
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#include "ddrphy-init.h"
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#include "ddrphy-regs.h"
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/* Select either decimal or hexadecimal */
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@ -23,22 +22,29 @@
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/* field separator */
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#define FS " "
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static unsigned long uniphier_ld4_base[] = {
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0x5bc01000,
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0x5be01000,
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0 /* sentinel */
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struct phy_param {
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resource_size_t base;
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unsigned int nr_dx;
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};
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static unsigned long uniphier_pro4_base[] = {
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0x5bc01000,
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0x5be01000,
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0 /* sentinel */
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static const struct phy_param uniphier_ld4_phy_param[] = {
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{ .base = 0x5bc01000, .nr_dx = 2, },
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{ .base = 0x5be01000, .nr_dx = 2, },
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{ /* sentinel */ }
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};
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static unsigned long uniphier_sld8_base[] = {
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0x5bc01000,
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0x5be01000,
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0 /* sentinel */
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static const struct phy_param uniphier_pro4_phy_param[] = {
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{ .base = 0x5bc01000, .nr_dx = 2, },
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{ .base = 0x5bc02000, .nr_dx = 2, },
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{ .base = 0x5be01000, .nr_dx = 2, },
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{ .base = 0x5be02000, .nr_dx = 2, },
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{ /* sentinel */ }
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};
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static const struct phy_param uniphier_sld8_phy_param[] = {
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{ .base = 0x5bc01000, .nr_dx = 2, },
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{ .base = 0x5be01000, .nr_dx = 2, },
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{ /* sentinel */ }
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};
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static void print_bdl(void __iomem *reg, int n)
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@ -50,17 +56,17 @@ static void print_bdl(void __iomem *reg, int n)
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printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f);
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}
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static void dump_loop(unsigned long *base,
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static void dump_loop(const struct phy_param *phy_param,
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void (*callback)(void __iomem *))
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{
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void __iomem *phy_base, *dx_base;
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int p, dx;
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for (p = 0; *base; base++, p++) {
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phy_base = ioremap(*base, SZ_4K);
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for (p = 0; phy_param->base; phy_param++, p++) {
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phy_base = ioremap(phy_param->base, SZ_4K);
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dx_base = phy_base + PHY_DX_BASE;
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for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
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for (dx = 0; dx < phy_param->nr_dx; dx++) {
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printf("PHY%dDX%d:", p, dx);
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(*callback)(dx_base);
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dx_base += PHY_DX_STRIDE;
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@ -80,12 +86,12 @@ static void __wbdl_dump(void __iomem *dx_base)
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readl(dx_base + PHY_DX_LCDLR1) & 0xff);
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}
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static void wbdl_dump(unsigned long *base)
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static void wbdl_dump(const struct phy_param *phy_param)
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{
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printf("\n--- Write Bit Delay Line ---\n");
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printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
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dump_loop(base, &__wbdl_dump);
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dump_loop(phy_param, &__wbdl_dump);
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}
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static void __rbdl_dump(void __iomem *dx_base)
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@ -97,12 +103,12 @@ static void __rbdl_dump(void __iomem *dx_base)
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(readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff);
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}
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static void rbdl_dump(unsigned long *base)
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static void rbdl_dump(const struct phy_param *phy_param)
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{
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printf("\n--- Read Bit Delay Line ---\n");
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printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
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dump_loop(base, &__rbdl_dump);
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dump_loop(phy_param, &__rbdl_dump);
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}
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static void __wld_dump(void __iomem *dx_base)
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@ -120,12 +126,12 @@ static void __wld_dump(void __iomem *dx_base)
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}
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}
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static void wld_dump(unsigned long *base)
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static void wld_dump(const struct phy_param *phy_param)
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{
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printf("\n--- Write Leveling Delay ---\n");
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printf(" Rank0 Rank1 Rank2 Rank3\n");
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dump_loop(base, &__wld_dump);
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dump_loop(phy_param, &__wld_dump);
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}
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static void __dqsgd_dump(void __iomem *dx_base)
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@ -142,12 +148,12 @@ static void __dqsgd_dump(void __iomem *dx_base)
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}
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}
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static void dqsgd_dump(unsigned long *base)
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static void dqsgd_dump(const struct phy_param *phy_param)
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{
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printf("\n--- DQS Gating Delay ---\n");
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printf(" Rank0 Rank1 Rank2 Rank3\n");
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dump_loop(base, &__dqsgd_dump);
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dump_loop(phy_param, &__dqsgd_dump);
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}
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static void __mdl_dump(void __iomem *dx_base)
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@ -158,12 +164,12 @@ static void __mdl_dump(void __iomem *dx_base)
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printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
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}
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static void mdl_dump(unsigned long *base)
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static void mdl_dump(const struct phy_param *phy_param)
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{
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printf("\n--- Master Delay Line ---\n");
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printf(" IPRD TPRD MDLD\n");
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dump_loop(base, &__mdl_dump);
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dump_loop(phy_param, &__mdl_dump);
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}
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#define REG_DUMP(x) \
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@ -178,15 +184,15 @@ static void mdl_dump(unsigned long *base)
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printf("%3d: DX%d%-7s: %p : %08x\n", \
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ofst >> PHY_REG_SHIFT, (dx), #x, reg, readl(reg)); }
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static void reg_dump(unsigned long *base)
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static void reg_dump(const struct phy_param *phy_param)
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{
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void __iomem *phy_base;
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int p, dx;
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printf("\n--- DDR PHY registers ---\n");
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for (p = 0; *base; base++, p++) {
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phy_base = ioremap(*base, SZ_4K);
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for (p = 0; phy_param->base; phy_param++, p++) {
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phy_base = ioremap(phy_param->base, SZ_4K);
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printf("== PHY%d (base: %p) ==\n", p, phy_base);
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printf(" No: Name : Address : Data\n");
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@ -216,7 +222,7 @@ static void reg_dump(unsigned long *base)
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REG_DUMP(MR2);
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REG_DUMP(MR3);
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for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
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for (dx = 0; dx < phy_param->nr_dx; dx++) {
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DX_REG_DUMP(dx, GCR);
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DX_REG_DUMP(dx, GTR);
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}
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@ -228,17 +234,17 @@ static void reg_dump(unsigned long *base)
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static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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char *cmd = argv[1];
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unsigned long *base;
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const struct phy_param *phy_param;
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switch (uniphier_get_soc_type()) {
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case SOC_UNIPHIER_LD4:
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base = uniphier_ld4_base;
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phy_param = uniphier_ld4_phy_param;
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break;
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case SOC_UNIPHIER_PRO4:
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base = uniphier_pro4_base;
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phy_param = uniphier_pro4_phy_param;
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break;
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case SOC_UNIPHIER_SLD8:
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base = uniphier_sld8_base;
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phy_param = uniphier_sld8_phy_param;
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break;
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default:
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printf("unsupported SoC\n");
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@ -249,22 +255,22 @@ static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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cmd = "all";
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if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
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wbdl_dump(base);
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wbdl_dump(phy_param);
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if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
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rbdl_dump(base);
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rbdl_dump(phy_param);
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if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
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wld_dump(base);
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wld_dump(phy_param);
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if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
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dqsgd_dump(base);
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dqsgd_dump(phy_param);
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if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
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mdl_dump(base);
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mdl_dump(phy_param);
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if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
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reg_dump(base);
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reg_dump(phy_param);
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return CMD_RET_SUCCESS;
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}
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@ -10,9 +10,6 @@
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#include <linux/compiler.h>
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#include <linux/types.h>
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/* for LD4, Pro4, sLD8 */
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#define NR_DATX8_PER_DDRPHY 2
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int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus);
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void ddrphy_prepare_training(void __iomem *phy_base, int rank);
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int ddrphy_training(void __iomem *phy_base);
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@ -12,6 +12,9 @@
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#include "ddrphy-init.h"
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#include "ddrphy-regs.h"
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/* for LD4, Pro4, sLD8 */
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#define NR_DATX8_PER_DDRPHY 2
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void ddrphy_prepare_training(void __iomem *phy_base, int rank)
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{
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void __iomem *dx_base = phy_base + PHY_DX_BASE;
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