Current driver always performs a phy soft reset when connecting the phy
device, but soft reset is not always supported by a phy device, so
introduce a quirk PHY_FLAG_BROKEN_RESET to let such a phy device to skip
soft reset. This commit uses 'flags' of phy device structure to store the
quirk.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The picoseconds to register value divisor(ps_to_regval) should be 60 and not
200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct
divisor because the 4-bit skew values are defined from 0x0000(-420ps) to
0xffff(480ps), increments of 60.
For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7.
With the previous divisor of 200, it would result in 0x2, which represents a
-300ps delay.
With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with
1Gb ethernet.
References:
http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Use the 'autoneg' flag available in phydev when checking if
autoneg is in use.
The previous implementation was checking directly in the PHY
if autoneg was supported. Some PHYs will report that autoneg
is supported, even when it is disabled. Thus it is not possible
to use that bit to determine if autoneg is currently in use or
not.
Signed-off-by: Alexandre Messier <amessier@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When configuring a PHY in fixed (forced) link mode, in order for
the changes to be applied, either one of these conditions must
be triggered:
1- PHY is reset
2- Autoneg is restarted
3- PHY transitions from power-down to power-up
Neither of these is currently done, so effectively the fixed link
configuration is not applied in the PHY.
Fix this by setting the Autoneg restart bit.
Signed-off-by: Alexandre Messier <amessier@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Micrel PHYs KSZ8021/31 and KSZ8081 have a feature where MDIO address 0
is considered as a broadcast address; the PHY will respond even if it
is not its configured (pinstrapped) address. This feature is enabled
by default.
The Linux kernel disables that feature at initialisation, but not
before it probes the MDIO bus. This causes an issue, because a PHY
at address 3 will be discovered at addresses 0 and 3, but will then
only respond at address 3. Because Linux attaches the first PHY it
discovers on 'eth0', it will attach the PHY from address 0, which
will never answer again.
Fix the issue by disabling the broadcast feature in U-Boot, before
Linux is started.
Signed-off-by: Alexandre Messier <amessier@tycoint.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This function can fail, so be sure to report any errors that occur.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
This property allows to specify fastest connection mode supported by
the MAC (as opposed to features of the phy).
There are situations when phy may handle faster modes than the
MAC (or even it's particular implementation or even due to CPU being too
slow).
This property is a standard one in Linux kernel these days and some
boards do already use it in their device tree descriptions.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
cc: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Current implementation only sets "port select" bit for non-1Gb mode.
That works fine if GMAC has just exited reset state but we may as well
change connection mode in runtime. Then we'll need to reprogram GMAC for
that new mode of operation and if previous mode was 10 or 100 Mb and new
one is 1 Gb we'll need to reset port mode bit.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
cc: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This new function will allow MAC drivers to override supported
capabilities of the phy. It is required when MAC cannot handle all
speeds supported by phy.
For example phy supports up-to 1Gb connections while MAC may only work
in modes up to 100 or even 10 Mbit/sec.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
of_set_phy_supported allows overwiting hardware capabilities of
a phy with values from the devicetree. This does not work with
the genphy driver though because the genphys config_init function
will overwrite all values adjusted by of_set_phy_supported. Fix
this by initialising the genphy features in the phy_driver struct
and in config_init just limit the features to the ones the hardware
can actually support. The resulting features are a subset of the
devicetree specified features and the hardware features.
This is a copy of the patch from Linux kernel, see
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=c242a47238fa2a6a54af8a16e62b54e6e031d4bc
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When a Gigabit PHY device is connected to a 10/100Mbits capable Ethernet
MAC, the driver will restrict the phydev->supported modes to mask off
Gigabit. If the Gigabit PHY comes out of reset with the Gigabit features
set by default in MII_CTRL1000, it will keep advertising these feature,
so by the time we call genphy_config_advert(), the condition on
phydev->supported having the Gigabit features on is false, and we do not
update MII_CTRL1000 with updated values, and we keep advertising Gigabit
features, eventually configuring the PHY for Gigabit whilst the Ethernet
MAC does not support that.
This patches fixes the problem by ensuring that the Gigabit feature bits
are always cleared in MII_CTRL1000, if the PHY happens to be a Gigabit
PHY, and then, if Gigabit features are supported, setting those and
updating MII_CTRL1000 accordingly.
This is a copy of patch from Linux kernel, see
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=5273e3a5ca94fbeb8e07d31203069220d5e682aa
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add a new member 'tbiaddr' to tsec_private struct. For non-DM driver,
it is initialized as CONFIG_SYS_TBIPA_VALUE, but for DM driver, we
can get this from device tree. Update the bindings doc as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This adds driver model support to Freescale TSEC ethernet driver.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
For internal routines like redundant_init(), startup_tsec() and
init_phy(), change to use tsec_private pointer as the parameter.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Adjust static functions in a proper order so that forward declaration
of tsec_send() can be avoided.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
rxbd and txbd are declared static with 8 byte alignment requirement,
but they can be put into struct tsec_private as well and are natually
aligned to 8 byte.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
At present rx_idx and tx_idx are declared as static variables
in the driver codes. To support multiple interfaces, move it to
struct tsec_private.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Clean up the tsec and fsl_mdio driver codes a little bit, by:
- Fix misuse of tab and space here and there
- Use correct multi-line comment format
- Replace license identifier to GPL-2.0+
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
You can now configure LAG on VSC9953's ports using the command:
ethsw [port <port_no>] aggr {[help] | show | <lag_group_no>}
A port must belong to a single LAG. By default, a port
belongs to a LAG equal to the port's number.
For each frame, a hash will be calculated based on
Source/Destination MAC addresses, Source/Destination IP(v4/v6)
addresses, Source/Destination ports. This hash will be used to
select a single egress port from LAG. This also assures
that frames from the same flow will always have the
same egress port.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
By default, the aging period is set to 0, so the dynamic
FDB entries are never removed. This patch sets the aging
time to 300 seconds.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When doing a software reset, the reset flag should be written without
other bits set. Writing the current state will lead to restoring the
state of the PHY (e.g. Powerdown), which is not what is expected from
a software reset.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Michael Welling <mwelling@ieee.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
In current driver, we always copy 4 bytes to the dest memory.
Actually the dest memory may be shorter than 4 bytes.
Add an argument to indicate the dest memory length.
Avoid writing memory outside of the bounds.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
In current driver everytime we memcpy 4 bytes to the dest memory
regardless of the remaining length.
This patch adds checking the remaining length before memcpy.
If the length is shorter than 4 bytes, memcpy the actual length of data
to the dest memory.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch fixes the following compile warning:
drivers/spi/fsl_qspi.c: In function 'fsl_qspi_probe':
drivers/spi/fsl_qspi.c:937:15:
warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
priv->regs = (struct fsl_qspi_regs *)plat->reg_base;
^
Just make the cast explicit.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
According to SD spec, CMD12, CMD52 for writing I/O abort in CCCR need
to be set an Abort command type when they are sent. So, we remove all
chip-specific #ifdefs and make it available for all platforms.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The MMC spec says "It is strongly recommended for hosts to implement
more than 500ms timeout value even if the card indicates the 250ms
maximum busy length." Even the previous value of 300ms is known to
be insufficient for some cards. So, increase the timeout to 500ms.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Management Complex firmware 9.0 has fixed the issue of
dprc_destroy_container i.e. the used portal is not return to the
free pool. Which was resulting in error ethernet driver want to
use this portal via either DPL or dynamically in Linux.
Hard-coding of portal id is removed.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add debug information prints to provide DPMAC statistics
- Number of bytes received
- Number of received and discard frames
- Number of bytes transferred
- Number of frames transferred
etc.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Management Complex FW 9.0 set the hardware depletion to be 20
buffers in order to support multiple pools in DPNI. This requires
driver to fill the pool with at least 21 to be able to receive
frames. So, Increase number of buffers for a pool.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Management Complex FW 9.0 puts a new requirement to provide Tx
confirmation and error queue configuration by calling
dpni_set_tx_conf API.
Configure report of only error frames for a tx frame.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Management Complex FW 9.0 puts a new requirement to prepare extended
parameters which should be provided as input in dpni_create. extended
parameters includes traffic class and IP reassembly configurations.
So prepare extended parameters with default "0" as input for
dpni_create.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
MC firmware version 9.0.0 contains
- Support of new APIs
- Update in existing APIs
- Change in Major and minor version of DPAA2 objects
This patch contains modifications in FLIB files to support new
MC firmware version.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Check and compare version of management complex's object with
the version supported by Freescale ldpaa2 ethernet driver.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Size of this snprintf "lltemac.%lx" is bigger than 16 characters.
Replacing it with "ll_tem.%lx"
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
xilinx_uartlite has been ported to DM, this patch makes the
xilinx-ppc405-generic and the xilinx-ppc440-generic boards use the new
DM driver.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Add quirk to disable high speed incase the high
speed was broken.This solves the issue where the
the controller is used in High Speed Mode and the
the hold time requirement for the JEDEC/MMC 4.41
specification is NOT met.
This timing issue is not on all boards and hence
provided config option to enable it when required.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Emil Lenchak <emill@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Clear high speed bit if it was not supported by
the driver.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Emil Lenchak <emill@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove hardcoded value zero as min frequency and
use config option CONFIG_ZYNQ_SDHCI_MIN_FREQ
defined in board config
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
MDC setting depends on pclk input clocks which varies across SoC. This
driver is used by xilinx zynq and zynqmp SOC.
Input clock frequence on silicon is 125MHz where divider 64 put
frequency below 2.5MHz requires by spec (125/64=1.95).
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Enable automatic crossover cable detection.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Use dev_get_addr() instead of reading reg base directly in the driver.
Core function is also more robust.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ZynqMP is using updated core with cdns,uart-r1p12 compatible string.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Check for substrings in deviceID validation check
so that it can support xa bitstreams also.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add PHYLIB and MII dependencies and enable it by default for Microblaze.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When IP is configured with pong buffers, IP is receiving packets to ping
and then to pong buffer and than ping again.
The original logic in the driver remains there that when ping buffer is
free, pong buffer is checked too and return if both are free.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The original logic in the driver was exchanging buffers which are used for
sending packet and tx_ping and tx_pong buffers were exchanged all the
time to ensure that IP has enough time to send the packet out.
Based on this "feature" send function was using nextbuffertouse variable
to save which buffer should be used.
Before this algorithm was called driver checked that there is free
buffer available.
This checking remains in the driver but driver tries to use tx_ping
first if available. If not, tx_pong buffer is used instead.
To reach this code the original condition is met that at least one of the
buffer should be available.
Testing doesn't show any performance drop when this patch is applied.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This flag is not documented anywhere in the latest documentation that's
why this patch removes it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Simplify logic how to find out if there is free TX buffer.
Both buffers are checked all the time that's why logic around order
can be removed.
Also add check when only one buffer is available.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Move to use indirect register access when timeout expires for resetting
TX buffers.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Do initialization via indirect register access.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Use u-boot coding style how to setup and access MDIO bus.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Also add dependency on PHYLIB and MII which is required.
Clean PHYLIB dependency from the driver too.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Rename few functions to fit to the new name convention used by DM.
Suggested-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Saving iobase directly to private structure helps with moving to DM.
There is an option to load iobase from pdata but it is additional load.
Pointer to private structure is available all the time.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Simplify mdio_wait function by passing regs directly.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fix these compilation warning by proper grouping:
In function 'axi_dma_init': drivers/net/xilinx_axi_emac.c:391:7:
warning: suggest parentheses around operand of '!' or change '&' to '&&'
or '!' to '~' [-Wparentheses]
if (!(in_be32(&priv->dmatx->control) |
^
In function 'axiemac_send': drivers/net/xilinx_axi_emac.c:501:21:
warning: suggest parentheses around operand of '!' or change '&' to '&&'
or '!' to '~' [-Wparentheses]
while (timeout && (!in_be32(&priv->dmatx->status) &
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
- Move config option out of board file.
- Remove uartlite address from config file
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Thomas Chou <thomas@wytron.com.tw>
The old mail address will stop working soon.
Update it all the files
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
As atmel_nand_ecc.h is sync with v4.1 kernel, which adds the
PMECC_OOB_RESERVED_BYTES. So use it in the driver.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Also align the open parenthesis.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Since ecc_{strength,step}_ds is introduced in nand_chip structure for
minimum ecc requirements. So we can use them directly and remove our
own get_onfi_ecc_param function.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
During the initialization of PHY the gigabit bit capable is set if the
controller is a GEM. However, for sama5d2 and sama5d4, the GEM is
configured to support only 10/100.
Improperly setting the GBE capability leads to an unresponsive MAC
controller. This patch fixes this behavior allowing using the gmac with
these SoCs.
Suggested-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
[fixed minor checkpatch warning]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Timing issue occurs on eMMC not only when modifying the frequency but
also for all the switch command(CMD6). According to the MMC spec waiting
8 clocks after a switch command would be the thing to do.
This patch allows fixing CPU hang observed when trying to changing the
bus width on a eMMC on SAMA5D4.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Marek Vasut <marex@denx.de> # on DENX MA5D4EV
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Andreas Bießmann <andreas.devel@googlemail.com> # on atngw100
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
[fixed minor checkpatch warning]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
"Fix mvtwsi not working on sun6i and newer sunxi SoCs" includes the following:
@@ -189,7 +200,8 @@ static int twsi_start(struct i2c_adapter *adap, int expected_status)
/* globally set TWSIEN in case it was not */
twsi_control_flags |= MVTWSI_CONTROL_TWSIEN;
/* assert START */
- writel(twsi_control_flags | MVTWSI_CONTROL_START, &twsi->control);
+ twsi_control_flags |= MVTWSI_CONTROL_START | MVTWSI_CONTROL_CLEAR_IFLG;
+ writel(twsi_control_flags, &twsi->control);
/* wait for controller to process START */
return twsi_wait(adap, expected_status);
}
The modification of twsi_control_flags done here was introduced while
merging to fix a line > 80 chars, but twsi_control_flags is a global variable
and should not be modified like this here, this commit fixes this, restoring
mvtwsi functionality.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Previously, AXP818 ALDO support was partially added to Kconfig, but
never enabled in the board file, nor properly set or configured in
Kconfig. The boards continue to work because the AXP818 is designed
to pair with the A83T/H8, and the default voltages match the reference
design's requirements.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
AXP818 provides an array of LDOs to provide power to various peripherals.
None of these regulators are critical.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Instead of one function for each DLDO regulator, make 1 function that
takes an extra "index". Since the control bits for the DLDO regulators
are contiguous, this makes the function very simple. This removes a lot
of duplicate code.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Adds poweroff support for axp209 pmic.
Signed-off-by: Michael van Slingerland <michael@deviousops.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Enabling CONFIG_DISPLAY breaks building for some architectures
(microblaze-generic), so we disable CONFIG_DISPLAY in Kconfig
by default and enable this option in defconfigs. CONFIG_DISPLAY
depends on CONFIG_I2C_EDID, so add and enable it in defconfigs, too.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reported-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
This driver is designed in a generic manner, so clocks should be
handled genericly as well.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Current code compares the return pointer of function
qbman_cena_write_start with NULL. Instead the value of the return
pointer should be compared.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Following commit 61bd2f75, exclude unused DDR controller from
calculating RAM size for SPL boot.
Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
to the desired value after DDR initialization has completed.
When DDR controller is configured to operate in auto-precharge
mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.
Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Zap the rockchip serial compatible string, because rockchip
serial has "snps,dw-apb-uart" compatible string in the dts.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Simon Glass <sjg@chromium.org>
When building katmai, it reports quite a lot
warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
Fix this by casting the dev->iobase with u_long.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
BUILD_BUG_* macros have been defined in several headers. It would
be nice to collect them in include/linux/bug.h like Linux.
This commit is cherry-picking useful macros from include/linux/bug.h
of Linux 4.4.
I did not import BUILD_BUG_ON_MSG() because it would not work if it
is used with include/common.h in U-Boot. I'd like to postpone it
until the root cause (the "error()" macro in include/common.h causes
the name conflict with "__attribute__((error()))") is fixed.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
