mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 23:51:33 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-usb
This commit is contained in:
commit
9c3193f8d0
11 changed files with 3305 additions and 104 deletions
|
@ -199,7 +199,7 @@ static int usb_kbd_translate(struct usb_kbd_pdata *data, unsigned char scancode,
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}
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}
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if ((scancode > 0x1d) && (scancode < 0x3a)) {
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if ((scancode > 0x1d) && (scancode < 0x39)) {
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/* Shift pressed */
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if (modifier & (LEFT_SHIFT | RIGHT_SHIFT))
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keycode = usb_kbd_numkey_shifted[scancode - 0x1e];
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@ -9,3 +9,4 @@ obj-$(CONFIG_USB_ETHER_ASIX) += asix.o
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obj-$(CONFIG_USB_ETHER_ASIX88179) += asix88179.o
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obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o
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obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o
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obj-$(CONFIG_USB_ETHER_RTL8152) += r8152.o r8152_fw.o
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1456
drivers/usb/eth/r8152.c
Normal file
1456
drivers/usb/eth/r8152.c
Normal file
File diff suppressed because it is too large
Load diff
631
drivers/usb/eth/r8152.h
Normal file
631
drivers/usb/eth/r8152.h
Normal file
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@ -0,0 +1,631 @@
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/*
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* Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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*/
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#ifndef _RTL8152_ETH_H
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#define _RTL8152_ETH_H
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#define R8152_BASE_NAME "r8152"
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#define PLA_IDR 0xc000
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#define PLA_RCR 0xc010
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#define PLA_RMS 0xc016
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#define PLA_RXFIFO_CTRL0 0xc0a0
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#define PLA_RXFIFO_CTRL1 0xc0a4
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#define PLA_RXFIFO_CTRL2 0xc0a8
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#define PLA_DMY_REG0 0xc0b0
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#define PLA_FMC 0xc0b4
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#define PLA_CFG_WOL 0xc0b6
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#define PLA_TEREDO_CFG 0xc0bc
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#define PLA_MAR 0xcd00
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#define PLA_BACKUP 0xd000
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#define PAL_BDC_CR 0xd1a0
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#define PLA_TEREDO_TIMER 0xd2cc
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#define PLA_REALWOW_TIMER 0xd2e8
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#define PLA_LEDSEL 0xdd90
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#define PLA_LED_FEATURE 0xdd92
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#define PLA_PHYAR 0xde00
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#define PLA_BOOT_CTRL 0xe004
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#define PLA_GPHY_INTR_IMR 0xe022
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#define PLA_EEE_CR 0xe040
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#define PLA_EEEP_CR 0xe080
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#define PLA_MAC_PWR_CTRL 0xe0c0
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#define PLA_MAC_PWR_CTRL2 0xe0ca
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#define PLA_MAC_PWR_CTRL3 0xe0cc
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#define PLA_MAC_PWR_CTRL4 0xe0ce
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#define PLA_WDT6_CTRL 0xe428
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#define PLA_TCR0 0xe610
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#define PLA_TCR1 0xe612
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#define PLA_MTPS 0xe615
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#define PLA_TXFIFO_CTRL 0xe618
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#define PLA_RSTTALLY 0xe800
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#define BIST_CTRL 0xe810
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#define PLA_CR 0xe813
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#define PLA_CRWECR 0xe81c
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#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
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#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
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#define PLA_CONFIG5 0xe822
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#define PLA_PHY_PWR 0xe84c
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#define PLA_OOB_CTRL 0xe84f
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#define PLA_CPCR 0xe854
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#define PLA_MISC_0 0xe858
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#define PLA_MISC_1 0xe85a
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#define PLA_OCP_GPHY_BASE 0xe86c
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#define PLA_TALLYCNT 0xe890
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#define PLA_SFF_STS_7 0xe8de
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#define PLA_PHYSTATUS 0xe908
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#define PLA_BP_BA 0xfc26
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#define PLA_BP_0 0xfc28
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#define PLA_BP_1 0xfc2a
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#define PLA_BP_2 0xfc2c
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#define PLA_BP_3 0xfc2e
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#define PLA_BP_4 0xfc30
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#define PLA_BP_5 0xfc32
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#define PLA_BP_6 0xfc34
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#define PLA_BP_7 0xfc36
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#define PLA_BP_EN 0xfc38
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#define USB_USB2PHY 0xb41e
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#define USB_SSPHYLINK2 0xb428
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#define USB_U2P3_CTRL 0xb460
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#define USB_CSR_DUMMY1 0xb464
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#define USB_CSR_DUMMY2 0xb466
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#define USB_DEV_STAT 0xb808
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#define USB_CONNECT_TIMER 0xcbf8
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#define USB_BURST_SIZE 0xcfc0
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#define USB_USB_CTRL 0xd406
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#define USB_PHY_CTRL 0xd408
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#define USB_TX_AGG 0xd40a
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#define USB_RX_BUF_TH 0xd40c
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#define USB_USB_TIMER 0xd428
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#define USB_RX_EARLY_TIMEOUT 0xd42c
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#define USB_RX_EARLY_SIZE 0xd42e
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#define USB_PM_CTRL_STATUS 0xd432
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#define USB_TX_DMA 0xd434
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#define USB_TOLERANCE 0xd490
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#define USB_LPM_CTRL 0xd41a
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#define USB_UPS_CTRL 0xd800
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#define USB_MISC_0 0xd81a
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#define USB_POWER_CUT 0xd80a
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#define USB_AFE_CTRL2 0xd824
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#define USB_WDT11_CTRL 0xe43c
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#define USB_BP_BA 0xfc26
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#define USB_BP_0 0xfc28
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#define USB_BP_1 0xfc2a
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#define USB_BP_2 0xfc2c
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#define USB_BP_3 0xfc2e
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#define USB_BP_4 0xfc30
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#define USB_BP_5 0xfc32
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#define USB_BP_6 0xfc34
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#define USB_BP_7 0xfc36
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#define USB_BP_EN 0xfc38
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||||
/* OCP Registers */
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#define OCP_ALDPS_CONFIG 0x2010
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#define OCP_EEE_CONFIG1 0x2080
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#define OCP_EEE_CONFIG2 0x2092
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#define OCP_EEE_CONFIG3 0x2094
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#define OCP_BASE_MII 0xa400
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#define OCP_EEE_AR 0xa41a
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#define OCP_EEE_DATA 0xa41c
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#define OCP_PHY_STATUS 0xa420
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#define OCP_POWER_CFG 0xa430
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#define OCP_EEE_CFG 0xa432
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#define OCP_SRAM_ADDR 0xa436
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#define OCP_SRAM_DATA 0xa438
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#define OCP_DOWN_SPEED 0xa442
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#define OCP_EEE_ABLE 0xa5c4
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#define OCP_EEE_ADV 0xa5d0
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#define OCP_EEE_LPABLE 0xa5d2
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#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
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#define OCP_ADC_CFG 0xbc06
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||||
/* SRAM Register */
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#define SRAM_LPF_CFG 0x8012
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#define SRAM_10M_AMP1 0x8080
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#define SRAM_10M_AMP2 0x8082
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#define SRAM_IMPEDANCE 0x8084
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||||
/* PLA_RCR */
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#define RCR_AAP 0x00000001
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#define RCR_APM 0x00000002
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#define RCR_AM 0x00000004
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#define RCR_AB 0x00000008
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#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
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||||
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||||
/* PLA_RXFIFO_CTRL0 */
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||||
#define RXFIFO_THR1_NORMAL 0x00080002
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#define RXFIFO_THR1_OOB 0x01800003
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||||
/* PLA_RXFIFO_CTRL1 */
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#define RXFIFO_THR2_FULL 0x00000060
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#define RXFIFO_THR2_HIGH 0x00000038
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#define RXFIFO_THR2_OOB 0x0000004a
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#define RXFIFO_THR2_NORMAL 0x00a0
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/* PLA_RXFIFO_CTRL2 */
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#define RXFIFO_THR3_FULL 0x00000078
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#define RXFIFO_THR3_HIGH 0x00000048
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#define RXFIFO_THR3_OOB 0x0000005a
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#define RXFIFO_THR3_NORMAL 0x0110
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/* PLA_TXFIFO_CTRL */
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#define TXFIFO_THR_NORMAL 0x00400008
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#define TXFIFO_THR_NORMAL2 0x01000008
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/* PLA_DMY_REG0 */
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#define ECM_ALDPS 0x0002
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/* PLA_FMC */
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#define FMC_FCR_MCU_EN 0x0001
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/* PLA_EEEP_CR */
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#define EEEP_CR_EEEP_TX 0x0002
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/* PLA_WDT6_CTRL */
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#define WDT6_SET_MODE 0x0010
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/* PLA_TCR0 */
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#define TCR0_TX_EMPTY 0x0800
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#define TCR0_AUTO_FIFO 0x0080
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/* PLA_TCR1 */
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#define VERSION_MASK 0x7cf0
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/* PLA_MTPS */
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#define MTPS_JUMBO (12 * 1024 / 64)
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#define MTPS_DEFAULT (6 * 1024 / 64)
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/* PLA_RSTTALLY */
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#define TALLY_RESET 0x0001
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/* PLA_CR */
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#define PLA_CR_RST 0x10
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#define PLA_CR_RE 0x08
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#define PLA_CR_TE 0x04
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/* PLA_BIST_CTRL */
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#define BIST_CTRL_SW_RESET (0x10 << 24)
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/* PLA_CRWECR */
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#define CRWECR_NORAML 0x00
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#define CRWECR_CONFIG 0xc0
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/* PLA_OOB_CTRL */
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#define NOW_IS_OOB 0x80
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#define TXFIFO_EMPTY 0x20
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#define RXFIFO_EMPTY 0x10
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#define LINK_LIST_READY 0x02
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#define DIS_MCU_CLROOB 0x01
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#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
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/* PLA_PHY_PWR */
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#define PLA_PHY_PWR_LLR (LINK_LIST_READY << 24)
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#define PLA_PHY_PWR_TXEMP (TXFIFO_EMPTY << 24)
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/* PLA_MISC_1 */
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#define RXDY_GATED_EN 0x0008
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/* PLA_SFF_STS_7 */
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#define RE_INIT_LL 0x8000
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#define MCU_BORW_EN 0x4000
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/* PLA_CPCR */
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#define CPCR_RX_VLAN 0x0040
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/* PLA_CFG_WOL */
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#define MAGIC_EN 0x0001
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/* PLA_TEREDO_CFG */
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#define TEREDO_SEL 0x8000
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#define TEREDO_WAKE_MASK 0x7f00
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#define TEREDO_RS_EVENT_MASK 0x00fe
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#define OOB_TEREDO_EN 0x0001
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/* PAL_BDC_CR */
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#define ALDPS_PROXY_MODE 0x0001
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/* PLA_CONFIG34 */
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#define LINK_ON_WAKE_EN 0x0010
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#define LINK_OFF_WAKE_EN 0x0008
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/* PLA_CONFIG5 */
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#define BWF_EN 0x0040
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#define MWF_EN 0x0020
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#define UWF_EN 0x0010
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#define LAN_WAKE_EN 0x0002
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/* PLA_LED_FEATURE */
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#define LED_MODE_MASK 0x0700
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/* PLA_PHY_PWR */
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#define TX_10M_IDLE_EN 0x0080
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#define PFM_PWM_SWITCH 0x0040
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||||
/* PLA_MAC_PWR_CTRL */
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#define D3_CLK_GATED_EN 0x00004000
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#define MCU_CLK_RATIO 0x07010f07
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#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
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#define ALDPS_SPDWN_RATIO 0x0f87
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/* PLA_MAC_PWR_CTRL2 */
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#define EEE_SPDWN_RATIO 0x8007
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/* PLA_MAC_PWR_CTRL3 */
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#define PKT_AVAIL_SPDWN_EN 0x0100
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#define SUSPEND_SPDWN_EN 0x0004
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#define U1U2_SPDWN_EN 0x0002
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#define L1_SPDWN_EN 0x0001
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/* PLA_MAC_PWR_CTRL4 */
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#define PWRSAVE_SPDWN_EN 0x1000
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#define RXDV_SPDWN_EN 0x0800
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#define TX10MIDLE_EN 0x0100
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#define TP100_SPDWN_EN 0x0020
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#define TP500_SPDWN_EN 0x0010
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#define TP1000_SPDWN_EN 0x0008
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#define EEE_SPDWN_EN 0x0001
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||||
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||||
/* PLA_GPHY_INTR_IMR */
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#define GPHY_STS_MSK 0x0001
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#define SPEED_DOWN_MSK 0x0002
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#define SPDWN_RXDV_MSK 0x0004
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#define SPDWN_LINKCHG_MSK 0x0008
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||||
/* PLA_PHYAR */
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#define PHYAR_FLAG 0x80000000
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||||
/* PLA_EEE_CR */
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#define EEE_RX_EN 0x0001
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#define EEE_TX_EN 0x0002
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||||
/* PLA_BOOT_CTRL */
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||||
#define AUTOLOAD_DONE 0x0002
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||||
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||||
/* USB_USB2PHY */
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#define USB2PHY_SUSPEND 0x0001
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||||
#define USB2PHY_L1 0x0002
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||||
/* USB_SSPHYLINK2 */
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#define pwd_dn_scale_mask 0x3ffe
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#define pwd_dn_scale(x) ((x) << 1)
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||||
/* USB_CSR_DUMMY1 */
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#define DYNAMIC_BURST 0x0001
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/* USB_CSR_DUMMY2 */
|
||||
#define EP4_FULL_FC 0x0001
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||||
|
||||
/* USB_DEV_STAT */
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#define STAT_SPEED_MASK 0x0006
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#define STAT_SPEED_HIGH 0x0000
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#define STAT_SPEED_FULL 0x0002
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||||
|
||||
/* USB_TX_AGG */
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#define TX_AGG_MAX_THRESHOLD 0x03
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|
||||
/* USB_RX_BUF_TH */
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#define RX_THR_SUPPER 0x0c350180
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#define RX_THR_HIGH 0x7a120180
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#define RX_THR_SLOW 0xffff0180
|
||||
|
||||
/* USB_TX_DMA */
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||||
#define TEST_MODE_DISABLE 0x00000001
|
||||
#define TX_SIZE_ADJUST1 0x00000100
|
||||
|
||||
/* USB_UPS_CTRL */
|
||||
#define POWER_CUT 0x0100
|
||||
|
||||
/* USB_PM_CTRL_STATUS */
|
||||
#define RESUME_INDICATE 0x0001
|
||||
|
||||
/* USB_USB_CTRL */
|
||||
#define RX_AGG_DISABLE 0x0010
|
||||
#define RX_ZERO_EN 0x0080
|
||||
|
||||
/* USB_U2P3_CTRL */
|
||||
#define U2P3_ENABLE 0x0001
|
||||
|
||||
/* USB_POWER_CUT */
|
||||
#define PWR_EN 0x0001
|
||||
#define PHASE2_EN 0x0008
|
||||
|
||||
/* USB_MISC_0 */
|
||||
#define PCUT_STATUS 0x0001
|
||||
|
||||
/* USB_RX_EARLY_TIMEOUT */
|
||||
#define COALESCE_SUPER 85000U
|
||||
#define COALESCE_HIGH 250000U
|
||||
#define COALESCE_SLOW 524280U
|
||||
|
||||
/* USB_WDT11_CTRL */
|
||||
#define TIMER11_EN 0x0001
|
||||
|
||||
/* USB_LPM_CTRL */
|
||||
/* bit 4 ~ 5: fifo empty boundary */
|
||||
#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
|
||||
/* bit 2 ~ 3: LMP timer */
|
||||
#define LPM_TIMER_MASK 0x0c
|
||||
#define LPM_TIMER_500MS 0x04 /* 500 ms */
|
||||
#define LPM_TIMER_500US 0x0c /* 500 us */
|
||||
#define ROK_EXIT_LPM 0x02
|
||||
|
||||
/* USB_AFE_CTRL2 */
|
||||
#define SEN_VAL_MASK 0xf800
|
||||
#define SEN_VAL_NORMAL 0xa000
|
||||
#define SEL_RXIDLE 0x0100
|
||||
|
||||
/* OCP_ALDPS_CONFIG */
|
||||
#define ENPWRSAVE 0x8000
|
||||
#define ENPDNPS 0x0200
|
||||
#define LINKENA 0x0100
|
||||
#define DIS_SDSAVE 0x0010
|
||||
|
||||
/* OCP_PHY_STATUS */
|
||||
#define PHY_STAT_MASK 0x0007
|
||||
#define PHY_STAT_LAN_ON 3
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||||
#define PHY_STAT_PWRDN 5
|
||||
|
||||
/* OCP_POWER_CFG */
|
||||
#define EEE_CLKDIV_EN 0x8000
|
||||
#define EN_ALDPS 0x0004
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||||
#define EN_10M_PLLOFF 0x0001
|
||||
|
||||
/* OCP_EEE_CONFIG1 */
|
||||
#define RG_TXLPI_MSK_HFDUP 0x8000
|
||||
#define RG_MATCLR_EN 0x4000
|
||||
#define EEE_10_CAP 0x2000
|
||||
#define EEE_NWAY_EN 0x1000
|
||||
#define TX_QUIET_EN 0x0200
|
||||
#define RX_QUIET_EN 0x0100
|
||||
#define sd_rise_time_mask 0x0070
|
||||
#define sd_rise_time(x) (min((x), 7) << 4) /* bit 4 ~ 6 */
|
||||
#define RG_RXLPI_MSK_HFDUP 0x0008
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||||
#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
|
||||
|
||||
/* OCP_EEE_CONFIG2 */
|
||||
#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
|
||||
#define RG_DACQUIET_EN 0x0400
|
||||
#define RG_LDVQUIET_EN 0x0200
|
||||
#define RG_CKRSEL 0x0020
|
||||
#define RG_EEEPRG_EN 0x0010
|
||||
|
||||
/* OCP_EEE_CONFIG3 */
|
||||
#define fast_snr_mask 0xff80
|
||||
#define fast_snr(x) (min((x), 0x1ff) << 7) /* bit 7 ~ 15 */
|
||||
#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
|
||||
#define MSK_PH 0x0006 /* bit 0 ~ 3 */
|
||||
|
||||
/* OCP_EEE_AR */
|
||||
/* bit[15:14] function */
|
||||
#define FUN_ADDR 0x0000
|
||||
#define FUN_DATA 0x4000
|
||||
/* bit[4:0] device addr */
|
||||
|
||||
/* OCP_EEE_CFG */
|
||||
#define CTAP_SHORT_EN 0x0040
|
||||
#define EEE10_EN 0x0010
|
||||
|
||||
/* OCP_DOWN_SPEED */
|
||||
#define EN_10M_BGOFF 0x0080
|
||||
|
||||
/* OCP_PHY_STATE */
|
||||
#define TXDIS_STATE 0x01
|
||||
#define ABD_STATE 0x02
|
||||
|
||||
/* OCP_ADC_CFG */
|
||||
#define CKADSEL_L 0x0100
|
||||
#define ADC_EN 0x0080
|
||||
#define EN_EMI_L 0x0040
|
||||
|
||||
/* SRAM_LPF_CFG */
|
||||
#define LPF_AUTO_TUNE 0x8000
|
||||
|
||||
/* SRAM_10M_AMP1 */
|
||||
#define GDAC_IB_UPALL 0x0008
|
||||
|
||||
/* SRAM_10M_AMP2 */
|
||||
#define AMP_DN 0x0200
|
||||
|
||||
/* SRAM_IMPEDANCE */
|
||||
#define RX_DRIVING_MASK 0x6000
|
||||
|
||||
#define RTL8152_MAX_TX 4
|
||||
#define RTL8152_MAX_RX 10
|
||||
#define INTBUFSIZE 2
|
||||
#define CRC_SIZE 4
|
||||
#define TX_ALIGN 4
|
||||
#define RX_ALIGN 8
|
||||
|
||||
#define INTR_LINK 0x0004
|
||||
|
||||
#define RTL8152_REQT_READ 0xc0
|
||||
#define RTL8152_REQT_WRITE 0x40
|
||||
#define RTL8152_REQ_GET_REGS 0x05
|
||||
#define RTL8152_REQ_SET_REGS 0x05
|
||||
|
||||
#define BYTE_EN_DWORD 0xff
|
||||
#define BYTE_EN_WORD 0x33
|
||||
#define BYTE_EN_BYTE 0x11
|
||||
#define BYTE_EN_SIX_BYTES 0x3f
|
||||
#define BYTE_EN_START_MASK 0x0f
|
||||
#define BYTE_EN_END_MASK 0xf0
|
||||
|
||||
#define RTL8152_ETH_FRAME_LEN 1514
|
||||
#define RTL8152_AGG_BUF_SZ 2048
|
||||
|
||||
#define RTL8152_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE)
|
||||
#define RTL8153_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE)
|
||||
#define RTL8152_TX_TIMEOUT (5 * HZ)
|
||||
|
||||
#define MCU_TYPE_PLA 0x0100
|
||||
#define MCU_TYPE_USB 0x0000
|
||||
|
||||
/* The forced speed, 10Mb, 100Mb, gigabit. */
|
||||
#define SPEED_10 10
|
||||
#define SPEED_100 100
|
||||
#define SPEED_1000 1000
|
||||
|
||||
#define SPEED_UNKNOWN -1
|
||||
|
||||
/* Duplex, half or full. */
|
||||
#define DUPLEX_HALF 0x00
|
||||
#define DUPLEX_FULL 0x01
|
||||
#define DUPLEX_UNKNOWN 0xff
|
||||
|
||||
/* Enable or disable autonegotiation. */
|
||||
#define AUTONEG_DISABLE 0x00
|
||||
#define AUTONEG_ENABLE 0x01
|
||||
|
||||
/* Generic MII registers. */
|
||||
#define MII_BMCR 0x00 /* Basic mode control register */
|
||||
#define MII_BMSR 0x01 /* Basic mode status register */
|
||||
#define MII_PHYSID1 0x02 /* PHYS ID 1 */
|
||||
#define MII_PHYSID2 0x03 /* PHYS ID 2 */
|
||||
#define MII_ADVERTISE 0x04 /* Advertisement control reg */
|
||||
#define MII_LPA 0x05 /* Link partner ability reg */
|
||||
#define MII_EXPANSION 0x06 /* Expansion register */
|
||||
#define MII_CTRL1000 0x09 /* 1000BASE-T control */
|
||||
#define MII_STAT1000 0x0a /* 1000BASE-T status */
|
||||
#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
|
||||
#define MII_MMD_DATA 0x0e /* MMD Access Data Register */
|
||||
#define MII_ESTATUS 0x0f /* Extended Status */
|
||||
#define MII_DCOUNTER 0x12 /* Disconnect counter */
|
||||
#define MII_FCSCOUNTER 0x13 /* False carrier counter */
|
||||
#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
|
||||
#define MII_RERRCOUNTER 0x15 /* Receive error counter */
|
||||
#define MII_SREVISION 0x16 /* Silicon revision */
|
||||
#define MII_RESV1 0x17 /* Reserved... */
|
||||
#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
|
||||
#define MII_PHYADDR 0x19 /* PHY address */
|
||||
#define MII_RESV2 0x1a /* Reserved... */
|
||||
#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
|
||||
#define MII_NCONFIG 0x1c /* Network interface config */
|
||||
|
||||
#define TIMEOUT_RESOLUTION 50
|
||||
#define PHY_CONNECT_TIMEOUT 5000
|
||||
#define USB_BULK_SEND_TIMEOUT 5000
|
||||
#define USB_BULK_RECV_TIMEOUT 5000
|
||||
#define R8152_WAIT_TIMEOUT 2000
|
||||
|
||||
struct rx_desc {
|
||||
__le32 opts1;
|
||||
#define RD_CRC BIT(15)
|
||||
#define RX_LEN_MASK 0x7fff
|
||||
|
||||
__le32 opts2;
|
||||
#define RD_UDP_CS BIT(23)
|
||||
#define RD_TCP_CS BIT(22)
|
||||
#define RD_IPV6_CS BIT(20)
|
||||
#define RD_IPV4_CS BIT(19)
|
||||
|
||||
__le32 opts3;
|
||||
#define IPF BIT(23) /* IP checksum fail */
|
||||
#define UDPF BIT(22) /* UDP checksum fail */
|
||||
#define TCPF BIT(21) /* TCP checksum fail */
|
||||
#define RX_VLAN_TAG BIT(16)
|
||||
|
||||
__le32 opts4;
|
||||
__le32 opts5;
|
||||
__le32 opts6;
|
||||
};
|
||||
|
||||
struct tx_desc {
|
||||
__le32 opts1;
|
||||
#define TX_FS BIT(31) /* First segment of a packet */
|
||||
#define TX_LS BIT(30) /* Final segment of a packet */
|
||||
#define LGSEND BIT(29)
|
||||
#define GTSENDV4 BIT(28)
|
||||
#define GTSENDV6 BIT(27)
|
||||
#define GTTCPHO_SHIFT 18
|
||||
#define GTTCPHO_MAX 0x7fU
|
||||
#define TX_LEN_MAX 0x3ffffU
|
||||
|
||||
__le32 opts2;
|
||||
#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
|
||||
#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
|
||||
#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
|
||||
#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
|
||||
#define MSS_SHIFT 17
|
||||
#define MSS_MAX 0x7ffU
|
||||
#define TCPHO_SHIFT 17
|
||||
#define TCPHO_MAX 0x7ffU
|
||||
#define TX_VLAN_TAG BIT(16)
|
||||
};
|
||||
|
||||
enum rtl_version {
|
||||
RTL_VER_UNKNOWN = 0,
|
||||
RTL_VER_01,
|
||||
RTL_VER_02,
|
||||
RTL_VER_03,
|
||||
RTL_VER_04,
|
||||
RTL_VER_05,
|
||||
RTL_VER_06,
|
||||
RTL_VER_07,
|
||||
RTL_VER_MAX
|
||||
};
|
||||
|
||||
enum rtl_register_content {
|
||||
_1000bps = 0x10,
|
||||
_100bps = 0x08,
|
||||
_10bps = 0x04,
|
||||
LINK_STATUS = 0x02,
|
||||
FULL_DUP = 0x01,
|
||||
};
|
||||
|
||||
struct r8152 {
|
||||
struct usb_device *udev;
|
||||
struct usb_interface *intf;
|
||||
bool supports_gmii;
|
||||
|
||||
struct rtl_ops {
|
||||
void (*init)(struct r8152 *);
|
||||
int (*enable)(struct r8152 *);
|
||||
void (*disable)(struct r8152 *);
|
||||
void (*up)(struct r8152 *);
|
||||
void (*down)(struct r8152 *);
|
||||
void (*unload)(struct r8152 *);
|
||||
} rtl_ops;
|
||||
|
||||
u32 coalesce;
|
||||
u16 ocp_base;
|
||||
|
||||
u8 version;
|
||||
};
|
||||
|
||||
int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
|
||||
u16 size, void *data, u16 type);
|
||||
int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
|
||||
void *data, u16 type);
|
||||
|
||||
int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data);
|
||||
int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
|
||||
u16 size, void *data);
|
||||
|
||||
int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data);
|
||||
int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
|
||||
u16 size, void *data);
|
||||
|
||||
u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index);
|
||||
void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data);
|
||||
|
||||
u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index);
|
||||
void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data);
|
||||
|
||||
u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index);
|
||||
void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data);
|
||||
|
||||
u16 ocp_reg_read(struct r8152 *tp, u16 addr);
|
||||
void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data);
|
||||
|
||||
void sram_write(struct r8152 *tp, u16 addr, u16 data);
|
||||
|
||||
int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
|
||||
const u32 mask, bool set, unsigned int timeout);
|
||||
|
||||
void r8152b_firmware(struct r8152 *tp);
|
||||
void r8153_firmware(struct r8152 *tp);
|
||||
#endif
|
980
drivers/usb/eth/r8152_fw.c
Normal file
980
drivers/usb/eth/r8152_fw.c
Normal file
|
@ -0,0 +1,980 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <errno.h>
|
||||
#include "r8152.h"
|
||||
|
||||
static u8 r8152b_pla_patch_a[] = {
|
||||
0x08, 0xe0, 0x40, 0xe0, 0x78, 0xe0, 0x85, 0xe0,
|
||||
0x5d, 0xe1, 0xa1, 0xe1, 0xa3, 0xe1, 0xab, 0xe1,
|
||||
0x31, 0xc3, 0x60, 0x72, 0xa0, 0x49, 0x10, 0xf0,
|
||||
0xa4, 0x49, 0x0e, 0xf0, 0x2c, 0xc3, 0x62, 0x72,
|
||||
0x26, 0x70, 0x80, 0x49, 0x05, 0xf0, 0x2f, 0x48,
|
||||
0x62, 0x9a, 0x24, 0x70, 0x60, 0x98, 0x24, 0xc3,
|
||||
0x60, 0x99, 0x23, 0xc3, 0x00, 0xbb, 0x2c, 0x75,
|
||||
0xdc, 0x21, 0xbc, 0x25, 0x04, 0x13, 0x0a, 0xf0,
|
||||
0x03, 0x13, 0x08, 0xf0, 0x02, 0x13, 0x06, 0xf0,
|
||||
0x01, 0x13, 0x04, 0xf0, 0x08, 0x13, 0x02, 0xf0,
|
||||
0x03, 0xe0, 0xd4, 0x49, 0x04, 0xf1, 0x14, 0xc2,
|
||||
0x12, 0xc3, 0x00, 0xbb, 0x12, 0xc3, 0x60, 0x75,
|
||||
0xd0, 0x49, 0x05, 0xf1, 0x50, 0x48, 0x60, 0x9d,
|
||||
0x09, 0xc6, 0x00, 0xbe, 0xd0, 0x48, 0x60, 0x9d,
|
||||
0xf3, 0xe7, 0xc2, 0xc0, 0x38, 0xd2, 0xc6, 0xd2,
|
||||
0x84, 0x17, 0xa2, 0x13, 0x0c, 0x17, 0xbc, 0xc0,
|
||||
0xa2, 0xd1, 0x33, 0xc5, 0xa0, 0x74, 0xc0, 0x49,
|
||||
0x1f, 0xf0, 0x30, 0xc5, 0xa0, 0x73, 0x00, 0x13,
|
||||
0x04, 0xf1, 0xa2, 0x73, 0x00, 0x13, 0x14, 0xf0,
|
||||
0x28, 0xc5, 0xa0, 0x74, 0xc8, 0x49, 0x1b, 0xf1,
|
||||
0x26, 0xc5, 0xa0, 0x76, 0xa2, 0x74, 0x01, 0x06,
|
||||
0x20, 0x37, 0xa0, 0x9e, 0xa2, 0x9c, 0x1e, 0xc5,
|
||||
0xa2, 0x73, 0x23, 0x40, 0x10, 0xf8, 0x04, 0xf3,
|
||||
0xa0, 0x73, 0x33, 0x40, 0x0c, 0xf8, 0x15, 0xc5,
|
||||
0xa0, 0x74, 0x41, 0x48, 0xa0, 0x9c, 0x14, 0xc5,
|
||||
0xa0, 0x76, 0x62, 0x48, 0xe0, 0x48, 0xa0, 0x9e,
|
||||
0x10, 0xc6, 0x00, 0xbe, 0x0a, 0xc5, 0xa0, 0x74,
|
||||
0x48, 0x48, 0xa0, 0x9c, 0x0b, 0xc5, 0x20, 0x1e,
|
||||
0xa0, 0x9e, 0xe5, 0x48, 0xa0, 0x9e, 0xf0, 0xe7,
|
||||
0xbc, 0xc0, 0xc8, 0xd2, 0xcc, 0xd2, 0x28, 0xe4,
|
||||
0x22, 0x02, 0xf0, 0xc0, 0x0b, 0xc0, 0x00, 0x71,
|
||||
0x0a, 0xc0, 0x00, 0x72, 0xa0, 0x49, 0x04, 0xf0,
|
||||
0xa4, 0x49, 0x02, 0xf0, 0x93, 0x48, 0x04, 0xc0,
|
||||
0x00, 0xb8, 0x00, 0xe4, 0xc2, 0xc0, 0x8c, 0x09,
|
||||
0x14, 0xc2, 0x40, 0x73, 0xba, 0x48, 0x40, 0x9b,
|
||||
0x11, 0xc2, 0x40, 0x73, 0xb0, 0x49, 0x17, 0xf0,
|
||||
0xbf, 0x49, 0x03, 0xf1, 0x09, 0xc5, 0x00, 0xbd,
|
||||
0xb1, 0x49, 0x11, 0xf0, 0xb1, 0x48, 0x40, 0x9b,
|
||||
0x02, 0xc2, 0x00, 0xba, 0x82, 0x18, 0x00, 0xa0,
|
||||
0x1e, 0xfc, 0xbc, 0xc0, 0xf0, 0xc0, 0xde, 0xe8,
|
||||
0x00, 0x80, 0x00, 0x60, 0x2c, 0x75, 0xd4, 0x49,
|
||||
0x12, 0xf1, 0x29, 0xe0, 0xf8, 0xc2, 0x46, 0x71,
|
||||
0xf7, 0xc2, 0x40, 0x73, 0xbe, 0x49, 0x03, 0xf1,
|
||||
0xf5, 0xc7, 0x02, 0xe0, 0xf2, 0xc7, 0x4f, 0x30,
|
||||
0x26, 0x62, 0xa1, 0x49, 0xf0, 0xf1, 0x22, 0x72,
|
||||
0xa0, 0x49, 0xed, 0xf1, 0x25, 0x25, 0x18, 0x1f,
|
||||
0x97, 0x30, 0x91, 0x30, 0x36, 0x9a, 0x2c, 0x75,
|
||||
0x32, 0xc3, 0x60, 0x73, 0xb1, 0x49, 0x0d, 0xf1,
|
||||
0xdc, 0x21, 0xbc, 0x25, 0x27, 0xc6, 0xc0, 0x77,
|
||||
0x04, 0x13, 0x18, 0xf0, 0x03, 0x13, 0x19, 0xf0,
|
||||
0x02, 0x13, 0x1a, 0xf0, 0x01, 0x13, 0x1b, 0xf0,
|
||||
0xd4, 0x49, 0x03, 0xf1, 0x1c, 0xc5, 0x00, 0xbd,
|
||||
0xcd, 0xc6, 0xc6, 0x67, 0x2e, 0x75, 0xd7, 0x22,
|
||||
0xdd, 0x26, 0x05, 0x15, 0x1a, 0xf0, 0x14, 0xc6,
|
||||
0x00, 0xbe, 0x13, 0xc5, 0x00, 0xbd, 0x12, 0xc5,
|
||||
0x00, 0xbd, 0xf1, 0x49, 0xfb, 0xf1, 0xef, 0xe7,
|
||||
0xf4, 0x49, 0xfa, 0xf1, 0xec, 0xe7, 0xf3, 0x49,
|
||||
0xf7, 0xf1, 0xe9, 0xe7, 0xf2, 0x49, 0xf4, 0xf1,
|
||||
0xe6, 0xe7, 0xb6, 0xc0, 0x6a, 0x14, 0xac, 0x13,
|
||||
0xd6, 0x13, 0xfa, 0x14, 0xa0, 0xd1, 0x00, 0x00,
|
||||
0xc0, 0x75, 0xd0, 0x49, 0x46, 0xf0, 0x26, 0x72,
|
||||
0xa7, 0x49, 0x43, 0xf0, 0x22, 0x72, 0x25, 0x25,
|
||||
0x20, 0x1f, 0x97, 0x30, 0x91, 0x30, 0x40, 0x73,
|
||||
0xf3, 0xc4, 0x1c, 0x40, 0x04, 0xf0, 0xd7, 0x49,
|
||||
0x05, 0xf1, 0x37, 0xe0, 0x53, 0x48, 0xc0, 0x9d,
|
||||
0x08, 0x02, 0x40, 0x66, 0x64, 0x27, 0x06, 0x16,
|
||||
0x30, 0xf1, 0x46, 0x63, 0x3b, 0x13, 0x2d, 0xf1,
|
||||
0x34, 0x9b, 0x18, 0x1b, 0x93, 0x30, 0x2b, 0xc3,
|
||||
0x10, 0x1c, 0x2b, 0xe8, 0x01, 0x14, 0x25, 0xf1,
|
||||
0x00, 0x1d, 0x26, 0x1a, 0x8a, 0x30, 0x22, 0x73,
|
||||
0xb5, 0x25, 0x0e, 0x0b, 0x00, 0x1c, 0x2c, 0xe8,
|
||||
0x1f, 0xc7, 0x27, 0x40, 0x1a, 0xf1, 0x38, 0xe8,
|
||||
0x32, 0x1f, 0x8f, 0x30, 0x08, 0x1b, 0x24, 0xe8,
|
||||
0x36, 0x72, 0x46, 0x77, 0x00, 0x17, 0x0d, 0xf0,
|
||||
0x13, 0xc3, 0x1f, 0x40, 0x03, 0xf1, 0x00, 0x1f,
|
||||
0x46, 0x9f, 0x44, 0x77, 0x9f, 0x44, 0x5f, 0x44,
|
||||
0x17, 0xe8, 0x0a, 0xc7, 0x27, 0x40, 0x05, 0xf1,
|
||||
0x02, 0xc3, 0x00, 0xbb, 0x50, 0x1a, 0x06, 0x1a,
|
||||
0xff, 0xc7, 0x00, 0xbf, 0xb8, 0xcd, 0xff, 0xff,
|
||||
0x02, 0x0c, 0x54, 0xa5, 0xdc, 0xa5, 0x2f, 0x40,
|
||||
0x05, 0xf1, 0x00, 0x14, 0xfa, 0xf1, 0x01, 0x1c,
|
||||
0x02, 0xe0, 0x00, 0x1c, 0x80, 0xff, 0xb0, 0x49,
|
||||
0x04, 0xf0, 0x01, 0x0b, 0xd3, 0xa1, 0x03, 0xe0,
|
||||
0x02, 0x0b, 0xd3, 0xa5, 0x27, 0x31, 0x20, 0x37,
|
||||
0x02, 0x0b, 0xd3, 0xa5, 0x27, 0x31, 0x20, 0x37,
|
||||
0x00, 0x13, 0xfb, 0xf1, 0x80, 0xff, 0x22, 0x73,
|
||||
0xb5, 0x25, 0x18, 0x1e, 0xde, 0x30, 0xd9, 0x30,
|
||||
0x64, 0x72, 0x11, 0x1e, 0x68, 0x23, 0x16, 0x31,
|
||||
0x80, 0xff, 0xd4, 0x49, 0x28, 0xf0, 0x02, 0xb4,
|
||||
0x2a, 0xc4, 0x00, 0x1d, 0x2e, 0xe8, 0xe0, 0x73,
|
||||
0xb9, 0x21, 0xbd, 0x25, 0x04, 0x13, 0x02, 0xf0,
|
||||
0x1a, 0xe0, 0x22, 0xc4, 0x23, 0xc3, 0x2f, 0xe8,
|
||||
0x23, 0xc3, 0x2d, 0xe8, 0x00, 0x1d, 0x21, 0xe8,
|
||||
0xe2, 0x73, 0xbb, 0x49, 0xfc, 0xf0, 0xe0, 0x73,
|
||||
0xb7, 0x48, 0x03, 0xb4, 0x81, 0x1d, 0x19, 0xe8,
|
||||
0x40, 0x1a, 0x84, 0x1d, 0x16, 0xe8, 0x12, 0xc3,
|
||||
0x1e, 0xe8, 0x03, 0xb0, 0x81, 0x1d, 0x11, 0xe8,
|
||||
0x0e, 0xc3, 0x19, 0xe8, 0x02, 0xb0, 0x06, 0xc7,
|
||||
0x04, 0x1e, 0xe0, 0x9e, 0x02, 0xc6, 0x00, 0xbe,
|
||||
0x22, 0x02, 0x20, 0xe4, 0x04, 0xb8, 0x34, 0xb0,
|
||||
0x00, 0x02, 0x00, 0x03, 0x00, 0x0e, 0x00, 0x0c,
|
||||
0x09, 0xc7, 0xe0, 0x9b, 0xe2, 0x9a, 0xe4, 0x9c,
|
||||
0xe6, 0x8d, 0xe6, 0x76, 0xef, 0x49, 0xfe, 0xf1,
|
||||
0x80, 0xff, 0x08, 0xea, 0x82, 0x1d, 0xf5, 0xef,
|
||||
0x00, 0x1a, 0x88, 0x1d, 0xf2, 0xef, 0xed, 0xc2,
|
||||
0xf0, 0xef, 0x80, 0xff, 0x02, 0xc6, 0x00, 0xbe,
|
||||
0x46, 0x06, 0x08, 0xc2, 0x40, 0x73, 0x3a, 0x48,
|
||||
0x40, 0x9b, 0x06, 0xff, 0x02, 0xc6, 0x00, 0xbe,
|
||||
0x86, 0x17, 0x1e, 0xfc, 0x36, 0xf0, 0x08, 0x1c,
|
||||
0xea, 0x8c, 0xe3, 0x64, 0xc7, 0x49, 0x25, 0xf1,
|
||||
0xe0, 0x75, 0xff, 0x1b, 0xeb, 0x47, 0xff, 0x1b,
|
||||
0x6b, 0x47, 0xe0, 0x9d, 0x15, 0xc3, 0x60, 0x75,
|
||||
0xd8, 0x49, 0x04, 0xf0, 0x81, 0x1d, 0xe2, 0x8d,
|
||||
0x05, 0xe0, 0xe2, 0x63, 0x81, 0x1d, 0xdd, 0x47,
|
||||
0xe2, 0x8b, 0x0b, 0xc3, 0x00, 0x1d, 0x61, 0x8d,
|
||||
0x3c, 0x03, 0x60, 0x75, 0xd8, 0x49, 0x06, 0xf1,
|
||||
0xdf, 0x48, 0x61, 0x95, 0x16, 0xe0, 0x4e, 0xe8,
|
||||
0x12, 0xe8, 0x21, 0xc5, 0xa0, 0x73, 0xb0, 0x49,
|
||||
0x03, 0xf0, 0x31, 0x48, 0xa0, 0x9b, 0x0d, 0xe0,
|
||||
0xc0, 0x49, 0x0b, 0xf1, 0xe2, 0x63, 0x7e, 0x1d,
|
||||
0xdd, 0x46, 0xe2, 0x8b, 0xe0, 0x75, 0x83, 0x1b,
|
||||
0xeb, 0x46, 0xfe, 0x1b, 0x6b, 0x46, 0xe0, 0x9d,
|
||||
0xe4, 0x49, 0x11, 0xf0, 0x10, 0x1d, 0xea, 0x8d,
|
||||
0xe3, 0x64, 0xc6, 0x49, 0x09, 0xf1, 0x07, 0xc5,
|
||||
0xa0, 0x73, 0xb1, 0x48, 0xa0, 0x9b, 0x02, 0xc5,
|
||||
0x00, 0xbd, 0xe6, 0x04, 0xa0, 0xd1, 0x02, 0xc5,
|
||||
0x00, 0xbd, 0xfe, 0x04, 0x02, 0xc5, 0x00, 0xbd,
|
||||
0x30, 0x05, 0x00, 0x00 };
|
||||
|
||||
static u16 r8152b_ram_code1[] = {
|
||||
0x9700, 0x7fe0, 0x4c00, 0x4007, 0x4400, 0x4800, 0x7c1f, 0x4c00,
|
||||
0x5310, 0x6000, 0x7c07, 0x6800, 0x673e, 0x0000, 0x0000, 0x571f,
|
||||
0x5ffb, 0xaa05, 0x5b58, 0x7d80, 0x6100, 0x3019, 0x5b64, 0x7d80,
|
||||
0x6080, 0xa6f8, 0xdcdb, 0x0015, 0xb915, 0xb511, 0xd16b, 0x000f,
|
||||
0xb40f, 0xd06b, 0x000d, 0xb206, 0x7c01, 0x5800, 0x7c04, 0x5c00,
|
||||
0x3011, 0x7c01, 0x5801, 0x7c04, 0x5c04, 0x3019, 0x30a5, 0x3127,
|
||||
0x31d5, 0x7fe0, 0x4c60, 0x7c07, 0x6803, 0x7d00, 0x6900, 0x65a0,
|
||||
0x0000, 0x0000, 0xaf03, 0x6015, 0x303e, 0x6017, 0x57e0, 0x580c,
|
||||
0x588c, 0x7fdd, 0x5fa2, 0x4827, 0x7c1f, 0x4c00, 0x7c1f, 0x4c10,
|
||||
0x8400, 0x7c30, 0x6020, 0x48bf, 0x7c1f, 0x4c00, 0x7c1f, 0x4c01,
|
||||
0x7c07, 0x6803, 0xb806, 0x7c08, 0x6800, 0x0000, 0x0000, 0x305c,
|
||||
0x7c08, 0x6808, 0x0000, 0x0000, 0xae06, 0x7c02, 0x5c02, 0x0000,
|
||||
0x0000, 0x3067, 0x8e05, 0x7c02, 0x5c00, 0x0000, 0x0000, 0xad06,
|
||||
0x7c20, 0x5c20, 0x0000, 0x0000, 0x3072, 0x8d05, 0x7c20, 0x5c00,
|
||||
0x0000, 0x0000, 0xa008, 0x7c07, 0x6800, 0xb8db, 0x7c07, 0x6803,
|
||||
0xd9b3, 0x00d7, 0x7fe0, 0x4c80, 0x7c08, 0x6800, 0x0000, 0x0000,
|
||||
0x7c23, 0x5c23, 0x481d, 0x7c1f, 0x4c00, 0x7c1f, 0x4c02, 0x5310,
|
||||
0x81ff, 0x30f5, 0x7fe0, 0x4d00, 0x4832, 0x7c1f, 0x4c00, 0x7c1f,
|
||||
0x4c10, 0x7c08, 0x6000, 0xa49e, 0x7c07, 0x6800, 0xb89b, 0x7c07,
|
||||
0x6803, 0xd9b3, 0x00f9, 0x7fe0, 0x4d20, 0x7e00, 0x6200, 0x3001,
|
||||
0x7fe0, 0x4dc0, 0xd09d, 0x0002, 0xb4fe, 0x7fe0, 0x4d80, 0x7c04,
|
||||
0x6004, 0x7c07, 0x6802, 0x6728, 0x0000, 0x0000, 0x7c08, 0x6000,
|
||||
0x486c, 0x7c1f, 0x4c00, 0x7c1f, 0x4c01, 0x9503, 0x7e00, 0x6200,
|
||||
0x571f, 0x5fbb, 0xaa05, 0x5b58, 0x7d80, 0x6100, 0x30c2, 0x5b64,
|
||||
0x7d80, 0x6080, 0xcdab, 0x0063, 0xcd8d, 0x0061, 0xd96b, 0x005f,
|
||||
0xd0a0, 0x00d7, 0xcba0, 0x0003, 0x80ec, 0x30cf, 0x30dc, 0x7fe0,
|
||||
0x4ce0, 0x4832, 0x7c1f, 0x4c00, 0x7c1f, 0x4c08, 0x7c08, 0x6008,
|
||||
0x8300, 0xb902, 0x30a5, 0x308a, 0x7fe0, 0x4da0, 0x65a8, 0x0000,
|
||||
0x0000, 0x56a0, 0x590c, 0x7ffd, 0x5fa2, 0xae06, 0x7c02, 0x5c02,
|
||||
0x0000, 0x0000, 0x30f0, 0x8e05, 0x7c02, 0x5c00, 0x0000, 0x0000,
|
||||
0xcba4, 0x0004, 0xcd8d, 0x0002, 0x80f1, 0x7fe0, 0x4ca0, 0x7c08,
|
||||
0x6408, 0x0000, 0x0000, 0x7d00, 0x6800, 0xb603, 0x7c10, 0x6010,
|
||||
0x7d1f, 0x551f, 0x5fb3, 0xaa07, 0x7c80, 0x5800, 0x5b58, 0x7d80,
|
||||
0x6100, 0x310f, 0x7c80, 0x5800, 0x5b64, 0x7d80, 0x6080, 0x4827,
|
||||
0x7c1f, 0x4c00, 0x7c1f, 0x4c10, 0x8400, 0x7c10, 0x6000, 0x7fe0,
|
||||
0x4cc0, 0x5fbb, 0x4824, 0x7c1f, 0x4c00, 0x7c1f, 0x4c04, 0x8200,
|
||||
0x7ce0, 0x5400, 0x6728, 0x0000, 0x0000, 0x30cf, 0x3001, 0x7fe0,
|
||||
0x4e00, 0x4007, 0x4400, 0x5310, 0x7c07, 0x6800, 0x673e, 0x0000,
|
||||
0x0000, 0x570f, 0x5fff, 0xaa05, 0x585b, 0x7d80, 0x6100, 0x313b,
|
||||
0x5867, 0x7d80, 0x6080, 0x9403, 0x7e00, 0x6200, 0xcda3, 0x00e7,
|
||||
0xcd85, 0x00e5, 0xd96b, 0x00e3, 0x96e3, 0x7c07, 0x6800, 0x673e,
|
||||
0x0000, 0x0000, 0x7fe0, 0x4e20, 0x96db, 0x8b04, 0x7c08, 0x5008,
|
||||
0xab03, 0x7c08, 0x5000, 0x7c07, 0x6801, 0x677e, 0x0000, 0x0000,
|
||||
0xdb7c, 0x00ec, 0x0000, 0x7fe1, 0x4f40, 0x4837, 0x4418, 0x41c7,
|
||||
0x7fe0, 0x4e40, 0x7c40, 0x5400, 0x7c1f, 0x4c01, 0x7c1f, 0x4c01,
|
||||
0x8fbf, 0xd2a0, 0x004b, 0x9204, 0xa042, 0x3168, 0x3127, 0x7fe1,
|
||||
0x4f60, 0x489c, 0x4628, 0x7fe0, 0x4e60, 0x7e28, 0x4628, 0x7c40,
|
||||
0x5400, 0x7c01, 0x5800, 0x7c04, 0x5c00, 0x41e8, 0x7c1f, 0x4c01,
|
||||
0x7c1f, 0x4c01, 0x8fa5, 0xb241, 0xa02a, 0x3182, 0x7fe0, 0x4ea0,
|
||||
0x7c02, 0x4402, 0x4448, 0x4894, 0x7c1f, 0x4c01, 0x7c1f, 0x4c03,
|
||||
0x4824, 0x7c1f, 0x4c07, 0x41ef, 0x41ff, 0x4891, 0x7c1f, 0x4c07,
|
||||
0x7c1f, 0x4c17, 0x8400, 0x8ef8, 0x41c7, 0x8f8a, 0x92d5, 0xa10f,
|
||||
0xd480, 0x0008, 0xd580, 0x00b8, 0xa202, 0x319d, 0x7c04, 0x4404,
|
||||
0x319d, 0xd484, 0x00f3, 0xd484, 0x00f1, 0x3127, 0x7fe0, 0x4ee0,
|
||||
0x7c40, 0x5400, 0x4488, 0x41cf, 0x3127, 0x7fe0, 0x4ec0, 0x48f3,
|
||||
0x7c1f, 0x4c01, 0x7c1f, 0x4c09, 0x4508, 0x41c7, 0x8fb0, 0xd218,
|
||||
0x00ae, 0xd2a4, 0x009e, 0x31be, 0x7fe0, 0x4e80, 0x4832, 0x7c1f,
|
||||
0x4c01, 0x7c1f, 0x4c11, 0x4428, 0x7c40, 0x5440, 0x7c01, 0x5801,
|
||||
0x7c04, 0x5c04, 0x41e8, 0xa4b3, 0x31d3, 0x7fe0, 0x4f20, 0x7c07,
|
||||
0x6800, 0x673e, 0x0000, 0x0000, 0x570f, 0x5fff, 0xaa04, 0x585b,
|
||||
0x6100, 0x31e4, 0x5867, 0x6080, 0xbcf1, 0x3001 };
|
||||
|
||||
static u16 r8152b_pla_patch_a_bp[] = {
|
||||
0xfc26, 0x8000, 0xfc28, 0x170b, 0xfc2a, 0x01e1, 0xfc2c, 0x0989,
|
||||
0xfc2e, 0x1349, 0xfc30, 0x01b7, 0xfc32, 0x061d, 0xe422, 0x0020,
|
||||
0xe420, 0x0018, 0xfc34, 0x1785, 0xfc36, 0x047b };
|
||||
|
||||
static u8 r8152b_pla_patch_a2[] = {
|
||||
0x08, 0xe0, 0x1a, 0xe0, 0xf2, 0xe0, 0xfa, 0xe0,
|
||||
0x32, 0xe1, 0x34, 0xe1, 0x36, 0xe1, 0x38, 0xe1,
|
||||
0x2c, 0x75, 0xdc, 0x21, 0xbc, 0x25, 0x04, 0x13,
|
||||
0x0b, 0xf0, 0x03, 0x13, 0x09, 0xf0, 0x02, 0x13,
|
||||
0x07, 0xf0, 0x01, 0x13, 0x05, 0xf0, 0x08, 0x13,
|
||||
0x03, 0xf0, 0x04, 0xc3, 0x00, 0xbb, 0x03, 0xc3,
|
||||
0x00, 0xbb, 0xd2, 0x17, 0xbc, 0x17, 0x14, 0xc2,
|
||||
0x40, 0x73, 0xba, 0x48, 0x40, 0x9b, 0x11, 0xc2,
|
||||
0x40, 0x73, 0xb0, 0x49, 0x17, 0xf0, 0xbf, 0x49,
|
||||
0x03, 0xf1, 0x09, 0xc5, 0x00, 0xbd, 0xb1, 0x49,
|
||||
0x11, 0xf0, 0xb1, 0x48, 0x40, 0x9b, 0x02, 0xc2,
|
||||
0x00, 0xba, 0x4e, 0x19, 0x00, 0xa0, 0x1e, 0xfc,
|
||||
0xbc, 0xc0, 0xf0, 0xc0, 0xde, 0xe8, 0x00, 0x80,
|
||||
0x00, 0x60, 0x2c, 0x75, 0xd4, 0x49, 0x12, 0xf1,
|
||||
0x29, 0xe0, 0xf8, 0xc2, 0x46, 0x71, 0xf7, 0xc2,
|
||||
0x40, 0x73, 0xbe, 0x49, 0x03, 0xf1, 0xf5, 0xc7,
|
||||
0x02, 0xe0, 0xf2, 0xc7, 0x4f, 0x30, 0x26, 0x62,
|
||||
0xa1, 0x49, 0xf0, 0xf1, 0x22, 0x72, 0xa0, 0x49,
|
||||
0xed, 0xf1, 0x25, 0x25, 0x18, 0x1f, 0x97, 0x30,
|
||||
0x91, 0x30, 0x36, 0x9a, 0x2c, 0x75, 0x32, 0xc3,
|
||||
0x60, 0x73, 0xb1, 0x49, 0x0d, 0xf1, 0xdc, 0x21,
|
||||
0xbc, 0x25, 0x27, 0xc6, 0xc0, 0x77, 0x04, 0x13,
|
||||
0x18, 0xf0, 0x03, 0x13, 0x19, 0xf0, 0x02, 0x13,
|
||||
0x1a, 0xf0, 0x01, 0x13, 0x1b, 0xf0, 0xd4, 0x49,
|
||||
0x03, 0xf1, 0x1c, 0xc5, 0x00, 0xbd, 0xcd, 0xc6,
|
||||
0xc6, 0x67, 0x2e, 0x75, 0xd7, 0x22, 0xdd, 0x26,
|
||||
0x05, 0x15, 0x1a, 0xf0, 0x14, 0xc6, 0x00, 0xbe,
|
||||
0x13, 0xc5, 0x00, 0xbd, 0x12, 0xc5, 0x00, 0xbd,
|
||||
0xf1, 0x49, 0xfb, 0xf1, 0xef, 0xe7, 0xf4, 0x49,
|
||||
0xfa, 0xf1, 0xec, 0xe7, 0xf3, 0x49, 0xf7, 0xf1,
|
||||
0xe9, 0xe7, 0xf2, 0x49, 0xf4, 0xf1, 0xe6, 0xe7,
|
||||
0xb6, 0xc0, 0xf6, 0x14, 0x36, 0x14, 0x62, 0x14,
|
||||
0x86, 0x15, 0xa0, 0xd1, 0x00, 0x00, 0xc0, 0x75,
|
||||
0xd0, 0x49, 0x46, 0xf0, 0x26, 0x72, 0xa7, 0x49,
|
||||
0x43, 0xf0, 0x22, 0x72, 0x25, 0x25, 0x20, 0x1f,
|
||||
0x97, 0x30, 0x91, 0x30, 0x40, 0x73, 0xf3, 0xc4,
|
||||
0x1c, 0x40, 0x04, 0xf0, 0xd7, 0x49, 0x05, 0xf1,
|
||||
0x37, 0xe0, 0x53, 0x48, 0xc0, 0x9d, 0x08, 0x02,
|
||||
0x40, 0x66, 0x64, 0x27, 0x06, 0x16, 0x30, 0xf1,
|
||||
0x46, 0x63, 0x3b, 0x13, 0x2d, 0xf1, 0x34, 0x9b,
|
||||
0x18, 0x1b, 0x93, 0x30, 0x2b, 0xc3, 0x10, 0x1c,
|
||||
0x2b, 0xe8, 0x01, 0x14, 0x25, 0xf1, 0x00, 0x1d,
|
||||
0x26, 0x1a, 0x8a, 0x30, 0x22, 0x73, 0xb5, 0x25,
|
||||
0x0e, 0x0b, 0x00, 0x1c, 0x2c, 0xe8, 0x1f, 0xc7,
|
||||
0x27, 0x40, 0x1a, 0xf1, 0x38, 0xe8, 0x32, 0x1f,
|
||||
0x8f, 0x30, 0x08, 0x1b, 0x24, 0xe8, 0x36, 0x72,
|
||||
0x46, 0x77, 0x00, 0x17, 0x0d, 0xf0, 0x13, 0xc3,
|
||||
0x1f, 0x40, 0x03, 0xf1, 0x00, 0x1f, 0x46, 0x9f,
|
||||
0x44, 0x77, 0x9f, 0x44, 0x5f, 0x44, 0x17, 0xe8,
|
||||
0x0a, 0xc7, 0x27, 0x40, 0x05, 0xf1, 0x02, 0xc3,
|
||||
0x00, 0xbb, 0x1c, 0x1b, 0xd2, 0x1a, 0xff, 0xc7,
|
||||
0x00, 0xbf, 0xb8, 0xcd, 0xff, 0xff, 0x02, 0x0c,
|
||||
0x54, 0xa5, 0xdc, 0xa5, 0x2f, 0x40, 0x05, 0xf1,
|
||||
0x00, 0x14, 0xfa, 0xf1, 0x01, 0x1c, 0x02, 0xe0,
|
||||
0x00, 0x1c, 0x80, 0xff, 0xb0, 0x49, 0x04, 0xf0,
|
||||
0x01, 0x0b, 0xd3, 0xa1, 0x03, 0xe0, 0x02, 0x0b,
|
||||
0xd3, 0xa5, 0x27, 0x31, 0x20, 0x37, 0x02, 0x0b,
|
||||
0xd3, 0xa5, 0x27, 0x31, 0x20, 0x37, 0x00, 0x13,
|
||||
0xfb, 0xf1, 0x80, 0xff, 0x22, 0x73, 0xb5, 0x25,
|
||||
0x18, 0x1e, 0xde, 0x30, 0xd9, 0x30, 0x64, 0x72,
|
||||
0x11, 0x1e, 0x68, 0x23, 0x16, 0x31, 0x80, 0xff,
|
||||
0x08, 0xc2, 0x40, 0x73, 0x3a, 0x48, 0x40, 0x9b,
|
||||
0x06, 0xff, 0x02, 0xc6, 0x00, 0xbe, 0x4e, 0x18,
|
||||
0x1e, 0xfc, 0x33, 0xc5, 0xa0, 0x74, 0xc0, 0x49,
|
||||
0x1f, 0xf0, 0x30, 0xc5, 0xa0, 0x73, 0x00, 0x13,
|
||||
0x04, 0xf1, 0xa2, 0x73, 0x00, 0x13, 0x14, 0xf0,
|
||||
0x28, 0xc5, 0xa0, 0x74, 0xc8, 0x49, 0x1b, 0xf1,
|
||||
0x26, 0xc5, 0xa0, 0x76, 0xa2, 0x74, 0x01, 0x06,
|
||||
0x20, 0x37, 0xa0, 0x9e, 0xa2, 0x9c, 0x1e, 0xc5,
|
||||
0xa2, 0x73, 0x23, 0x40, 0x10, 0xf8, 0x04, 0xf3,
|
||||
0xa0, 0x73, 0x33, 0x40, 0x0c, 0xf8, 0x15, 0xc5,
|
||||
0xa0, 0x74, 0x41, 0x48, 0xa0, 0x9c, 0x14, 0xc5,
|
||||
0xa0, 0x76, 0x62, 0x48, 0xe0, 0x48, 0xa0, 0x9e,
|
||||
0x10, 0xc6, 0x00, 0xbe, 0x0a, 0xc5, 0xa0, 0x74,
|
||||
0x48, 0x48, 0xa0, 0x9c, 0x0b, 0xc5, 0x20, 0x1e,
|
||||
0xa0, 0x9e, 0xe5, 0x48, 0xa0, 0x9e, 0xf0, 0xe7,
|
||||
0xbc, 0xc0, 0xc8, 0xd2, 0xcc, 0xd2, 0x28, 0xe4,
|
||||
0x22, 0x02, 0xf0, 0xc0, 0x02, 0xc6, 0x00, 0xbe,
|
||||
0x00, 0x00, 0x02, 0xc6, 0x00, 0xbe, 0x00, 0x00,
|
||||
0x02, 0xc6, 0x00, 0xbe, 0x00, 0x00, 0x02, 0xc6,
|
||||
0x00, 0xbe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
|
||||
|
||||
static u16 r8152b_pla_patch_a2_bp[] = {
|
||||
0xfc28, 0x8000, 0xfc28, 0x17a5, 0xfc2a, 0x13ad,
|
||||
0xfc2c, 0x184d, 0xfc2e, 0x01e1 };
|
||||
|
||||
static u16 r8153_ram_code_a[] = {
|
||||
0xE86C, 0xA000, 0xB436, 0xB820, 0xB438, 0x0290, 0xB436, 0xA012,
|
||||
0xB438, 0x0000, 0xB436, 0xA014, 0xB438, 0x2c04, 0xB438, 0x2c18,
|
||||
0xB438, 0x2c45, 0xB438, 0x2c45, 0xB438, 0xd502, 0xB438, 0x8301,
|
||||
0xB438, 0x8306, 0xB438, 0xd500, 0xB438, 0x8208, 0xB438, 0xd501,
|
||||
0xB438, 0xe018, 0xB438, 0x0308, 0xB438, 0x60f2, 0xB438, 0x8404,
|
||||
0xB438, 0x607d, 0xB438, 0xc117, 0xB438, 0x2c16, 0xB438, 0xc116,
|
||||
0xB438, 0x2c16, 0xB438, 0x607d, 0xB438, 0xc117, 0xB438, 0xa404,
|
||||
0xB438, 0xd500, 0xB438, 0x0800, 0xB438, 0xd501, 0xB438, 0x62d2,
|
||||
0xB438, 0x615d, 0xB438, 0xc115, 0xB438, 0xa404, 0xB438, 0xc307,
|
||||
0xB438, 0xd502, 0xB438, 0x8301, 0xB438, 0x8306, 0xB438, 0xd500,
|
||||
0xB438, 0x8208, 0xB438, 0x2c42, 0xB438, 0xc114, 0xB438, 0x8404,
|
||||
0xB438, 0xc317, 0xB438, 0xd701, 0xB438, 0x435d, 0xB438, 0xd500,
|
||||
0xB438, 0xa208, 0xB438, 0xd502, 0xB438, 0xa306, 0xB438, 0xa301,
|
||||
0xB438, 0x2c42, 0xB438, 0x8404, 0xB438, 0x613d, 0xB438, 0xc115,
|
||||
0xB438, 0xc307, 0xB438, 0xd502, 0xB438, 0x8301, 0xB438, 0x8306,
|
||||
0xB438, 0xd500, 0xB438, 0x8208, 0xB438, 0x2c42, 0xB438, 0xc114,
|
||||
0xB438, 0xc317, 0xB438, 0xd701, 0xB438, 0x40dd, 0xB438, 0xd500,
|
||||
0xB438, 0xa208, 0xB438, 0xd502, 0xB438, 0xa306, 0xB438, 0xa301,
|
||||
0xB438, 0xd500, 0xB438, 0xd702, 0xB438, 0x0800, 0xB436, 0xA01A,
|
||||
0xB438, 0x0000, 0xB436, 0xA006, 0xB438, 0x0fff, 0xB436, 0xA004,
|
||||
0xB438, 0x0fff, 0xB436, 0xA002, 0xB438, 0x05a3, 0xB436, 0xA000,
|
||||
0xB438, 0x3591, 0xB436, 0xB820, 0xB438, 0x0210 };
|
||||
|
||||
static u8 r8153_usb_patch_c[] = {
|
||||
0x08, 0xe0, 0x0a, 0xe0, 0x14, 0xe0, 0x2e, 0xe0,
|
||||
0x37, 0xe0, 0x3e, 0xe0, 0x6d, 0xe0, 0x78, 0xe0,
|
||||
0x02, 0xc5, 0x00, 0xbd, 0x38, 0x3b, 0xdb, 0x49,
|
||||
0x04, 0xf1, 0x06, 0xc3, 0x00, 0xbb, 0x5a, 0x02,
|
||||
0x05, 0xc4, 0x03, 0xc3, 0x00, 0xbb, 0xa4, 0x04,
|
||||
0x7e, 0x02, 0x30, 0xd4, 0x30, 0x18, 0x18, 0xc1,
|
||||
0x0c, 0xe8, 0x17, 0xc6, 0xc7, 0x65, 0xd0, 0x49,
|
||||
0x05, 0xf0, 0x32, 0x48, 0x02, 0xc2, 0x00, 0xba,
|
||||
0x3e, 0x16, 0x02, 0xc2, 0x00, 0xba, 0x48, 0x16,
|
||||
0x02, 0xb4, 0x09, 0xc2, 0x40, 0x99, 0x0e, 0x48,
|
||||
0x42, 0x98, 0x42, 0x70, 0x8e, 0x49, 0xfe, 0xf1,
|
||||
0x02, 0xb0, 0x80, 0xff, 0xc0, 0xd4, 0xe4, 0x40,
|
||||
0x20, 0xd4, 0xb0, 0x49, 0x04, 0xf0, 0x30, 0x18,
|
||||
0x06, 0xc1, 0xef, 0xef, 0xfa, 0xc7, 0x02, 0xc0,
|
||||
0x00, 0xb8, 0xd0, 0x10, 0xe4, 0x4b, 0x07, 0xc3,
|
||||
0x70, 0x61, 0x12, 0x48, 0x70, 0x89, 0x02, 0xc3,
|
||||
0x00, 0xbb, 0x9c, 0x15, 0x20, 0xd4, 0x2b, 0xc5,
|
||||
0xa0, 0x77, 0x00, 0x1c, 0xa0, 0x9c, 0x28, 0xc5,
|
||||
0xa0, 0x64, 0xc0, 0x48, 0xc1, 0x48, 0xc2, 0x48,
|
||||
0xa0, 0x8c, 0xb1, 0x64, 0xc0, 0x48, 0xb1, 0x8c,
|
||||
0x20, 0xc5, 0xa0, 0x64, 0x40, 0x48, 0x41, 0x48,
|
||||
0xc2, 0x48, 0xa0, 0x8c, 0x19, 0xc5, 0xa4, 0x64,
|
||||
0x44, 0x48, 0xa4, 0x8c, 0xb1, 0x64, 0x40, 0x48,
|
||||
0xb1, 0x8c, 0x14, 0xc4, 0x80, 0x73, 0x13, 0xc4,
|
||||
0x82, 0x9b, 0x11, 0x1b, 0x80, 0x9b, 0x0c, 0xc5,
|
||||
0xa0, 0x64, 0x40, 0x48, 0x41, 0x48, 0x42, 0x48,
|
||||
0xa0, 0x8c, 0x05, 0xc5, 0xa0, 0x9f, 0x02, 0xc5,
|
||||
0x00, 0xbd, 0x6c, 0x3a, 0x1e, 0xfc, 0x10, 0xd8,
|
||||
0x86, 0xd4, 0xf8, 0xcb, 0x20, 0xe4, 0x0a, 0xc0,
|
||||
0x16, 0x61, 0x91, 0x48, 0x16, 0x89, 0x07, 0xc0,
|
||||
0x11, 0x19, 0x0c, 0x89, 0x02, 0xc1, 0x00, 0xb9,
|
||||
0x02, 0x06, 0x00, 0xd4, 0x40, 0xb4, 0xfe, 0xc0,
|
||||
0x16, 0x61, 0x91, 0x48, 0x16, 0x89, 0xfb, 0xc0,
|
||||
0x11, 0x19, 0x0c, 0x89, 0x02, 0xc1, 0x00, 0xb9,
|
||||
0xd2, 0x05, 0x00, 0x00 };
|
||||
|
||||
static u16 r8153_usb_patch_c_bp[] = {
|
||||
0xfc26, 0xa000, 0xfc28, 0x3b34, 0xfc2a, 0x027c, 0xfc2c, 0x162c,
|
||||
0xfc2e, 0x10ce, 0xfc30, 0x0000, 0xfc32, 0x3a28, 0xfc34, 0x05f8,
|
||||
0xfc36, 0x05c8 };
|
||||
|
||||
static u8 r8153_pla_patch_c[] = {
|
||||
0x08, 0xe0, 0xea, 0xe0, 0xf2, 0xe0, 0x04, 0xe1,
|
||||
0x06, 0xe1, 0x08, 0xe1, 0x40, 0xe1, 0xf1, 0xe1,
|
||||
0x14, 0xc2, 0x40, 0x73, 0xba, 0x48, 0x40, 0x9b,
|
||||
0x11, 0xc2, 0x40, 0x73, 0xb0, 0x49, 0x17, 0xf0,
|
||||
0xbf, 0x49, 0x03, 0xf1, 0x09, 0xc5, 0x00, 0xbd,
|
||||
0xb1, 0x49, 0x11, 0xf0, 0xb1, 0x48, 0x40, 0x9b,
|
||||
0x02, 0xc2, 0x00, 0xba, 0xde, 0x18, 0x00, 0xe0,
|
||||
0x1e, 0xfc, 0xbc, 0xc0, 0xf0, 0xc0, 0xde, 0xe8,
|
||||
0x00, 0x80, 0x00, 0x20, 0x2c, 0x75, 0xd4, 0x49,
|
||||
0x12, 0xf1, 0x32, 0xe0, 0xf8, 0xc2, 0x46, 0x71,
|
||||
0xf7, 0xc2, 0x40, 0x73, 0xbe, 0x49, 0x03, 0xf1,
|
||||
0xf5, 0xc7, 0x02, 0xe0, 0xf2, 0xc7, 0x4f, 0x30,
|
||||
0x26, 0x62, 0xa1, 0x49, 0xf0, 0xf1, 0x22, 0x72,
|
||||
0xa0, 0x49, 0xed, 0xf1, 0x25, 0x25, 0x18, 0x1f,
|
||||
0x97, 0x30, 0x91, 0x30, 0x36, 0x9a, 0x2c, 0x75,
|
||||
0x3c, 0xc3, 0x60, 0x73, 0xb1, 0x49, 0x0d, 0xf1,
|
||||
0xdc, 0x21, 0xbc, 0x25, 0x30, 0xc6, 0xc0, 0x77,
|
||||
0x04, 0x13, 0x21, 0xf0, 0x03, 0x13, 0x22, 0xf0,
|
||||
0x02, 0x13, 0x23, 0xf0, 0x01, 0x13, 0x24, 0xf0,
|
||||
0x08, 0x13, 0x08, 0xf1, 0x2e, 0x73, 0xba, 0x21,
|
||||
0xbd, 0x25, 0x05, 0x13, 0x03, 0xf1, 0x24, 0xc5,
|
||||
0x00, 0xbd, 0xd4, 0x49, 0x03, 0xf1, 0x1c, 0xc5,
|
||||
0x00, 0xbd, 0xc4, 0xc6, 0xc6, 0x67, 0x2e, 0x75,
|
||||
0xd7, 0x22, 0xdd, 0x26, 0x05, 0x15, 0x1b, 0xf0,
|
||||
0x14, 0xc6, 0x00, 0xbe, 0x13, 0xc5, 0x00, 0xbd,
|
||||
0x12, 0xc5, 0x00, 0xbd, 0xf1, 0x49, 0xfb, 0xf1,
|
||||
0xef, 0xe7, 0xf4, 0x49, 0xfa, 0xf1, 0xec, 0xe7,
|
||||
0xf3, 0x49, 0xf7, 0xf1, 0xe9, 0xe7, 0xf2, 0x49,
|
||||
0xf4, 0xf1, 0xe6, 0xe7, 0xb6, 0xc0, 0x50, 0x14,
|
||||
0x90, 0x13, 0xbc, 0x13, 0xf2, 0x14, 0x00, 0xa0,
|
||||
0xa0, 0xd1, 0x00, 0x00, 0xc0, 0x75, 0xd0, 0x49,
|
||||
0x46, 0xf0, 0x26, 0x72, 0xa7, 0x49, 0x43, 0xf0,
|
||||
0x22, 0x72, 0x25, 0x25, 0x20, 0x1f, 0x97, 0x30,
|
||||
0x91, 0x30, 0x40, 0x73, 0xf3, 0xc4, 0x1c, 0x40,
|
||||
0x04, 0xf0, 0xd7, 0x49, 0x05, 0xf1, 0x37, 0xe0,
|
||||
0x53, 0x48, 0xc0, 0x9d, 0x08, 0x02, 0x40, 0x66,
|
||||
0x64, 0x27, 0x06, 0x16, 0x30, 0xf1, 0x46, 0x63,
|
||||
0x3b, 0x13, 0x2d, 0xf1, 0x34, 0x9b, 0x18, 0x1b,
|
||||
0x93, 0x30, 0x2b, 0xc3, 0x10, 0x1c, 0x2b, 0xe8,
|
||||
0x01, 0x14, 0x25, 0xf1, 0x00, 0x1d, 0x26, 0x1a,
|
||||
0x8a, 0x30, 0x22, 0x73, 0xb5, 0x25, 0x0e, 0x0b,
|
||||
0x00, 0x1c, 0x2c, 0xe8, 0x1f, 0xc7, 0x27, 0x40,
|
||||
0x1a, 0xf1, 0x38, 0xe8, 0x32, 0x1f, 0x8f, 0x30,
|
||||
0x08, 0x1b, 0x24, 0xe8, 0x36, 0x72, 0x46, 0x77,
|
||||
0x00, 0x17, 0x0d, 0xf0, 0x13, 0xc3, 0x1f, 0x40,
|
||||
0x03, 0xf1, 0x00, 0x1f, 0x46, 0x9f, 0x44, 0x77,
|
||||
0x9f, 0x44, 0x5f, 0x44, 0x17, 0xe8, 0x0a, 0xc7,
|
||||
0x27, 0x40, 0x05, 0xf1, 0x02, 0xc3, 0x00, 0xbb,
|
||||
0xbe, 0x1a, 0x74, 0x14, 0xff, 0xc7, 0x00, 0xbf,
|
||||
0xb8, 0xcd, 0xff, 0xff, 0x02, 0x0c, 0x54, 0xa5,
|
||||
0xdc, 0xa5, 0x2f, 0x40, 0x05, 0xf1, 0x00, 0x14,
|
||||
0xfa, 0xf1, 0x01, 0x1c, 0x02, 0xe0, 0x00, 0x1c,
|
||||
0x80, 0xff, 0xb0, 0x49, 0x04, 0xf0, 0x01, 0x0b,
|
||||
0xd3, 0xa1, 0x03, 0xe0, 0x02, 0x0b, 0xd3, 0xa5,
|
||||
0x27, 0x31, 0x20, 0x37, 0x02, 0x0b, 0xd3, 0xa5,
|
||||
0x27, 0x31, 0x20, 0x37, 0x00, 0x13, 0xfb, 0xf1,
|
||||
0x80, 0xff, 0x22, 0x73, 0xb5, 0x25, 0x18, 0x1e,
|
||||
0xde, 0x30, 0xd9, 0x30, 0x64, 0x72, 0x11, 0x1e,
|
||||
0x68, 0x23, 0x16, 0x31, 0x80, 0xff, 0x08, 0xc2,
|
||||
0x40, 0x73, 0x3a, 0x48, 0x40, 0x9b, 0x06, 0xff,
|
||||
0x02, 0xc6, 0x00, 0xbe, 0xcc, 0x17, 0x1e, 0xfc,
|
||||
0x2c, 0x75, 0xdc, 0x21, 0xbc, 0x25, 0x04, 0x13,
|
||||
0x0b, 0xf0, 0x03, 0x13, 0x09, 0xf0, 0x02, 0x13,
|
||||
0x07, 0xf0, 0x01, 0x13, 0x05, 0xf0, 0x08, 0x13,
|
||||
0x03, 0xf0, 0x04, 0xc3, 0x00, 0xbb, 0x03, 0xc3,
|
||||
0x00, 0xbb, 0x50, 0x17, 0x3a, 0x17, 0x02, 0xc6,
|
||||
0x00, 0xbe, 0x00, 0x00, 0x02, 0xc6, 0x00, 0xbe,
|
||||
0x00, 0x00, 0x33, 0xc5, 0xa0, 0x74, 0xc0, 0x49,
|
||||
0x1f, 0xf0, 0x30, 0xc5, 0xa0, 0x73, 0x00, 0x13,
|
||||
0x04, 0xf1, 0xa2, 0x73, 0x00, 0x13, 0x14, 0xf0,
|
||||
0x28, 0xc5, 0xa0, 0x74, 0xc8, 0x49, 0x1b, 0xf1,
|
||||
0x26, 0xc5, 0xa0, 0x76, 0xa2, 0x74, 0x01, 0x06,
|
||||
0x20, 0x37, 0xa0, 0x9e, 0xa2, 0x9c, 0x1e, 0xc5,
|
||||
0xa2, 0x73, 0x23, 0x40, 0x10, 0xf8, 0x04, 0xf3,
|
||||
0xa0, 0x73, 0x33, 0x40, 0x0c, 0xf8, 0x15, 0xc5,
|
||||
0xa0, 0x74, 0x41, 0x48, 0xa0, 0x9c, 0x14, 0xc5,
|
||||
0xa0, 0x76, 0x62, 0x48, 0xe0, 0x48, 0xa0, 0x9e,
|
||||
0x10, 0xc6, 0x00, 0xbe, 0x0a, 0xc5, 0xa0, 0x74,
|
||||
0x48, 0x48, 0xa0, 0x9c, 0x0b, 0xc5, 0x20, 0x1e,
|
||||
0xa0, 0x9e, 0xe5, 0x48, 0xa0, 0x9e, 0xf0, 0xe7,
|
||||
0xbc, 0xc0, 0xc8, 0xd2, 0xcc, 0xd2, 0x28, 0xe4,
|
||||
0xfa, 0x01, 0xf0, 0xc0, 0x18, 0x89, 0x00, 0x1d,
|
||||
0x43, 0xc3, 0x62, 0x62, 0xa0, 0x49, 0x06, 0xf0,
|
||||
0x41, 0xc0, 0x02, 0x71, 0x60, 0x99, 0x3f, 0xc1,
|
||||
0x03, 0xe0, 0x3c, 0xc0, 0x3d, 0xc1, 0x02, 0x99,
|
||||
0x00, 0x61, 0x67, 0x11, 0x3d, 0xf1, 0x69, 0x33,
|
||||
0x34, 0xc0, 0x28, 0x40, 0xf7, 0xf1, 0x35, 0xc0,
|
||||
0x00, 0x19, 0x81, 0x1b, 0x89, 0xe8, 0x32, 0xc0,
|
||||
0x04, 0x1a, 0x84, 0x1b, 0x85, 0xe8, 0x7a, 0xe8,
|
||||
0xa3, 0x49, 0xfe, 0xf0, 0x2c, 0xc0, 0x76, 0xe8,
|
||||
0xa1, 0x48, 0x29, 0xc0, 0x84, 0x1b, 0x7c, 0xe8,
|
||||
0x00, 0x1d, 0x69, 0x33, 0x00, 0x1e, 0x01, 0x06,
|
||||
0xff, 0x18, 0x30, 0x40, 0xfd, 0xf1, 0x7f, 0xc0,
|
||||
0x00, 0x76, 0x2e, 0x40, 0xf7, 0xf1, 0x21, 0x48,
|
||||
0x1a, 0xc0, 0x84, 0x1b, 0x6d, 0xe8, 0x76, 0xc0,
|
||||
0x61, 0xe8, 0xa1, 0x49, 0xfd, 0xf0, 0x12, 0xc0,
|
||||
0x00, 0x1a, 0x84, 0x1b, 0x65, 0xe8, 0x5a, 0xe8,
|
||||
0xa5, 0x49, 0xfe, 0xf0, 0x0a, 0xc0, 0x01, 0x19,
|
||||
0x81, 0x1b, 0x5e, 0xe8, 0x48, 0xe0, 0x8c, 0xd3,
|
||||
0xb8, 0x0b, 0x50, 0xe8, 0x83, 0x00, 0x82, 0x00,
|
||||
0x20, 0xb4, 0x10, 0xd8, 0x84, 0xd4, 0xfa, 0xc0,
|
||||
0x00, 0x61, 0x9c, 0x20, 0x9c, 0x24, 0x06, 0x11,
|
||||
0x06, 0xf1, 0x5d, 0xc0, 0x00, 0x61, 0x11, 0x48,
|
||||
0x00, 0x89, 0x35, 0xe0, 0x00, 0x11, 0x02, 0xf1,
|
||||
0x03, 0xe0, 0x04, 0x11, 0x06, 0xf1, 0x53, 0xc0,
|
||||
0x00, 0x61, 0x92, 0x48, 0x00, 0x89, 0x2b, 0xe0,
|
||||
0x05, 0x11, 0x08, 0xf1, 0x4c, 0xc0, 0x00, 0x61,
|
||||
0x91, 0x49, 0x04, 0xf0, 0x91, 0x48, 0x00, 0x89,
|
||||
0x11, 0xe0, 0xdc, 0xc0, 0x00, 0x61, 0x98, 0x20,
|
||||
0x98, 0x24, 0x25, 0x11, 0x1c, 0xf1, 0x40, 0xc0,
|
||||
0x25, 0xe8, 0x95, 0x49, 0x18, 0xf0, 0xd2, 0xc0,
|
||||
0x00, 0x61, 0x98, 0x20, 0x98, 0x24, 0x25, 0x11,
|
||||
0x12, 0xf1, 0x35, 0xc0, 0x00, 0x61, 0x92, 0x49,
|
||||
0x0e, 0xf1, 0x12, 0x48, 0x00, 0x89, 0x2d, 0xc0,
|
||||
0x00, 0x19, 0x00, 0x89, 0x2b, 0xc0, 0x01, 0x89,
|
||||
0x27, 0xc0, 0x10, 0xe8, 0x25, 0xc0, 0x12, 0x48,
|
||||
0x81, 0x1b, 0x16, 0xe8, 0xb9, 0xc3, 0x62, 0x62,
|
||||
0xa0, 0x49, 0x05, 0xf0, 0xb5, 0xc3, 0x60, 0x71,
|
||||
0xb5, 0xc0, 0x02, 0x99, 0x02, 0xc0, 0x00, 0xb8,
|
||||
0xd6, 0x07, 0x13, 0xc4, 0x84, 0x98, 0x00, 0x1b,
|
||||
0x86, 0x8b, 0x86, 0x73, 0xbf, 0x49, 0xfe, 0xf1,
|
||||
0x80, 0x71, 0x82, 0x72, 0x80, 0xff, 0x09, 0xc4,
|
||||
0x84, 0x98, 0x80, 0x99, 0x82, 0x9a, 0x86, 0x8b,
|
||||
0x86, 0x73, 0xbf, 0x49, 0xfe, 0xf1, 0x80, 0xff,
|
||||
0x08, 0xea, 0x10, 0xd4, 0x88, 0xd3, 0x30, 0xd4,
|
||||
0x10, 0xc0, 0x12, 0xe8, 0x8a, 0xd3, 0x00, 0xd8,
|
||||
0x02, 0xc0, 0x00, 0xb8, 0xe0, 0x08, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
|
||||
|
||||
static u16 r8153_pla_patch_c_bp[] = {
|
||||
0xfc26, 0x8000, 0xfc28, 0x1306, 0xfc2a, 0x17ca, 0xfc2c, 0x171e,
|
||||
0xfc2e, 0x0000, 0xfc30, 0x0000, 0xfc32, 0x01b4, 0xfc34, 0x07d4,
|
||||
0xfc36, 0x0894, 0xfc38, 0x00e7 };
|
||||
|
||||
static u16 r8153_ram_code_bc[] = {
|
||||
0xB436, 0xB820, 0xB438, 0x0290, 0xB436, 0xA012, 0xB438, 0x0000,
|
||||
0xB436, 0xA014, 0xB438, 0x2c04, 0xB438, 0x2c07, 0xB438, 0x2c0a,
|
||||
0xB438, 0x2c0d, 0xB438, 0xa240, 0xB438, 0xa104, 0xB438, 0x292d,
|
||||
0xB438, 0x8620, 0xB438, 0xa480, 0xB438, 0x2a2c, 0xB438, 0x8480,
|
||||
0xB438, 0xa101, 0xB438, 0x2a36, 0xB438, 0xd056, 0xB438, 0x2223,
|
||||
0xB436, 0xA01A, 0xB438, 0x0000, 0xB436, 0xA006, 0xB438, 0x0222,
|
||||
0xB436, 0xA004, 0xB438, 0x0a35, 0xB436, 0xA002, 0xB438, 0x0a2b,
|
||||
0xB436, 0xA000, 0xB438, 0xf92c, 0xB436, 0xB820, 0xB438, 0x0210 };
|
||||
|
||||
static u8 r8153_usb_patch_b[] = {
|
||||
0x08, 0xe0, 0x0f, 0xe0, 0x18, 0xe0, 0x24, 0xe0,
|
||||
0x26, 0xe0, 0x3a, 0xe0, 0x84, 0xe0, 0x9c, 0xe0,
|
||||
0xc2, 0x49, 0x04, 0xf0, 0x02, 0xc0, 0x00, 0xb8,
|
||||
0x14, 0x18, 0x02, 0xc0, 0x00, 0xb8, 0x2e, 0x18,
|
||||
0x06, 0x89, 0x08, 0xc0, 0x0c, 0x61, 0x92, 0x48,
|
||||
0x93, 0x48, 0x0c, 0x89, 0x02, 0xc0, 0x00, 0xb8,
|
||||
0x08, 0x05, 0x40, 0xb4, 0x16, 0x89, 0x6d, 0xc0,
|
||||
0x00, 0x61, 0x95, 0x49, 0x06, 0xf0, 0xfa, 0xc0,
|
||||
0x0c, 0x61, 0x92, 0x48, 0x93, 0x48, 0x0c, 0x89,
|
||||
0x02, 0xc0, 0x00, 0xb8, 0xe2, 0x04, 0x02, 0xc2,
|
||||
0x00, 0xba, 0xec, 0x11, 0x60, 0x60, 0x85, 0x49,
|
||||
0x0d, 0xf1, 0x11, 0xc6, 0xd2, 0x61, 0x91, 0x49,
|
||||
0xfd, 0xf0, 0x74, 0x60, 0x04, 0x48, 0x74, 0x88,
|
||||
0x08, 0xc6, 0x08, 0xc0, 0xc4, 0x98, 0x01, 0x18,
|
||||
0xc0, 0x88, 0x02, 0xc0, 0x00, 0xb8, 0x6e, 0x12,
|
||||
0x04, 0xe4, 0x0d, 0x00, 0x00, 0xd4, 0xd1, 0x49,
|
||||
0x3c, 0xf1, 0xd2, 0x49, 0x16, 0xf1, 0xd3, 0x49,
|
||||
0x18, 0xf1, 0xd4, 0x49, 0x19, 0xf1, 0xd5, 0x49,
|
||||
0x1a, 0xf1, 0xd6, 0x49, 0x1b, 0xf1, 0xd7, 0x49,
|
||||
0x1c, 0xf1, 0xd8, 0x49, 0x1d, 0xf1, 0xd9, 0x49,
|
||||
0x20, 0xf1, 0xda, 0x49, 0x23, 0xf1, 0xdb, 0x49,
|
||||
0x24, 0xf1, 0x02, 0xc4, 0x00, 0xbc, 0x20, 0x04,
|
||||
0xe5, 0x8e, 0x02, 0xc4, 0x00, 0xbc, 0x14, 0x02,
|
||||
0x02, 0xc4, 0x00, 0xbc, 0x16, 0x02, 0x02, 0xc4,
|
||||
0x00, 0xbc, 0x18, 0x02, 0x02, 0xc4, 0x00, 0xbc,
|
||||
0x1a, 0x02, 0x02, 0xc4, 0x00, 0xbc, 0x1c, 0x02,
|
||||
0x02, 0xc4, 0x00, 0xbc, 0x94, 0x02, 0x10, 0xc7,
|
||||
0xe0, 0x8e, 0x02, 0xc4, 0x00, 0xbc, 0x8a, 0x02,
|
||||
0x0b, 0xc7, 0xe4, 0x8e, 0x02, 0xc4, 0x00, 0xbc,
|
||||
0x88, 0x02, 0x02, 0xc4, 0x00, 0xbc, 0x6e, 0x02,
|
||||
0x02, 0xc4, 0x00, 0xbc, 0x5a, 0x02, 0x30, 0xe4,
|
||||
0x0c, 0xc3, 0x60, 0x64, 0xc5, 0x49, 0x04, 0xf1,
|
||||
0x74, 0x64, 0xc4, 0x48, 0x74, 0x8c, 0x06, 0xc3,
|
||||
0x64, 0x8e, 0x02, 0xc4, 0x00, 0xbc, 0x20, 0x04,
|
||||
0x00, 0xd8, 0x00, 0xe4, 0xb2, 0xc0, 0x00, 0x61,
|
||||
0x90, 0x49, 0x09, 0xf1, 0x8b, 0xc6, 0xca, 0x61,
|
||||
0x94, 0x49, 0x0e, 0xf1, 0xf6, 0xc6, 0xda, 0x60,
|
||||
0x81, 0x49, 0x0a, 0xf0, 0x65, 0x60, 0x03, 0x48,
|
||||
0x65, 0x88, 0xef, 0xc6, 0xdc, 0x60, 0x80, 0x48,
|
||||
0xdc, 0x88, 0x05, 0xc6, 0x00, 0xbe, 0x02, 0xc6,
|
||||
0x00, 0xbe, 0x36, 0x13, 0x4c, 0x17, 0x99, 0xc4,
|
||||
0x80, 0x65, 0xd0, 0x49, 0x04, 0xf1, 0xfa, 0x75,
|
||||
0x04, 0xc4, 0x00, 0xbc, 0x03, 0xc4, 0x00, 0xbc,
|
||||
0x9a, 0x00, 0xee, 0x01 };
|
||||
|
||||
static u16 r8153_usb_patch_b_bp[] = {
|
||||
0xfc26, 0xa000, 0xfc28, 0x180c, 0xfc2a, 0x0506, 0xfc2c, 0x04E0,
|
||||
0xfc2e, 0x11E4, 0xfc30, 0x125C, 0xfc32, 0x0232, 0xfc34, 0x131E,
|
||||
0xfc36, 0x0098, 0xfc38, 0x00FF };
|
||||
|
||||
static u8 r8153_pla_patch_b[] = {
|
||||
0x08, 0xe0, 0xea, 0xe0, 0xf2, 0xe0, 0x04, 0xe1,
|
||||
0x09, 0xe1, 0x0e, 0xe1, 0x46, 0xe1, 0xf3, 0xe1,
|
||||
0x14, 0xc2, 0x40, 0x73, 0xba, 0x48, 0x40, 0x9b,
|
||||
0x11, 0xc2, 0x40, 0x73, 0xb0, 0x49, 0x17, 0xf0,
|
||||
0xbf, 0x49, 0x03, 0xf1, 0x09, 0xc5, 0x00, 0xbd,
|
||||
0xb1, 0x49, 0x11, 0xf0, 0xb1, 0x48, 0x40, 0x9b,
|
||||
0x02, 0xc2, 0x00, 0xba, 0x1a, 0x17, 0x00, 0xe0,
|
||||
0x1e, 0xfc, 0xbc, 0xc0, 0xf0, 0xc0, 0xde, 0xe8,
|
||||
0x00, 0x80, 0x00, 0x20, 0x2c, 0x75, 0xd4, 0x49,
|
||||
0x12, 0xf1, 0x32, 0xe0, 0xf8, 0xc2, 0x46, 0x71,
|
||||
0xf7, 0xc2, 0x40, 0x73, 0xbe, 0x49, 0x03, 0xf1,
|
||||
0xf5, 0xc7, 0x02, 0xe0, 0xf2, 0xc7, 0x4f, 0x30,
|
||||
0x26, 0x62, 0xa1, 0x49, 0xf0, 0xf1, 0x22, 0x72,
|
||||
0xa0, 0x49, 0xed, 0xf1, 0x25, 0x25, 0x18, 0x1f,
|
||||
0x97, 0x30, 0x91, 0x30, 0x36, 0x9a, 0x2c, 0x75,
|
||||
0x3c, 0xc3, 0x60, 0x73, 0xb1, 0x49, 0x0d, 0xf1,
|
||||
0xdc, 0x21, 0xbc, 0x25, 0x30, 0xc6, 0xc0, 0x77,
|
||||
0x04, 0x13, 0x21, 0xf0, 0x03, 0x13, 0x22, 0xf0,
|
||||
0x02, 0x13, 0x23, 0xf0, 0x01, 0x13, 0x24, 0xf0,
|
||||
0x08, 0x13, 0x08, 0xf1, 0x2e, 0x73, 0xba, 0x21,
|
||||
0xbd, 0x25, 0x05, 0x13, 0x03, 0xf1, 0x24, 0xc5,
|
||||
0x00, 0xbd, 0xd4, 0x49, 0x03, 0xf1, 0x1c, 0xc5,
|
||||
0x00, 0xbd, 0xc4, 0xc6, 0xc6, 0x67, 0x2e, 0x75,
|
||||
0xd7, 0x22, 0xdd, 0x26, 0x05, 0x15, 0x1b, 0xf0,
|
||||
0x14, 0xc6, 0x00, 0xbe, 0x13, 0xc5, 0x00, 0xbd,
|
||||
0x12, 0xc5, 0x00, 0xbd, 0xf1, 0x49, 0xfb, 0xf1,
|
||||
0xef, 0xe7, 0xf4, 0x49, 0xfa, 0xf1, 0xec, 0xe7,
|
||||
0xf3, 0x49, 0xf7, 0xf1, 0xe9, 0xe7, 0xf2, 0x49,
|
||||
0xf4, 0xf1, 0xe6, 0xe7, 0xb6, 0xc0, 0x9e, 0x12,
|
||||
0xde, 0x11, 0x0a, 0x12, 0x3c, 0x13, 0x00, 0xa0,
|
||||
0xa0, 0xd1, 0x00, 0x00, 0xc0, 0x75, 0xd0, 0x49,
|
||||
0x46, 0xf0, 0x26, 0x72, 0xa7, 0x49, 0x43, 0xf0,
|
||||
0x22, 0x72, 0x25, 0x25, 0x20, 0x1f, 0x97, 0x30,
|
||||
0x91, 0x30, 0x40, 0x73, 0xf3, 0xc4, 0x1c, 0x40,
|
||||
0x04, 0xf0, 0xd7, 0x49, 0x05, 0xf1, 0x37, 0xe0,
|
||||
0x53, 0x48, 0xc0, 0x9d, 0x08, 0x02, 0x40, 0x66,
|
||||
0x64, 0x27, 0x06, 0x16, 0x30, 0xf1, 0x46, 0x63,
|
||||
0x3b, 0x13, 0x2d, 0xf1, 0x34, 0x9b, 0x18, 0x1b,
|
||||
0x93, 0x30, 0x2b, 0xc3, 0x10, 0x1c, 0x2b, 0xe8,
|
||||
0x01, 0x14, 0x25, 0xf1, 0x00, 0x1d, 0x26, 0x1a,
|
||||
0x8a, 0x30, 0x22, 0x73, 0xb5, 0x25, 0x0e, 0x0b,
|
||||
0x00, 0x1c, 0x2c, 0xe8, 0x1f, 0xc7, 0x27, 0x40,
|
||||
0x1a, 0xf1, 0x38, 0xe8, 0x32, 0x1f, 0x8f, 0x30,
|
||||
0x08, 0x1b, 0x24, 0xe8, 0x36, 0x72, 0x46, 0x77,
|
||||
0x00, 0x17, 0x0d, 0xf0, 0x13, 0xc3, 0x1f, 0x40,
|
||||
0x03, 0xf1, 0x00, 0x1f, 0x46, 0x9f, 0x44, 0x77,
|
||||
0x9f, 0x44, 0x5f, 0x44, 0x17, 0xe8, 0x0a, 0xc7,
|
||||
0x27, 0x40, 0x05, 0xf1, 0x02, 0xc3, 0x00, 0xbb,
|
||||
0xfa, 0x18, 0xb0, 0x18, 0xff, 0xc7, 0x00, 0xbf,
|
||||
0xb8, 0xcd, 0xff, 0xff, 0x02, 0x0c, 0x54, 0xa5,
|
||||
0xdc, 0xa5, 0x2f, 0x40, 0x05, 0xf1, 0x00, 0x14,
|
||||
0xfa, 0xf1, 0x01, 0x1c, 0x02, 0xe0, 0x00, 0x1c,
|
||||
0x80, 0xff, 0xb0, 0x49, 0x04, 0xf0, 0x01, 0x0b,
|
||||
0xd3, 0xa1, 0x03, 0xe0, 0x02, 0x0b, 0xd3, 0xa5,
|
||||
0x27, 0x31, 0x20, 0x37, 0x02, 0x0b, 0xd3, 0xa5,
|
||||
0x27, 0x31, 0x20, 0x37, 0x00, 0x13, 0xfb, 0xf1,
|
||||
0x80, 0xff, 0x22, 0x73, 0xb5, 0x25, 0x18, 0x1e,
|
||||
0xde, 0x30, 0xd9, 0x30, 0x64, 0x72, 0x11, 0x1e,
|
||||
0x68, 0x23, 0x16, 0x31, 0x80, 0xff, 0x08, 0xc2,
|
||||
0x40, 0x73, 0x3a, 0x48, 0x40, 0x9b, 0x06, 0xff,
|
||||
0x02, 0xc6, 0x00, 0xbe, 0x08, 0x16, 0x1e, 0xfc,
|
||||
0x2c, 0x75, 0xdc, 0x21, 0xbc, 0x25, 0x04, 0x13,
|
||||
0x0b, 0xf0, 0x03, 0x13, 0x09, 0xf0, 0x02, 0x13,
|
||||
0x07, 0xf0, 0x01, 0x13, 0x05, 0xf0, 0x08, 0x13,
|
||||
0x03, 0xf0, 0x04, 0xc3, 0x00, 0xbb, 0x03, 0xc3,
|
||||
0x00, 0xbb, 0x8c, 0x15, 0x76, 0x15, 0xa0, 0x64,
|
||||
0x40, 0x48, 0xa0, 0x8c, 0x02, 0xc4, 0x00, 0xbc,
|
||||
0x82, 0x00, 0xa0, 0x62, 0x21, 0x48, 0xa0, 0x8a,
|
||||
0x02, 0xc2, 0x00, 0xba, 0x40, 0x03, 0x33, 0xc5,
|
||||
0xa0, 0x74, 0xc0, 0x49, 0x1f, 0xf0, 0x30, 0xc5,
|
||||
0xa0, 0x73, 0x00, 0x13, 0x04, 0xf1, 0xa2, 0x73,
|
||||
0x00, 0x13, 0x14, 0xf0, 0x28, 0xc5, 0xa0, 0x74,
|
||||
0xc8, 0x49, 0x1b, 0xf1, 0x26, 0xc5, 0xa0, 0x76,
|
||||
0xa2, 0x74, 0x01, 0x06, 0x20, 0x37, 0xa0, 0x9e,
|
||||
0xa2, 0x9c, 0x1e, 0xc5, 0xa2, 0x73, 0x23, 0x40,
|
||||
0x10, 0xf8, 0x04, 0xf3, 0xa0, 0x73, 0x33, 0x40,
|
||||
0x0c, 0xf8, 0x15, 0xc5, 0xa0, 0x74, 0x41, 0x48,
|
||||
0xa0, 0x9c, 0x14, 0xc5, 0xa0, 0x76, 0x62, 0x48,
|
||||
0xe0, 0x48, 0xa0, 0x9e, 0x10, 0xc6, 0x00, 0xbe,
|
||||
0x0a, 0xc5, 0xa0, 0x74, 0x48, 0x48, 0xa0, 0x9c,
|
||||
0x0b, 0xc5, 0x20, 0x1e, 0xa0, 0x9e, 0xe5, 0x48,
|
||||
0xa0, 0x9e, 0xf0, 0xe7, 0xbc, 0xc0, 0xc8, 0xd2,
|
||||
0xcc, 0xd2, 0x28, 0xe4, 0xe6, 0x01, 0xf0, 0xc0,
|
||||
0x18, 0x89, 0x00, 0x1d, 0x3c, 0xc3, 0x60, 0x71,
|
||||
0x3c, 0xc0, 0x02, 0x99, 0x00, 0x61, 0x67, 0x11,
|
||||
0x3c, 0xf1, 0x69, 0x33, 0x35, 0xc0, 0x28, 0x40,
|
||||
0xf6, 0xf1, 0x34, 0xc0, 0x00, 0x19, 0x81, 0x1b,
|
||||
0x8c, 0xe8, 0x31, 0xc0, 0x04, 0x1a, 0x84, 0x1b,
|
||||
0x88, 0xe8, 0x7d, 0xe8, 0xa3, 0x49, 0xfe, 0xf0,
|
||||
0x2b, 0xc0, 0x79, 0xe8, 0xa1, 0x48, 0x28, 0xc0,
|
||||
0x84, 0x1b, 0x7f, 0xe8, 0x00, 0x1d, 0x69, 0x33,
|
||||
0x00, 0x1e, 0x01, 0x06, 0xff, 0x18, 0x30, 0x40,
|
||||
0xfd, 0xf1, 0x18, 0xc0, 0x00, 0x76, 0x2e, 0x40,
|
||||
0xf7, 0xf1, 0x21, 0x48, 0x19, 0xc0, 0x84, 0x1b,
|
||||
0x70, 0xe8, 0x79, 0xc0, 0x64, 0xe8, 0xa1, 0x49,
|
||||
0xfd, 0xf0, 0x11, 0xc0, 0x00, 0x1a, 0x84, 0x1b,
|
||||
0x68, 0xe8, 0x5d, 0xe8, 0xa5, 0x49, 0xfe, 0xf0,
|
||||
0x09, 0xc0, 0x01, 0x19, 0x81, 0x1b, 0x61, 0xe8,
|
||||
0x4f, 0xe0, 0x88, 0xd3, 0x8c, 0xd3, 0xb8, 0x0b,
|
||||
0x50, 0xe8, 0x20, 0xb4, 0x10, 0xd8, 0x84, 0xd4,
|
||||
0xfc, 0xc0, 0x00, 0x61, 0x9c, 0x20, 0x9c, 0x24,
|
||||
0x06, 0x11, 0x06, 0xf1, 0x60, 0xc0, 0x00, 0x61,
|
||||
0x11, 0x48, 0x00, 0x89, 0x3d, 0xe0, 0x00, 0x11,
|
||||
0x02, 0xf1, 0x03, 0xe0, 0x04, 0x11, 0x06, 0xf1,
|
||||
0x56, 0xc0, 0x00, 0x61, 0x92, 0x48, 0x00, 0x89,
|
||||
0x33, 0xe0, 0x05, 0x11, 0x08, 0xf1, 0x4f, 0xc0,
|
||||
0x00, 0x61, 0x91, 0x49, 0x04, 0xf0, 0x91, 0x48,
|
||||
0x00, 0x89, 0x11, 0xe0, 0xde, 0xc0, 0x00, 0x61,
|
||||
0x98, 0x20, 0x98, 0x24, 0x25, 0x11, 0x24, 0xf1,
|
||||
0x45, 0xc0, 0x29, 0xe8, 0x95, 0x49, 0x20, 0xf0,
|
||||
0xd4, 0xc0, 0x00, 0x61, 0x98, 0x20, 0x98, 0x24,
|
||||
0x25, 0x11, 0x1a, 0xf1, 0x38, 0xc0, 0x00, 0x61,
|
||||
0x92, 0x49, 0x16, 0xf1, 0x12, 0x48, 0x00, 0x89,
|
||||
0x30, 0xc0, 0x00, 0x19, 0x00, 0x89, 0x2e, 0xc0,
|
||||
0x01, 0x89, 0x2e, 0xc0, 0x04, 0x19, 0x81, 0x1b,
|
||||
0x1c, 0xe8, 0x2b, 0xc0, 0x14, 0x19, 0x81, 0x1b,
|
||||
0x18, 0xe8, 0x22, 0xc0, 0x0c, 0xe8, 0x20, 0xc0,
|
||||
0x12, 0x48, 0x81, 0x1b, 0x12, 0xe8, 0xb3, 0xc3,
|
||||
0x62, 0x71, 0xb3, 0xc0, 0x02, 0x99, 0x02, 0xc0,
|
||||
0x00, 0xb8, 0x96, 0x07, 0x13, 0xc4, 0x84, 0x98,
|
||||
0x00, 0x1b, 0x86, 0x8b, 0x86, 0x73, 0xbf, 0x49,
|
||||
0xfe, 0xf1, 0x80, 0x71, 0x82, 0x72, 0x80, 0xff,
|
||||
0x09, 0xc4, 0x84, 0x98, 0x80, 0x99, 0x82, 0x9a,
|
||||
0x86, 0x8b, 0x86, 0x73, 0xbf, 0x49, 0xfe, 0xf1,
|
||||
0x80, 0xff, 0x08, 0xea, 0x10, 0xd4, 0x30, 0xd4,
|
||||
0x10, 0xc0, 0x12, 0xe8, 0x8a, 0xd3, 0x28, 0xe4,
|
||||
0x2c, 0xe4, 0x00, 0xd8, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
|
||||
|
||||
static u16 r8153_pla_patch_b_bp[] = {
|
||||
0xfc26, 0x8000, 0xfc28, 0x1154, 0xfc2a, 0x1606, 0xfc2c, 0x155a,
|
||||
0xfc2e, 0x0080, 0xfc30, 0x033c, 0xfc32, 0x01a0, 0xfc34, 0x0794,
|
||||
0xfc36, 0x0000, 0xfc38, 0x007f };
|
||||
|
||||
static u16 r8153_ram_code_d[] = {
|
||||
0xa436, 0xb820, 0xa438, 0x0290, 0xa436, 0xa012, 0xa438, 0x0000,
|
||||
0xa436, 0xa014, 0xa438, 0x2c04, 0xb438, 0x2c07, 0xb438, 0x2c07,
|
||||
0xb438, 0x2c07, 0xb438, 0xa240, 0xb438, 0xa104, 0xb438, 0x2944,
|
||||
0xa436, 0xa01a, 0xa438, 0x0000, 0xa436, 0xa006, 0xa438, 0x0fff,
|
||||
0xa436, 0xa004, 0xa438, 0x0fff, 0xa436, 0xa002, 0xa438, 0x0fff,
|
||||
0xa436, 0xa000, 0xa438, 0x1943, 0xa436, 0xb820, 0xa438, 0x0210 };
|
||||
|
||||
static u8 usb_patch_d[] = {
|
||||
0x08, 0xe0, 0x0a, 0xe0, 0x0c, 0xe0, 0x1f, 0xe0,
|
||||
0x28, 0xe0, 0x2a, 0xe0, 0x2c, 0xe0, 0x2e, 0xe0,
|
||||
0x02, 0xc5, 0x00, 0xbd, 0x00, 0x00, 0x02, 0xc3,
|
||||
0x00, 0xbb, 0x00, 0x00, 0x30, 0x18, 0x11, 0xc1,
|
||||
0x05, 0xe8, 0x10, 0xc6, 0x02, 0xc2, 0x00, 0xba,
|
||||
0x94, 0x17, 0x02, 0xb4, 0x09, 0xc2, 0x40, 0x99,
|
||||
0x0e, 0x48, 0x42, 0x98, 0x42, 0x70, 0x8e, 0x49,
|
||||
0xfe, 0xf1, 0x02, 0xb0, 0x80, 0xff, 0xc0, 0xd4,
|
||||
0xe4, 0x40, 0x20, 0xd4, 0xb0, 0x49, 0x04, 0xf0,
|
||||
0x30, 0x18, 0x06, 0xc1, 0xef, 0xef, 0xfa, 0xc7,
|
||||
0x02, 0xc0, 0x00, 0xb8, 0x38, 0x12, 0xe4, 0x4b,
|
||||
0x02, 0xc3, 0x00, 0xbb, 0x00, 0x00, 0x02, 0xc5,
|
||||
0x00, 0xbd, 0x00, 0x00, 0x02, 0xc1, 0x00, 0xb9,
|
||||
0x00, 0x00, 0x02, 0xc1, 0x00, 0xb9, 0x00, 0x00 };
|
||||
|
||||
static u16 r8153_usb_patch_d_bp[] = {
|
||||
0xfc26, 0xa000, 0xfc28, 0x0000, 0xfc2a, 0x0000, 0xfc2c, 0x1792,
|
||||
0xfc2e, 0x1236, 0xfc30, 0x0000, 0xfc32, 0x0000, 0xfc34, 0x0000,
|
||||
0xfc36, 0x0000, 0xfc38, 0x000c };
|
||||
|
||||
static void rtl_clear_bp(struct r8152 *tp)
|
||||
{
|
||||
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
|
||||
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
|
||||
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
|
||||
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
|
||||
ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
|
||||
ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
|
||||
ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
|
||||
ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
|
||||
|
||||
mdelay(6);
|
||||
|
||||
ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
|
||||
ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
|
||||
}
|
||||
|
||||
static void r8153_clear_bp(struct r8152 *tp)
|
||||
{
|
||||
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
|
||||
ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0);
|
||||
rtl_clear_bp(tp);
|
||||
}
|
||||
|
||||
static void r8152b_set_dq_desc(struct r8152 *tp)
|
||||
{
|
||||
u8 data;
|
||||
|
||||
data = ocp_read_byte(tp, MCU_TYPE_USB, 0xd429);
|
||||
data |= 0x80;
|
||||
ocp_write_byte(tp, MCU_TYPE_USB, 0xd429, data);
|
||||
ocp_write_word(tp, MCU_TYPE_USB, 0xc0ce, 0x0210);
|
||||
data = ocp_read_byte(tp, MCU_TYPE_USB, 0xd429);
|
||||
data &= ~0x80;
|
||||
ocp_write_byte(tp, MCU_TYPE_USB, 0xd429, data);
|
||||
}
|
||||
|
||||
static int r8153_pre_ram_code(struct r8152 *tp, u16 patch_key)
|
||||
{
|
||||
u16 data;
|
||||
int i;
|
||||
|
||||
data = ocp_reg_read(tp, 0xb820);
|
||||
data |= 0x0010;
|
||||
ocp_reg_write(tp, 0xb820, data);
|
||||
|
||||
for (i = 0, data = 0; !data && i < 5000; i++) {
|
||||
mdelay(2);
|
||||
data = ocp_reg_read(tp, 0xb800) & 0x0040;
|
||||
}
|
||||
|
||||
sram_write(tp, 0x8146, patch_key);
|
||||
sram_write(tp, 0xb82e, 0x0001);
|
||||
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
static int r8153_post_ram_code(struct r8152 *tp)
|
||||
{
|
||||
u16 data;
|
||||
|
||||
sram_write(tp, 0x0000, 0x0000);
|
||||
|
||||
data = ocp_reg_read(tp, 0xb82e);
|
||||
data &= ~0x0001;
|
||||
ocp_reg_write(tp, 0xb82e, data);
|
||||
|
||||
sram_write(tp, 0x8146, 0x0000);
|
||||
|
||||
data = ocp_reg_read(tp, 0xb820);
|
||||
data &= ~0x0010;
|
||||
ocp_reg_write(tp, 0xb820, data);
|
||||
|
||||
ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void r8153_wdt1_end(struct r8152 *tp)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 104; i++) {
|
||||
if (!(ocp_read_byte(tp, MCU_TYPE_USB, 0xe404) & 1))
|
||||
break;
|
||||
mdelay(2);
|
||||
}
|
||||
}
|
||||
|
||||
void r8152b_firmware(struct r8152 *tp)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (tp->version == RTL_VER_01) {
|
||||
int i;
|
||||
|
||||
r8152b_set_dq_desc(tp);
|
||||
rtl_clear_bp(tp);
|
||||
|
||||
generic_ocp_write(tp, 0xf800, 0x3f,
|
||||
sizeof(r8152b_pla_patch_a),
|
||||
r8152b_pla_patch_a, MCU_TYPE_PLA);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(r8152b_pla_patch_a_bp); i += 2)
|
||||
ocp_write_word(tp, MCU_TYPE_PLA,
|
||||
r8152b_pla_patch_a_bp[i],
|
||||
r8152b_pla_patch_a_bp[i+1]);
|
||||
|
||||
ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
|
||||
ocp_write_word(tp, MCU_TYPE_PLA, 0xb092, 0x7070);
|
||||
ocp_write_word(tp, MCU_TYPE_PLA, 0xb098, 0x0600);
|
||||
for (i = 0; i < ARRAY_SIZE(r8152b_ram_code1); i++)
|
||||
ocp_write_word(tp, MCU_TYPE_PLA, 0xb09a,
|
||||
r8152b_ram_code1[i]);
|
||||
|
||||
ocp_write_word(tp, MCU_TYPE_PLA, 0xb098, 0x0200);
|
||||
ocp_write_word(tp, MCU_TYPE_PLA, 0xb092, 0x7030);
|
||||
} else if (tp->version == RTL_VER_02) {
|
||||
rtl_clear_bp(tp);
|
||||
|
||||
generic_ocp_write(tp, 0xf800, 0xff,
|
||||
sizeof(r8152b_pla_patch_a2),
|
||||
r8152b_pla_patch_a2, MCU_TYPE_PLA);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(r8152b_pla_patch_a2_bp);
|
||||
i += 2)
|
||||
ocp_write_word(tp, MCU_TYPE_PLA,
|
||||
r8152b_pla_patch_a2_bp[i],
|
||||
r8152b_pla_patch_a2_bp[i+1]);
|
||||
}
|
||||
}
|
||||
|
||||
void r8153_firmware(struct r8152 *tp)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (tp->version == RTL_VER_03) {
|
||||
r8153_clear_bp(tp);
|
||||
|
||||
r8153_pre_ram_code(tp, 0x7000);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(r8153_ram_code_a); i += 2)
|
||||
ocp_write_word(tp, MCU_TYPE_PLA,
|
||||
r8153_ram_code_a[i],
|
||||
r8153_ram_code_a[i+1]);
|
||||
|
||||
r8153_post_ram_code(tp);
|
||||
} else if (tp->version == RTL_VER_04) {
|
||||
r8153_pre_ram_code(tp, 0x7001);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(r8153_ram_code_bc); i += 2)
|
||||
ocp_write_word(tp, MCU_TYPE_PLA,
|
||||
r8153_ram_code_bc[i],
|
||||
r8153_ram_code_bc[i+1]);
|
||||
|
||||
r8153_post_ram_code(tp);
|
||||
|
||||
r8153_wdt1_end(tp);
|
||||
r8153_clear_bp(tp);
|
||||
|
||||
ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x0000);
|
||||
generic_ocp_write(tp, 0xf800, 0xff,
|
||||
sizeof(r8153_usb_patch_b),
|
||||
r8153_usb_patch_b, MCU_TYPE_USB);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(r8153_usb_patch_b_bp); i += 2)
|
||||
ocp_write_word(tp, MCU_TYPE_USB,
|
||||
r8153_usb_patch_b_bp[i],
|
||||
r8153_usb_patch_b_bp[i+1]);
|
||||
|
||||
if (!(ocp_read_word(tp, MCU_TYPE_PLA, 0xd38e) & BIT(0))) {
|
||||
ocp_write_word(tp, MCU_TYPE_PLA, 0xd38c, 0x0082);
|
||||
ocp_write_word(tp, MCU_TYPE_PLA, 0xd38e, 0x0082);
|
||||
}
|
||||
|
||||
ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, 0x0000);
|
||||
generic_ocp_write(tp, 0xf800, 0xff,
|
||||
sizeof(r8153_pla_patch_b),
|
||||
r8153_pla_patch_b, MCU_TYPE_PLA);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(r8153_pla_patch_b_bp); i += 2)
|
||||
ocp_write_word(tp, MCU_TYPE_PLA,
|
||||
r8153_pla_patch_b_bp[i],
|
||||
r8153_pla_patch_b_bp[i+1]);
|
||||
|
||||
ocp_write_word(tp, MCU_TYPE_PLA, 0xd388, 0x08ca);
|
||||
} else if (tp->version == RTL_VER_05) {
|
||||
u32 ocp_data;
|
||||
|
||||
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcfca);
|
||||
ocp_data &= ~0x4000;
|
||||
ocp_write_word(tp, MCU_TYPE_USB, 0xcfca, ocp_data);
|
||||
|
||||
r8153_pre_ram_code(tp, 0x7001);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(r8153_ram_code_bc); i += 2)
|
||||
ocp_write_word(tp, MCU_TYPE_PLA,
|
||||
r8153_ram_code_bc[i],
|
||||
r8153_ram_code_bc[i+1]);
|
||||
|
||||
r8153_post_ram_code(tp);
|
||||
|
||||
r8153_wdt1_end(tp);
|
||||
r8153_clear_bp(tp);
|
||||
|
||||
ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x0000);
|
||||
generic_ocp_write(tp, 0xf800, 0xff,
|
||||
sizeof(r8153_usb_patch_c),
|
||||
r8153_usb_patch_c, MCU_TYPE_USB);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(r8153_usb_patch_c_bp); i += 2)
|
||||
ocp_write_word(tp, MCU_TYPE_USB,
|
||||
r8153_usb_patch_c_bp[i],
|
||||
r8153_usb_patch_c_bp[i+1]);
|
||||
|
||||
if (ocp_read_byte(tp, MCU_TYPE_USB, 0xcfef) & 1) {
|
||||
ocp_write_word(tp, MCU_TYPE_USB, 0xfc30, 0x1578);
|
||||
ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x00ff);
|
||||
} else {
|
||||
ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x00ef);
|
||||
}
|
||||
|
||||
ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, 0x0000);
|
||||
generic_ocp_write(tp, 0xf800, 0xff,
|
||||
sizeof(r8153_pla_patch_c),
|
||||
r8153_pla_patch_c, MCU_TYPE_PLA);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(r8153_pla_patch_c_bp); i += 2)
|
||||
ocp_write_word(tp, MCU_TYPE_PLA,
|
||||
r8153_pla_patch_c_bp[i],
|
||||
r8153_pla_patch_c_bp[i+1]);
|
||||
|
||||
ocp_write_word(tp, MCU_TYPE_PLA, 0xd388, 0x08ca);
|
||||
|
||||
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcfca);
|
||||
ocp_data |= 0x4000;
|
||||
ocp_write_word(tp, MCU_TYPE_USB, 0xcfca, ocp_data);
|
||||
} else if (tp->version == RTL_VER_06) {
|
||||
r8153_pre_ram_code(tp, 0x7002);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(r8153_ram_code_d); i += 2)
|
||||
ocp_write_word(tp, MCU_TYPE_PLA,
|
||||
r8153_ram_code_d[i],
|
||||
r8153_ram_code_d[i+1]);
|
||||
|
||||
r8153_post_ram_code(tp);
|
||||
|
||||
r8153_clear_bp(tp);
|
||||
|
||||
ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x0000);
|
||||
generic_ocp_write(tp, 0xf800, 0xff, sizeof(usb_patch_d),
|
||||
usb_patch_d, MCU_TYPE_USB);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(r8153_usb_patch_d_bp); i += 2)
|
||||
ocp_write_word(tp, MCU_TYPE_USB,
|
||||
r8153_usb_patch_d_bp[i],
|
||||
r8153_usb_patch_d_bp[i+1]);
|
||||
}
|
||||
}
|
|
@ -179,6 +179,13 @@ static const struct usb_eth_prob_dev prob_dev[] = {
|
|||
.probe = smsc95xx_eth_probe,
|
||||
.get_info = smsc95xx_eth_get_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_USB_ETHER_RTL8152
|
||||
{
|
||||
.before_probe = r8152_eth_before_probe,
|
||||
.probe = r8152_eth_probe,
|
||||
.get_info = r8152_eth_get_info,
|
||||
},
|
||||
#endif
|
||||
{ }, /* END */
|
||||
};
|
||||
|
|
|
@ -35,7 +35,8 @@ struct dwc2_priv {
|
|||
uint8_t *aligned_buffer;
|
||||
uint8_t *status_buffer;
|
||||
#endif
|
||||
int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
|
||||
u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
|
||||
u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
|
||||
struct dwc2_core_regs *regs;
|
||||
int root_hub_devnum;
|
||||
};
|
||||
|
@ -410,19 +411,29 @@ static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
|
|||
if (dev->speed == USB_SPEED_LOW)
|
||||
hcchar |= DWC2_HCCHAR_LSPDDEV;
|
||||
|
||||
/* Clear old interrupt conditions for this host channel. */
|
||||
writel(0x3fff, &hc_regs->hcint);
|
||||
|
||||
/*
|
||||
* Program the HCCHARn register with the endpoint characteristics
|
||||
* for the current transfer.
|
||||
*/
|
||||
writel(hcchar, &hc_regs->hcchar);
|
||||
|
||||
/* Program the HCSPLIT register for SPLITs */
|
||||
/* Program the HCSPLIT register, default to no SPLIT */
|
||||
writel(0, &hc_regs->hcsplt);
|
||||
}
|
||||
|
||||
static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
|
||||
uint8_t hub_devnum, uint8_t hub_port)
|
||||
{
|
||||
uint32_t hcsplt = 0;
|
||||
|
||||
hcsplt = DWC2_HCSPLT_SPLTENA;
|
||||
hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
|
||||
hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
|
||||
|
||||
/* Program the HCSPLIT register for SPLITs */
|
||||
writel(hcsplt, &hc_regs->hcsplt);
|
||||
}
|
||||
|
||||
/*
|
||||
* DWC2 to USB API interface
|
||||
*/
|
||||
|
@ -713,11 +724,8 @@ static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
|
|||
return stat;
|
||||
}
|
||||
|
||||
int wait_for_chhltd(struct dwc2_core_regs *regs, uint32_t *sub, int *toggle,
|
||||
bool ignore_ack)
|
||||
int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
|
||||
{
|
||||
uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP | DWC2_HCINT_CHHLTD;
|
||||
struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
|
||||
int ret;
|
||||
uint32_t hcint, hctsiz;
|
||||
|
||||
|
@ -727,25 +735,22 @@ int wait_for_chhltd(struct dwc2_core_regs *regs, uint32_t *sub, int *toggle,
|
|||
return ret;
|
||||
|
||||
hcint = readl(&hc_regs->hcint);
|
||||
if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
|
||||
return -EAGAIN;
|
||||
if (ignore_ack)
|
||||
hcint &= ~DWC2_HCINT_ACK;
|
||||
else
|
||||
hcint_comp_hlt_ack |= DWC2_HCINT_ACK;
|
||||
if (hcint != hcint_comp_hlt_ack) {
|
||||
debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
hctsiz = readl(&hc_regs->hctsiz);
|
||||
*sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
|
||||
DWC2_HCTSIZ_XFERSIZE_OFFSET;
|
||||
*toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
|
||||
|
||||
debug("%s: sub=%u toggle=%d\n", __func__, *sub, *toggle);
|
||||
debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
|
||||
*toggle);
|
||||
|
||||
return 0;
|
||||
if (hcint & DWC2_HCINT_XFERCOMP)
|
||||
return 0;
|
||||
|
||||
if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
|
||||
return -EAGAIN;
|
||||
|
||||
debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int dwc2_eptype[] = {
|
||||
|
@ -755,96 +760,176 @@ static int dwc2_eptype[] = {
|
|||
DWC2_HCCHAR_EPTYPE_BULK,
|
||||
};
|
||||
|
||||
static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
|
||||
u8 *pid, int in, void *buffer, int num_packets,
|
||||
int xfer_len, int *actual_len, int odd_frame)
|
||||
{
|
||||
int ret = 0;
|
||||
uint32_t sub;
|
||||
|
||||
debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
|
||||
*pid, xfer_len, num_packets);
|
||||
|
||||
writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
|
||||
(num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
|
||||
(*pid << DWC2_HCTSIZ_PID_OFFSET),
|
||||
&hc_regs->hctsiz);
|
||||
|
||||
if (!in && xfer_len) {
|
||||
memcpy(aligned_buffer, buffer, xfer_len);
|
||||
|
||||
flush_dcache_range((unsigned long)aligned_buffer,
|
||||
(unsigned long)aligned_buffer +
|
||||
roundup(xfer_len, ARCH_DMA_MINALIGN));
|
||||
}
|
||||
|
||||
writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
|
||||
|
||||
/* Clear old interrupt conditions for this host channel. */
|
||||
writel(0x3fff, &hc_regs->hcint);
|
||||
|
||||
/* Set host channel enable after all other setup is complete. */
|
||||
clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
|
||||
DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
|
||||
DWC2_HCCHAR_ODDFRM,
|
||||
(1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
|
||||
(odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
|
||||
DWC2_HCCHAR_CHEN);
|
||||
|
||||
ret = wait_for_chhltd(hc_regs, &sub, pid);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (in) {
|
||||
xfer_len -= sub;
|
||||
|
||||
invalidate_dcache_range((unsigned long)aligned_buffer,
|
||||
(unsigned long)aligned_buffer +
|
||||
roundup(xfer_len, ARCH_DMA_MINALIGN));
|
||||
|
||||
memcpy(buffer, aligned_buffer, xfer_len);
|
||||
}
|
||||
*actual_len = xfer_len;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
|
||||
unsigned long pipe, int *pid, int in, void *buffer, int len,
|
||||
bool ignore_ack)
|
||||
unsigned long pipe, u8 *pid, int in, void *buffer, int len)
|
||||
{
|
||||
struct dwc2_core_regs *regs = priv->regs;
|
||||
struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
|
||||
struct dwc2_host_regs *host_regs = ®s->host_regs;
|
||||
int devnum = usb_pipedevice(pipe);
|
||||
int ep = usb_pipeendpoint(pipe);
|
||||
int max = usb_maxpacket(dev, pipe);
|
||||
int eptype = dwc2_eptype[usb_pipetype(pipe)];
|
||||
int done = 0;
|
||||
int ret = 0;
|
||||
uint32_t sub;
|
||||
int do_split = 0;
|
||||
int complete_split = 0;
|
||||
uint32_t xfer_len;
|
||||
uint32_t num_packets;
|
||||
int stop_transfer = 0;
|
||||
uint32_t max_xfer_len;
|
||||
int ssplit_frame_num = 0;
|
||||
|
||||
debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
|
||||
in, len);
|
||||
|
||||
do {
|
||||
/* Initialize channel */
|
||||
dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
|
||||
eptype, max);
|
||||
max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
|
||||
if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
|
||||
max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
|
||||
if (max_xfer_len > DWC2_DATA_BUF_SIZE)
|
||||
max_xfer_len = DWC2_DATA_BUF_SIZE;
|
||||
|
||||
xfer_len = len - done;
|
||||
if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
|
||||
xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
|
||||
if (xfer_len > DWC2_DATA_BUF_SIZE)
|
||||
xfer_len = DWC2_DATA_BUF_SIZE - max + 1;
|
||||
/* Make sure that max_xfer_len is a multiple of max packet size. */
|
||||
num_packets = max_xfer_len / max;
|
||||
max_xfer_len = num_packets * max;
|
||||
|
||||
/* Make sure that xfer_len is a multiple of max packet size. */
|
||||
if (xfer_len > 0) {
|
||||
num_packets = (xfer_len + max - 1) / max;
|
||||
if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) {
|
||||
num_packets = CONFIG_DWC2_MAX_PACKET_COUNT;
|
||||
xfer_len = num_packets * max;
|
||||
}
|
||||
} else {
|
||||
/* Initialize channel */
|
||||
dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
|
||||
eptype, max);
|
||||
|
||||
/* Check if the target is a FS/LS device behind a HS hub */
|
||||
if (dev->speed != USB_SPEED_HIGH) {
|
||||
uint8_t hub_addr;
|
||||
uint8_t hub_port;
|
||||
uint32_t hprt0 = readl(®s->hprt0);
|
||||
if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
|
||||
DWC2_HPRT0_PRTSPD_HIGH) {
|
||||
usb_find_usb2_hub_address_port(dev, &hub_addr,
|
||||
&hub_port);
|
||||
dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
|
||||
|
||||
do_split = 1;
|
||||
num_packets = 1;
|
||||
max_xfer_len = max;
|
||||
}
|
||||
}
|
||||
|
||||
do {
|
||||
int actual_len = 0;
|
||||
uint32_t hcint;
|
||||
int odd_frame = 0;
|
||||
xfer_len = len - done;
|
||||
|
||||
if (xfer_len > max_xfer_len)
|
||||
xfer_len = max_xfer_len;
|
||||
else if (xfer_len > max)
|
||||
num_packets = (xfer_len + max - 1) / max;
|
||||
else
|
||||
num_packets = 1;
|
||||
|
||||
if (complete_split)
|
||||
setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
|
||||
else if (do_split)
|
||||
clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
|
||||
|
||||
if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
|
||||
int uframe_num = readl(&host_regs->hfnum);
|
||||
if (!(uframe_num & 0x1))
|
||||
odd_frame = 1;
|
||||
}
|
||||
|
||||
if (in)
|
||||
xfer_len = num_packets * max;
|
||||
ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
|
||||
in, (char *)buffer + done, num_packets,
|
||||
xfer_len, &actual_len, odd_frame);
|
||||
|
||||
debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
|
||||
*pid, xfer_len, num_packets);
|
||||
|
||||
writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
|
||||
(num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
|
||||
(*pid << DWC2_HCTSIZ_PID_OFFSET),
|
||||
&hc_regs->hctsiz);
|
||||
|
||||
if (!in && xfer_len) {
|
||||
memcpy(priv->aligned_buffer, (char *)buffer + done,
|
||||
xfer_len);
|
||||
|
||||
flush_dcache_range((unsigned long)priv->aligned_buffer,
|
||||
(unsigned long)((void *)priv->aligned_buffer +
|
||||
roundup(xfer_len, ARCH_DMA_MINALIGN)));
|
||||
hcint = readl(&hc_regs->hcint);
|
||||
if (complete_split) {
|
||||
stop_transfer = 0;
|
||||
if (hcint & DWC2_HCINT_NYET) {
|
||||
ret = 0;
|
||||
int frame_num = DWC2_HFNUM_MAX_FRNUM &
|
||||
readl(&host_regs->hfnum);
|
||||
if (((frame_num - ssplit_frame_num) &
|
||||
DWC2_HFNUM_MAX_FRNUM) > 4)
|
||||
ret = -EAGAIN;
|
||||
} else
|
||||
complete_split = 0;
|
||||
} else if (do_split) {
|
||||
if (hcint & DWC2_HCINT_ACK) {
|
||||
ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
|
||||
readl(&host_regs->hfnum);
|
||||
ret = 0;
|
||||
complete_split = 1;
|
||||
}
|
||||
}
|
||||
|
||||
writel(phys_to_bus((unsigned long)priv->aligned_buffer),
|
||||
&hc_regs->hcdma);
|
||||
|
||||
/* Set host channel enable after all other setup is complete. */
|
||||
clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
|
||||
DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
|
||||
(1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
|
||||
DWC2_HCCHAR_CHEN);
|
||||
|
||||
ret = wait_for_chhltd(regs, &sub, pid, ignore_ack);
|
||||
if (ret)
|
||||
break;
|
||||
|
||||
if (in) {
|
||||
xfer_len -= sub;
|
||||
if (actual_len < xfer_len)
|
||||
stop_transfer = 1;
|
||||
|
||||
invalidate_dcache_range((unsigned long)priv->aligned_buffer,
|
||||
(unsigned long)((void *)priv->aligned_buffer +
|
||||
roundup(xfer_len, ARCH_DMA_MINALIGN)));
|
||||
done += actual_len;
|
||||
|
||||
memcpy(buffer + done, priv->aligned_buffer, xfer_len);
|
||||
if (sub)
|
||||
stop_transfer = 1;
|
||||
}
|
||||
|
||||
done += xfer_len;
|
||||
|
||||
} while ((done < len) && !stop_transfer);
|
||||
/* Transactions are done when when either all data is transferred or
|
||||
* there is a short transfer. In case of a SPLIT make sure the CSPLIT
|
||||
* is executed.
|
||||
*/
|
||||
} while (((done < len) && !stop_transfer) || complete_split);
|
||||
|
||||
writel(0, &hc_regs->hcintmsk);
|
||||
writel(0xFFFFFFFF, &hc_regs->hcint);
|
||||
|
@ -861,14 +946,19 @@ int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
|
|||
{
|
||||
int devnum = usb_pipedevice(pipe);
|
||||
int ep = usb_pipeendpoint(pipe);
|
||||
u8* pid;
|
||||
|
||||
if (devnum == priv->root_hub_devnum) {
|
||||
if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
|
||||
dev->status = 0;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return chunk_msg(priv, dev, pipe, &priv->bulk_data_toggle[devnum][ep],
|
||||
usb_pipein(pipe), buffer, len, true);
|
||||
if (usb_pipein(pipe))
|
||||
pid = &priv->in_data_toggle[devnum][ep];
|
||||
else
|
||||
pid = &priv->out_data_toggle[devnum][ep];
|
||||
|
||||
return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
|
||||
}
|
||||
|
||||
static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
|
||||
|
@ -876,7 +966,8 @@ static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
|
|||
struct devrequest *setup)
|
||||
{
|
||||
int devnum = usb_pipedevice(pipe);
|
||||
int pid, ret, act_len;
|
||||
int ret, act_len;
|
||||
u8 pid;
|
||||
/* For CONTROL endpoint pid should start with DATA1 */
|
||||
int status_direction;
|
||||
|
||||
|
@ -887,31 +978,39 @@ static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
|
|||
setup);
|
||||
}
|
||||
|
||||
/* SETUP stage */
|
||||
pid = DWC2_HC_PID_SETUP;
|
||||
ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8, true);
|
||||
do {
|
||||
ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
|
||||
} while (ret == -EAGAIN);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* DATA stage */
|
||||
act_len = 0;
|
||||
if (buffer) {
|
||||
pid = DWC2_HC_PID_DATA1;
|
||||
ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), buffer,
|
||||
len, false);
|
||||
do {
|
||||
ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
|
||||
buffer, len);
|
||||
act_len += dev->act_len;
|
||||
buffer += dev->act_len;
|
||||
len -= dev->act_len;
|
||||
} while (ret == -EAGAIN);
|
||||
if (ret)
|
||||
return ret;
|
||||
act_len = dev->act_len;
|
||||
} /* End of DATA stage */
|
||||
else
|
||||
act_len = 0;
|
||||
status_direction = usb_pipeout(pipe);
|
||||
} else {
|
||||
/* No-data CONTROL always ends with an IN transaction */
|
||||
status_direction = 1;
|
||||
}
|
||||
|
||||
/* STATUS stage */
|
||||
if ((len == 0) || usb_pipeout(pipe))
|
||||
status_direction = 1;
|
||||
else
|
||||
status_direction = 0;
|
||||
|
||||
pid = DWC2_HC_PID_DATA1;
|
||||
ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
|
||||
priv->status_buffer, 0, false);
|
||||
do {
|
||||
ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
|
||||
priv->status_buffer, 0);
|
||||
} while (ret == -EAGAIN);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
@ -968,8 +1067,10 @@ static int dwc2_init_common(struct dwc2_priv *priv)
|
|||
DWC2_HPRT0_PRTRST);
|
||||
|
||||
for (i = 0; i < MAX_DEVICE; i++) {
|
||||
for (j = 0; j < MAX_ENDPOINT; j++)
|
||||
priv->bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
|
||||
for (j = 0; j < MAX_ENDPOINT; j++) {
|
||||
priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
|
||||
priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -500,6 +500,7 @@ struct dwc2_core_regs {
|
|||
#define DWC2_HFNUM_FRNUM_OFFSET 0
|
||||
#define DWC2_HFNUM_FRREM_MASK (0xFFFF << 16)
|
||||
#define DWC2_HFNUM_FRREM_OFFSET 16
|
||||
#define DWC2_HFNUM_MAX_FRNUM 0x3FFF
|
||||
#define DWC2_HPTXSTS_PTXFSPCAVAIL_MASK (0xFFFF << 0)
|
||||
#define DWC2_HPTXSTS_PTXFSPCAVAIL_OFFSET 0
|
||||
#define DWC2_HPTXSTS_PTXQSPCAVAIL_MASK (0xFF << 16)
|
||||
|
|
|
@ -5,6 +5,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk.h>
|
||||
#include <dm.h>
|
||||
#include "ehci.h"
|
||||
|
||||
|
@ -21,6 +22,19 @@ static int ehci_usb_probe(struct udevice *dev)
|
|||
{
|
||||
struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev);
|
||||
struct ehci_hcor *hcor;
|
||||
int i;
|
||||
|
||||
for (i = 0; ; i++) {
|
||||
struct udevice *clk_dev;
|
||||
int clk_id;
|
||||
|
||||
clk_id = clk_get_by_index(dev, i, &clk_dev);
|
||||
if (clk_id < 0)
|
||||
break;
|
||||
if (clk_enable(clk_dev, clk_id))
|
||||
printf("failed to enable clock (dev=%s, id=%d)\n",
|
||||
clk_dev->name, clk_id);
|
||||
}
|
||||
|
||||
hcor = (struct ehci_hcor *)((uintptr_t)hccr +
|
||||
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
|
||||
|
|
|
@ -88,6 +88,9 @@
|
|||
#define CONFIG_USB_HOST_ETHER
|
||||
#define CONFIG_USB_ETHER_SMSC95XX
|
||||
#define CONFIG_MISC_INIT_R
|
||||
#define CONFIG_USB_KEYBOARD
|
||||
#define CONFIG_SYS_USB_EVENT_POLL
|
||||
#define CONFIG_SYS_STDIO_DEREGISTER
|
||||
#endif
|
||||
|
||||
/* Console UART */
|
||||
|
@ -111,6 +114,7 @@
|
|||
#define CONFIG_SYS_LOAD_ADDR 0x1000000
|
||||
#define CONFIG_CONSOLE_MUX
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
#define CONFIG_PREBOOT "usb start"
|
||||
|
||||
/* Shell */
|
||||
#define CONFIG_SYS_MAXARGS 8
|
||||
|
@ -133,7 +137,7 @@
|
|||
/* Environment */
|
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
#define ENV_DEVICE_SETTINGS \
|
||||
"stdin=serial,lcd\0" \
|
||||
"stdin=serial,usbkbd\0" \
|
||||
"stdout=serial,lcd\0" \
|
||||
"stderr=serial,lcd\0"
|
||||
|
||||
|
|
|
@ -131,6 +131,12 @@ int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
|
|||
struct ueth_data *ss);
|
||||
int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
|
||||
struct eth_device *eth);
|
||||
|
||||
void r8152_eth_before_probe(void);
|
||||
int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
|
||||
struct ueth_data *ss);
|
||||
int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
|
||||
struct eth_device *eth);
|
||||
#endif
|
||||
|
||||
#endif /* __USB_ETHER_H__ */
|
||||
|
|
Loading…
Reference in a new issue