Commit graph

85816 commits

Author SHA1 Message Date
Linus Walleij
eb3a6e3283 nand: brcmnand: add iproc support
Add support for the iproc Broadcom NAND controller,
used in Northstar SoCs for example. Based on the Linux
driver.

Cc: Philippe Reynes <philippe.reynes@softathome.com>
Cc: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: William Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/all/20230308214231.378013-1-linus.walleij@linaro.org/
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-04-16 12:28:06 +02:00
Linus Walleij
ff33d3c87c mtd: rawnand: nand_base: Handle algorithm selection
For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the
D-Link DIR-885L and DIR-890L routers, we need to explicitly
select the ECC like this in the device tree:

  nand-ecc-algo = "bch";
  nand-ecc-strength = <1>;
  nand-ecc-step-size = <512>;

This is handled by the Linux kernel but U-Boot core does
not respect this. Fix it up by parsing the algorithm and
preserve the behaviour using this property to select
software BCH as far as possible.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: William Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/all/20230308212851.370939-1-linus.walleij@linaro.org/
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-04-16 12:25:36 +02:00
Frieder Schrempf
28b395ccc4 MAINTAINERS: Rename NAND FLASH to RAW NAND
As there are other types of NAND flashes like SPI NAND, let's be
more specific.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Link: https://lore.kernel.org/all/20230213094626.50957-2-frieder@fris.de/
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-04-16 12:24:59 +02:00
Frieder Schrempf
175bc1c65b MAINTAINERS: Add entry for SPI NAND framework and drivers
In [1] Michael agreed on taking patches for SPI NAND through the RAW
NAND tree. Add a dedicated entry to the MAINTAINERS file which adds
Michael and Dario as maintainers and myself as reviewer.

[1] https://lists.denx.de/pipermail/u-boot/2023-February/508571.html

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
Cc: Tom Rini <trini@konsulko.com>
Link: https://lore.kernel.org/all/20230213094626.50957-1-frieder@fris.de/
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-04-16 12:24:33 +02:00
Tom Rini
12c1e57824 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-marvell
- mvebu: Boot support for 4K Native disks (Pali)
- a38x: Perform DDR training sequence again for 2nd boot (Tony)
2023-04-14 10:50:55 -04:00
Tom Rini
75f415b326 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
The biggest change is some refactoring of the H616 DRAM driver, which
allows better fine-tuning for each board, and is the base for pending
LPDDR3 and LPDDR4 support, needed by new boards.  The sun8i-emac
Ethernet driver sees some refactoring that enables it for the Allwinner
D1 EMAC IP. The sunxi HDMI driver is now using more DT properties. Also
the early SPL code now supports some odd H616 SoC variant.

There are some more patches pending, that require the final review
touches and some testing, I will send a separate PR for them later.

The gitlab CI completed successfully, and I boot tested a few boards
with different SoCs, via FEL and SD card, into Linux.
2023-04-14 10:50:04 -04:00
Tony Dinh
6add83991b ddr: marvell: a38x: Perform DDR training sequence again for 2nd boot
- DDR Training sequence happens very fast. The speedup in boot time is
negligible by skipping the training sequence during 2nd boot or after.
So remove the check and skip.
- This change improves the robustness of DDR training. If u-boot crashed
during DDR training, the training could be left in a limbo state, where
the BootROM has recorded that it is already in a 2nd boot. The training
must be repeated in this scenario to get out of this limbo state, but due
to the check it cannot be performed.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-04-13 11:34:47 +02:00
Pali Rohár
c62af15393 arm: mvebu: spl: Allow to build SATA kwbimage for 4K Native disks
Add a new config option CONFIG_MVEBU_SPL_SATA_BLKSZ for specifying block
size of SATA disk. This information is used during building of SATA
kwbimage and must be correctly set, otherwise BootROM does not load SPL.

For 4K Native disks CONFIG_MVEBU_SPL_SATA_BLKSZ must be set to 4096.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
2023-04-13 11:34:47 +02:00
Pali Rohár
5d8178563b tools: kwboot: Add support for parsing SATA images with non-512 block size
Currently kwboot expected that sector size for SATA image is always 512
bytes. If SATA image cannot be parsed with sector size of 512 bytes, try
larger sector sizes which are power of two and up to the 32 kB. Maximal
theoretical value is 32 kB because ATA IDENTIFY command returns sector size
as 16-bit number.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-04-13 11:34:47 +02:00
Pali Rohár
11af96d7e6 tools: kwbimage: Add support for SATA images with non-512 byte block size
SATA kwbimage contains offsets in block size unit, not in bytes.

Until now kwbimage expected that SATA disk always have block size of 512
bytes. But there are 4K Native SATA disks with block size of 4096 bytes.

New SATA_BLKSZ command allows to specify different block size than 512
bytes and therefore allows to generate kwbimage for disks with different
block sizes.

This change add support for generating SATA images with different block
size. Also it add support for verifying and dumping such images.

Because block size itself is not stored in SATA kwbimage, image
verification is done by checking every possible block size (it is any
power of two value between 512 and 32 kB).

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-04-13 11:34:47 +02:00
Pali Rohár
62d81d68d2 tools: kwbimage: Simplify align code
Replace repeated code patterns by generic code.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-04-13 11:34:47 +02:00
Pali Rohár
2972d7d62f tools: imagetool: Extend print_header() by params argument
This allows image type print_header() callback to access struct
image_tool_params *params.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-13 11:34:47 +02:00
Pali Rohár
4548b37a29 cmd: mvebu/bubt: a38x: Do not hardcode SATA block size to 512
Find SATA block device by blk_get_devnum_by_uclass_id() function and read
from it the real block size of the SATA disk. In case of error, fallback
back to 512 bytes.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-04-13 11:34:47 +02:00
Pali Rohár
fa06a6df65 arm: mvebu: spl: Do not hardcode SATA block size to 512
Find SATA block device by blk_get_devnum_by_uclass_id() function and read
from it the real block size of the SATA disk.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-04-13 11:34:24 +02:00
Andre Przywara
5fc892e83f sunxi: A64: drop boot0 header reservation
In the early days of the Allwinner A64 U-Boot support, we relied on a
vendor provided "boot0" binary to perform the DRAM initialisation. This
replaced the SPL, and required to equip the U-Boot (proper) binary with
a vendor specific header to be recognised as a valid boot0 payload.
Fortunately these days are long gone (we gained SPL and DRAM support in
early 2017!), and we never needed to use that hack on any later 64-bit
Allwinner SoC.

Since this is highly obsolete by now, remove that option from the
defconfigs of all A64 boards. We leave the code still in here for now,
since some people expressed their interest in this.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-12 00:17:22 +01:00
Andre Przywara
0a137ac501 sunxi: arm64: boot0.h: runtime check for RVBAR address
Some SoCs of the H616 family use a die variant, that puts some CPU power
and reset control registers at a different address. There are examples
of two instances of the same board, using different die revisions of the
otherwise same H313 SoC. We need to write to a register in that block
*very* early in the SPL boot, to switch the core to AArch64.

Since the devices are otherwise indistinguishable, let the SPL code read
that die variant and use the respective RVBAR address based on that.
That is a bit tricky, since we need to do that in hand-coded AArch32
machine language, shared by all 64-bit SoCs. To avoid build dependencies
in this mess, we always provide two addresses to choose from, and just
give identical values for all other SoCs. This allows the same code to
run on all 64-bit SoCs, and controls this switch behaviour purely from
Kconfig.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-12 00:17:22 +01:00
Andre Przywara
342abc1472 sunxi: boot0.h: allow RVBAR MMIO address customisation
To switch the ARMv8 Allwinner SoCs into the 64-bit AArch64 ISA, we need
to program the 64-bit start code address into an MMIO mapped register
that shadows the architectural RVBAR register.
This address is SoC specific, with just two versions out there so far.
Now a third address emerged, on a *variant* of an existing SoC (H616).

Change the boot0.h start code to make this address a Kconfig
selectable option, to allow easier maintenance.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-12 00:17:22 +01:00
Jernej Skrabec
deb77f18bf sunxi: Add TPR2 parameter for H616 DRAM driver
It turns out that some H616 and related SoCs (like H313) need TPR2
parameter for proper working. Add it.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:22 +01:00
Jernej Skrabec
4a967cb95f sunxi: Parameterize some of H616 DDR3 timings
Currently twr2rd, trd2wr and twtp are constants, but according to
vendor driver they are calculated from other values. Do that here too,
in preparation for later introduction of new parameter.

While at it, introduce constant for t_wr_lat, which was incorrectly
calculated from tcl before.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:22 +01:00
Jernej Skrabec
b3cb03cf79 sunxi: Parameterize "unknown feature" in H616 DRAM driver
Part of the code, previously known as "unknown feature", also doesn't
have constant values. They are derived from TPR0 parameter in vendor
DRAM code.

Let's move that code to separate function and introduce TPR0 parameter
here too, to ease adding new boards.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Jernej Skrabec
ae6f66d5b5 sunxi: Parameterize bit delay code in H616 DRAM driver
These values are highly board specific and thus make sense to add
parameter for them. To ease adding support for new boards, let's make
them same as in vendor DRAM settings.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Jernej Skrabec
83118bfa04 sunxi: Make bit delay function in H616 DRAM code void
Mentioned function result is always true and result isn't checked
anyway. Let's make it void.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Jernej Skrabec
7742eac7af sunxi: Always configure ODT on H616 DRAM
Vendor H616 DRAM code always configure part which we call ODT
configuration. Let's reflect that here too.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Jernej Skrabec
f221411caa sunxi: Convert H616 DRAM options to single setting
Vendor DRAM settings use TPR10 parameter to enable various features.
There are many mores features that just those that are currently
mentioned. Since new will be added later and most are not known, let's
reuse value from vendor DRAM driver as-is. This will also help adding
support for new boards.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Jernej Skrabec
f35ec2105e sunxi: parameterize H616 DRAM ODT values
While ODT values for same memory type are similar, they are not
necessary the same. Let's parameterize them and make parameter same as
in vendor DRAM settings. That way it will be easy to introduce new board
support.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Jernej Skrabec
cdb5aadd59 sunxi: cosmetic: Fix H616 DRAM driver code style
Fix code style for pointer declaration. This is just cosmetic change to
avoid checkpatch errors in later commits.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Jernej Skrabec
7230bebfe3 sunxi: Fix write to H616 DRAM CR register
Vendor DRAM code actually writes to whole CR register and not just sets
bit 31 in mctl_ctrl_init().

Just to be safe, do that here too.

Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Samuel Holland
f050069297 ARM: dts: sun6i: mixtile-loftq: Add USB1 VBUS regulator
This board is configured with CONFIG_USB1_VBUS_PIN="PH24", but no
regulator exists in its device tree. Add the regulator, so USB will
continue to work when the PHY driver switches to using the regulator
uclass instead of a GPIO.

Update the device tree here because it does not exist in Linux.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Samuel Holland
93f93fe4cd net: sun8i-emac: Remove the SoC variant ID
Now that all differences in functionality are covered by individual
flags, remove the enumeration of SoC variants.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Samuel Holland
3cfb1e6914 net: sun8i-emac: Use common syscon setup for R40
While R40 puts the EMAC syscon register at a different address from
other variants, the relevant portion of the register's layout is the
same. Factor out the register offset so the same code can be shared
by all variants. This matches what the Linux driver does.

This change provides two benefits beyond the simplification:
 - R40 boards now respect the RX delays from the devicetree
 - This resolves a warning on architectures where readl/writel
   expect the address to have a pointer type, not phys_addr_t.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Samuel Holland
0e148342f7 net: sun8i-emac: Add a flag for the internal PHY switch
Describe this feature instead of using the SoC ID.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Samuel Holland
c5ac4b160f net: sun8i-emac: Add a flag for RMII support
Describe this feature instead of using the SoC ID.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:21 +01:00
Samuel Holland
c86d47328e net: sun8i-emac: Add a structure for variant data
Currently, EMAC variants are distinguished by their identity, but this
gets unwieldy as more overlapping variants are added. Add a structure so
we can describe the individual feature differences between the variants.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12 00:17:20 +01:00
Samuel Holland
f5ee1ea864 video: sunxi: dw-hdmi: Use DM for HVCC regulator
The HDMI PHY depends on the HVCC supply being enabled. So far we have
relied on it being enabled by an earlier firmware stage (SPL or TF-A).
Attempt to enable the regulator here, so we can remove that dependency.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-12 00:17:20 +01:00
Samuel Holland
7108dd2443 video: sunxi: dw-hdmi: Use DM for clock gates and resets
This abstracts away the CCU register layout, which is necessary for
supporting new SoCs like H6 with a reorganized CCU. One of the resets is
referenced from the PHY node instead of the controller node, so it will
have to wait until the PHY code is factored out to a separate driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-12 00:17:20 +01:00
Tom Rini
9e804638bf Merge tag 'for-v2023-07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c updates for v2023-07-rc1

- designware_i2c: remove apparently redundant read of 'i2c, speeds' DT property
  from Rasmus Villemoes

- fix: correct I2C deblock logic from Haibo Chen

- imx_lpi2c: Fix misuse the IS_ENABLED for DM clock from Ye Li

- m68k: convert to DM from Angelo Dureghello
2023-04-11 09:29:28 -04:00
Angelo Dureghello
5cf0086372 m68k: upgrading all boards to dm i2c
Upgrading all board configs where i2c is involved to DM i2c.

Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
2023-04-11 06:52:11 +02:00
Angelo Dureghello
96283b83da m68k: dts: add i2c nodes
Add all the i2c nodes for each family, and add specific i2c
overwrites in the related board-specific dts.

Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
2023-04-11 06:52:05 +02:00
Angelo Dureghello
b6afa7cf62 i2c: fsl_i2c: fix m68k transferts
This driver is actually used for powerpc and m68k/ColdFire.

On ColdFire SoC's, interrupt flag get not set if IIEN flag (mbcr bit6,
interrupt enabled) is not set appropriately before each transfert.
As a result, the transfert hangs forever waiting for IIEN.
This patch set IIEN before each transfert, while considering this fix
as not harming powerpc arch.

Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
2023-04-11 06:51:56 +02:00
Angelo Dureghello
987e20e593 m68k: mcf5441x: fix CONFIG_SYS_FSL_I2C definition
Fix CONFIG_SYS_FSL_I2C to correct name CONFIG_SYS_I2C_FSL.

Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
2023-04-11 06:51:51 +02:00
Angelo Dureghello
db457e682a board: stmark2: add i2c0 pinmux pad configuration
Add CFG option to enable proper pinmux pad setting for i2c0.

Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
2023-04-11 06:51:38 +02:00
Angelo Dureghello
5d3a5f330d m68k: move CONFIG_SYS_I2C to CFG_ namespace
Move CONFIG_SYS_I2C_X to CFG_ namespace.
This is a preliminary step to move to dm i2c.

Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
2023-04-11 06:50:57 +02:00
Ye Li
b4004c2949 i2c: imx_lpi2c: Fix misuse the IS_ENABLED for DM clock
The IS_ENABLED, which does not consider SPL build, should be replaced
by CONFIG_IS_ENABLED.
For the case that we only enable DM CLK for u-boot but not in SPL, the
IS_ENABLED(CONFIG_CLK) still returns true, then cause clock failure.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-04-11 06:45:29 +02:00
Haibo Chen
7f6a2e6e0f i2c: correct I2C deblock logic
Current code use dm_gpio_get_value() to get SDA and SCL value, and the
value depends on whether DTS file config the GPIO_ACTIVE_LOW. In ususal
case for i2c GPIO, DTS need to set GPIO_ACTIVE_LOW for SCL/SDA pins. So
here the logic is not correct.

And we must not use GPIOD_ACTIVE_LOW in client code include the
dm_gpio_set_dir_flags(), it is DTS's responsibility for this flag. So
remove GPIOD_ACTIVE_LOW here.

Fixes: aa54192d4a ("dm: i2c: implement gpio-based I2C deblock")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Alexander Kochetkov <al.kochet@gmail.com <mailto:al.kochet@gmail.com>>
2023-04-11 06:44:39 +02:00
Rasmus Villemoes
d600b0fcbb i2c: designware_i2c: remove apparently redundant read of 'i2c, speeds' DT property
This code first figures out if there is an i2c,speeds property, if so
its size in u32s, and then reads the value into the local speeds[]
array. Both 'size' and 'speeds' are completely unused thereafter.

It's not at all clear what this is supposed to do. Of course, it could
be seen as a sanity check that the DT node does have an i2c,speeds
property with an appropriate number of elements, but for that one
wouldn't actually need to read it into speeds[]. Also, I can't find
anywhere else in the U-Boot code which makes use of values from that
property (this is is the only C code referencing "i2c,speeds"), so it
seems pointless to insist that it's there.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2023-04-11 06:43:33 +02:00
Tom Rini
11c25c6df0 Merge https://source.denx.de/u-boot/custodians/u-boot-mmc 2023-04-10 08:32:11 -04:00
Pali Rohár
fbf368f176 cmd: mmc: Return CMD_RET_* from commands
Numeric return values may cause strange errors line:
exit not allowed from main input shell.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-10 12:18:45 +09:00
Pali Rohár
8b88206696 mmc: Use EXT_CSD_EXTRACT_BOOT_PART() macro for extracting boot part
Mask macro PART_ACCESS_MASK filter out access bits of emmc register and
macro EXT_CSD_EXTRACT_BOOT_PART() extracts boot part bits of emmc register.
So use EXT_CSD_EXTRACT_BOOT_PART() when extracting boot partition.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-10 12:18:17 +09:00
Stefan Roese
8af21b094d mmc: mv_sdhci: Depend on DM_MMC
All build targets using this driver already use DM_MMC. So let's depend
this driver on this Kconfig symbol and remove the non-DM driver part.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-04-10 12:17:58 +09:00
Stefan Roese
c06a568473 mmc: mv_sdhci: Remove CONFIG_MMC_SDHCI_IO_ACCESSORS support
CONFIG_MMC_SDHCI_IO_ACCESSORS is not supported and/or used by this
driver so let's remove these unused parts completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-04-10 12:17:50 +09:00