Commit graph

197 commits

Author SHA1 Message Date
Michael Walle
285edfd782 mmc: fsl_esdhc: remove 1ms sleep in esdhc_send_cmd_common()
Since the beginning of this driver which was initially for the MPC8379
and MPC8536 SoCs, there is this spurious 1ms delay. According to the
comment it should actually be only 8 clock cycles. Esp. during EFI block
transfers, this 1ms add up to a significant delay and slows down EFI
boot.

I couldn't find any mention in the MPC8536 that there should be a delay
of 8 clock cycles between commands. The SD card specification mentions that
the clock has to be left enabled for 8 cycles after a command or
response. But I don't see how this delay will help with this.

Go ahead and just remove it. If there will ever be any regression we can
introduce a compile time flag, but for now I'd like to keep it simple.

In the split off imx driver this delay was also removed in commit
9098682200 ("mmc: fsl_esdhc_imx: remove the 1ms delay before sending
command").

Signed-off-by: Michael Walle <michael@walle.cc>
2021-09-13 11:46:50 +08:00
Yangbo Lu
ae7020b435 mmc: fsl_esdhc: convert to CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT
For eSDHC, power supply is through peripheral circuit.
Some eSDHC versions have value 0 of the bit but that
does not reflect the truth. 3.3V is common for SD/MMC,
and is supported for all boards with eSDHC in current
u-boot. So, make 3.3V is supported in default in code.
CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT can be enabled if
future board does not support 3.3V.

This is also a fix-up for one previous patch, which converted
to use IS_ENABLED() for CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
that is not a Kconfig option.

Fixes: 52faec3182 ("mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()")
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17 11:46:11 +05:30
Michael Walle
d3b745f7d0 mmc: fsl_esdhc: add pulse width detection workaround
HS400 mode on the LS1028A SoC isn't reliable. The linux driver has a
workaroung for the pulse width detection. Apply this workaround in
u-boot, too.

This will make HS400 mode work reliably on the LS1028A SoC.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-04-06 18:36:04 +08:00
Michael Walle
bd7b8505f2 mmc: fsl_esdhc: add workaround for erratum A-011334
LS1028A SoCs are restricted in what divider values are allowed for HS400
mode. This is basically a port from the corresponding linux driver.

Signed-off-by: Michael Walle <michael@walle.cc>
2021-04-06 18:35:55 +08:00
Simon Glass
401d1c4f5d common: Drop asm/global_data.h from common header
Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-02-02 15:33:42 -05:00
Simon Glass
c69cda25c9 dm: treewide: Rename dev_get_platdata() to dev_get_plat()
Rename this to be consistent with the change from 'platdata'.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:09 -07:00
Simon Glass
caa4daa2ae dm: treewide: Rename 'platdata' variables to just 'plat'
We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).

Rename some of the latter variables to end with 'plat' for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:08 -07:00
Simon Glass
41575d8e4c dm: treewide: Rename auto_alloc_size members to be shorter
This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.

Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 08:00:25 -07:00
Yangbo Lu
8ee802f899 mmc: fsl_esdhc: make sure delay chain locked for HS400
For eMMC HS400 mode, the DLL reset is a required step for mmc rescan.
This step has not been documented in reference manual, but the RM will
be fixed sooner or later.

In previous commit to support eMMC HS400,
  db8f936 mmc: fsl_esdhc: support eMMC HS400 mode

the steps to configure DLL could be found in commit message,
  13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL].
  14. Wait for delay chain to lock.

these would be fixed as,
  13.   Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL].
  13.1  Write DLLCFG0[DLL_RESET] to 1 and wait for 1us,
        then write DLLCFG0[DLL_RESET]
  14.   Wait for delay chain to lock.

This patch is to add the step of DLL reset, and make sure delay chain
locked for HS400.

Fixes: db8f93672b ("mmc: fsl_esdhc: support eMMC HS400 mode")
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-11-28 10:39:44 +08:00
Yangbo Lu
263ddfc345 mmc: fsl_esdhc: set sysctl register for clock initialization
The initial clock setting should be through sysctl register only,
while the mmc_set_clock() will call mmc_set_ios() introduce other
configurations like bus width, mode, and so on.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-11-28 10:39:44 +08:00
Michael Walle
361a422b90 mmc: fsl_esdhc: add ADMA2 support
Newer eSDHC controllers support ADMA2 descriptor tables which support
64bit DMA addresses. One notable user of addresses in the upper memory
segment is the EFI loader.

If support is enabled, but the controller doesn't support ADMA2, we
will fall back to SDMA (and thus 32 bit DMA addresses only).

Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-14 14:00:44 +08:00
Michael Walle
52faec3182 mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()
Make the code cleaner and drop the old-style #ifdef constructs where it is
possible.

Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-14 14:00:37 +08:00
Michael Walle
7e48a028a4 mmc: fsl_esdhc: simplify esdhc_setup_data()
First, we need the waterlevel setting for PIO mode only. Secondy, both DMA
setup code is identical for both directions, except for the data pointer.
Thus, unify them.

Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-12 15:49:18 +08:00
Michael Walle
b1ba1460a4 mmc: fsl_esdhc: use dma-mapping API
Use the dma_{map,unmap}_single() calls. These will take care of the
flushing and invalidation of caches.

Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-12 15:49:09 +08:00
Michael Walle
da86e8cfcb mmc: fsl_esdhc: simplify 64bit check for SDMA transfers
SDMA can only do DMA with 32 bit addresses. This is true for all
architectures (just doesn't apply to 32 bit ones). Simplify the code and
remove unnecessary CONFIG_FSL_LAYERSCAPE.

Also make the error message more concise.

Signed-off-by: Michael Walle <michael@walle.cc>
2020-10-12 15:48:50 +08:00
Yangbo Lu
78804de483 mmc: fsl_esdhc: fix eMMC HS400 stability issue
There was a fix-up for eMMC HS400 stability issue in Linux.

Patch link:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
commit/?id=58d0bf843b49fa99588ac9f85178bd8dfd651b53

Description:
Currently only LX2160A eSDHC supports eMMC HS400. According to
a large number of tests, eMMC HS400 failed to work at 150MHz,
and for a few boards failed to work at 175MHz. But eMMC HS400
worked fine on 200MHz. We hadn't found the root cause but
setting eSDHC_DLLCFG0[DLL_FREQ_SEL] = 0 using slow delay chain
seemed to resovle this issue. Let's use this as fixup for now.

Introduce the fix-up in u-boot since the issue could be reproduced
in u-boot too.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12 15:47:06 +08:00
Yangbo Lu
30f6444d02 mmc: fsl_esdhc: fix mmc->clock with actual clock
Fix mmc->clock with actual clock which is divided by the
controller, and record it with priv->clock which was removed
accidentally.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12 15:47:05 +08:00
Yangbo Lu
db8f93672b mmc: fsl_esdhc: support eMMC HS400 mode
The process for eMMC HS400 mode for eSDHC is,

1. Perform the Tuning Process at the HS400 target operating frequency.
   Latched the clock division value.
2. if read transaction, then set the SDTIMNGCTL[FLW_CTL_BG].
3. Switch to High Speed mode and then set the card clock frequency to
   a value not greater than 52Mhz
4. Clear TBCTL[TB_EN],tuning block enable bit.
5. Change to 8 bit DDR Mode
6. Switch the card to HS400 mode.
7. Set TBCTL[TB_EN], tuning block enable bit.
8. Clear SYSCTL[SDCLKEN]
9. Wait for PRSSTAT[SDSTB] to be set
10. Change the clock division to latched value.Set TBCTL[HS 400 mode]
    and Set SDCLKCTL[CMD_CLK_CTRL]
11. Set SYSCTL[SDCLKEN]
12. Wait for PRSSTAT[SDSTB] to be set
13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL].
14. Wait for delay chain to lock.
15. Set TBCTL[HS400_WNDW_ADJUST]
16. Again clear SYSCTL[SDCLKEN]
17. Wait for PRSSTAT[SDSTB] to be set
18. Set ESDHCCTL[FAF]
19. Wait for ESDHCCTL[FAF] to be cleared
20. Set SYSCTL[SDCLKEN]
21. Wait for PRSSTAT[SDSTB] to be set.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12 15:46:34 +08:00
Yangbo Lu
1b5f0ba7a5 mmc: fsl_esdhc: clean TBCTL[TB_EN] manually during init
Clean TBCTL[TB_EN] manually during init since it is not able to
be reset by reset all operation.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12 15:46:30 +08:00
Yangbo Lu
b1a4247b41 mmc: fsl_esdhc: support tuning for eMMC HS200
Support tuning process for eMMC HS200 for eSDHC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-10-12 15:46:29 +08:00
Yangbo Lu
1fdefd1d0d mmc: fsl_esdhc: add a reinit() callback
Add a reinit() callback for mmc rescan.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-12 15:45:40 +08:00
Yangbo Lu
39913acedd Move eSDHC adapter card identification to board files
The eSDHC adapter card identification and multiplexing configuration
through FPGA had been implemented in both common mmc driver and
fsl_esdhc driver. However it is proper to move these code to board
files and do it during board initialization. The FPGA registers are
also board specific.

This patch is to move eSDHC adapter card identification and
multiplexing configuration from mmc driver to specific board files.
And the option CONFIG_FSL_ESDHC_ADAPTER_IDENT is no longer needed.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
[Rebased, Removed T1040QDS change as board does not exist]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:28 +05:30
Yangbo Lu
4f73897b99 Drop global data sdhc_adapter for powerpc
The sdhc_adapter of global data has not been used, and we
do not have to use it as global data even we may need it
in the future.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:28 +05:30
Masahiro Yamada
b75d8dc564 treewide: convert bd_t to struct bd_info by coccinelle
The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:

  It's a **mistake** to use typedef for structures and pointers.

Besides, using typedef for structures is annoying when you try to make
headers self-contained.

Let's say you have the following function declaration in a header:

  void foo(bd_t *bd);

This is not self-contained since bd_t is not defined.

To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h>

  #include <asm/u-boot.h>
  void foo(bd_t *bd);

Then, the include direcective pulls in more bloat needlessly.

If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:

  struct bd_info;
  void foo(struct bd_info *bd);

Right, typedef'ing bd_t is a mistake.

I used coccinelle to generate this commit.

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  typedef bd_t;
  @@
  -bd_t
  +struct bd_info
  </smpl>

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2020-07-17 09:30:13 -04:00
Yangbo Lu
c927d65873 mmc: fsl_esdhc: workaround for hardware 3.3v IO reliability issue
When eSDHC operates at 3.3v, damage can accumulate in an internal
level shifter at a higher than expected rate. The faster the interface
runs, the more damage accumulates. This issue now is found on LX2160A
eSDHC1 for only SD card.

The hardware workaround is recommended to use an on-board level shifter
that is 1.8v on SoC side and 3.3v on SD card side.

For boards without hardware workaround, this option could be enabled,
ensuring 1.8v IO voltage and disabling eSDHC if no card.
This option assumes no hotplug, and u-boot has to make all the way to
to linux to use 1.8v UHS-I speed mode if has card.
If you do not want the workaround for better user experience, of course
you can choose to not select it running eSDHC in unsafe mode.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2020-06-15 09:45:22 +08:00
Yangbo Lu
9abf648436 mmc: fsl_esdhc: read register once for card inserted status
No need to poll register for card inserted status.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2020-06-15 09:45:22 +08:00
Simon Glass
cd93d625fd common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
c05ed00afb common: Drop linux/delay.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
90526e9fba common: Drop net.h from common header
Move this header out of the common header. Network support is used in
quite a few places but it still does not warrant blanket inclusion.

Note that this net.h header itself has quite a lot in it. It could be
split into the driver-mode support, functions, structures, checksumming,
etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:31 -04:00
Rasmus Villemoes
ede2822864 mmc: fsl_esdhc: actually enable cache snooping on mpc830x
The reference manuals for MPC8308 and MPC8309 both say that the
esdhcctl aka DMA Control Register "is implemented as SDHCCR" in the
System configuration registers. Unfortunately, that doesn't mean that
the registers are just mirrors of each other - any write to esdhcctl
is simply ignored. So to actually enable cache snooping, we
unfortunately have to add a little ifdeffery.

There is, naturally, no description of the bit fields of esdhcctl in
the MPC8309 manual, but comparing the description of esdhcctl from the
LS1021A reference manual to the description of the sdhccr in MPC8309,
one also finds that the fields are bit-reversed, so the bit to set is
0x02000000 rather than 0x00000040 - this is also what board_mmc_init()
uses in the two gdsys/mpc8308/ boards.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-02-19 21:21:42 +08:00
Simon Glass
336d4615f8 dm: core: Create a new header file for 'compat' features
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.

Move the compatibility features into a separate header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Yangbo Lu
f1bce08426 Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage
The eSDHC reference clocks should be provided by speed.c in arch/.
And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to
select which clock to use. Because we can make the driver to select
the periperhal clock which is better (provides higher frequency)
automatically if its value is provided by speed.c.

This patch is to drop this option and make driver to select clock
automatically. Also fix peripheral clock calculation issue in
fsl_lsch2_speed.c/fsl_lsch3_speed.c.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-01-16 13:20:33 +08:00
Yangbo Lu
7fdcbac5d6 mmc: fsl_esdhc: drop useless fdt fixup
The fdt fixup for properties "peripheral-frequency" and "adapter-type"
was once for a Freescale SDK release. The properties haven't been existed
in linux mainline. Drop these useless code.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-01-16 13:16:24 +08:00
Simon Glass
1eb69ae498 common: Move ARM cache operations out of common.h
These functions are CPU-related and do not use driver model. Move them to
cpu_func.h

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:24:58 -05:00
Yangbo Lu
5e81cbff37 mmc: fsl_esdhc: get clock directly from global data
This patch is to get clock directly from global data.

- Remove uclass clk api method. This was what i.MX platforms were
  using, while QorIQ platforms weren't.
- Get clock only from global data, dropping mxc_get_clock().
  QorIQ eSDHC controllers on one silicon use same reference clock.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-27 16:55:56 +08:00
Yangbo Lu
618704753e mmc: fsl_esdhc: clean up DM and non-DM code
Make DM and non-DM code clear using below structure.
	#if !CONFIG_IS_ENABLED(DM_MMC)
		<non-DM_MMC code>
	#else
		<DM_MMC code>
	#endif

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:25 +08:00
Yangbo Lu
0cc127c424 mmc: fsl_esdhc: always check write protect state
The QorIQ eSDHC on all platforms supports checking write protect
state through register bit. So check it always.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:25 +08:00
Yangbo Lu
08197cb8df mmc: fsl_esdhc: drop redundant code for non-removable feature
Drop redundant code for non-removable feature. "non-removable" property
has been read in mmc_of_parse().

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:25 +08:00
Yangbo Lu
5705973b09 mmc: fsl_esdhc: convert to use fsl_esdhc_get_cfg_common()
The fsl_esdhc_init() was actually to get configuration of mmc_config.
So rename it to fsl_esdhc_get_cfg_common() and make it common for both
DM_MMC and non-DM_MMC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:25 +08:00
Yangbo Lu
07bae1de38 mmc: fsl_esdhc: clean up bus width configuration code
This patch is to clean up bus width setting code.

- For DM_MMC, remove getting "bus-width" from device tree.
  This has been done in mmc_of_parse().

- For non-DM_MMC, move bus width configuration from fsl_esdhc_init()
  to fsl_esdhc_initialize() which is non-DM_MMC specific.
  And fix up bus width configuration to support only 1-bit, 4-bit,
  or 8-bit. Keep using 8-bit if it's not set because many platforms
  use driver without providing max bus width.

- Remove bus_width member from fsl_esdhc_priv structure.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:24 +08:00
Yangbo Lu
5b05fc0310 mmc: fsl_esdhc: fix voltage validation
Voltage validation should be done by CMD8. Current comparison between
mmc_cfg voltages and host voltage capabilities is meaningless.
So drop current comparison and let voltage validation is through CMD8.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:24 +08:00
Yangbo Lu
531ccd407c mmc: fsl_esdhc: drop controller initialization in fsl_esdhc_init()
Controller initialization is not needed in fsl_esdhc_init().
It will be done in esdhc_init() for non-DM_MMC, and in
esdhc_init_common() in probe for DM_MMC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:24 +08:00
Yangbo Lu
5d336d1701 mmc: fsl_esdhc: drop i.MX DDR support code
A previous patch below adding DDR mode support was actually for i.MX
platforms. Now i.MX eSDHC driver is fsl_esdhc_imx.c. For QorIQ eSDHC,
it uses different process for DDR mode, and hasn't been supported.
Let's drop DDR support code for i.MX in fsl_esdhc driver.

0e1bf61 mmc: fsl_esdhc: Add support for DDR mode

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-10-29 10:09:22 +08:00
Yangbo Lu
2913926f3b mmc: fsl_esdhc: remove redundant DM_MMC checking
Remove redundant DM_MMC checking which is already in DM_MMC conditional
compile block.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-10-29 10:09:21 +08:00
Yangbo Lu
41dec2fe99 mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC
U-boot prefers DM_MMC + BLK for MMC. Now eSDHC driver has already
support it, so let's force to use it.

- Drop non-BLK support for DM_MMC introduced by below patch.
  66fa035 mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled

- Support only DM_MMC + BLK (assuming BLK is always enabled for DM_MMC).

- Use DM_MMC instead of BLK for conditional compile.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-10-29 10:09:21 +08:00
Yinbo Zhu
6f883e501b mmc: fsl_esdhc: Add emmc hs200 support
Add eMMC hs200 mode for ls1028a, ls1012a, lx2160a.
This increases eMMC performance.
Tuning procedure is currently not supported.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12 14:05:38 +05:30
Yangbo Lu
4d8ff42e46 mmc: fsl_esdhc: drop i.MX code
Dropped i.MX code which couldn't be reused.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
2019-06-23 14:18:42 +08:00
Yangbo Lu
66fa035b55 mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled
u-boot is trying to make CONFIG_BLK as a hard requirement
for DM_MMC. But now it's still not.

config BLK
	bool "Support block devices"
	depends on DM
	default y if DM_MMC

When fsl_esdhc driver was reworked for DM_MMC support, DM_MMC
without CONFIG_BLK enabled wasn't considered. This patch is to
fix probe issue without CONFIG_BLK enabled.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19 12:54:56 +05:30
Yinbo Zhu
b69e1d0bc7 driver: mmc: adopt 32 bit addr in fsl_esdhc for CONFIG_PPC
PowerPC supports 32 bit address.
So adopt 32 bit addr in fsl_esdhc for CONFIG_PPC.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-23 14:22:33 +05:30
Yinbo Zhu
b512d07e8c driver: mmc: set sdhc clock in fsl_esdhc for CONFIG_PPC
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-23 14:22:33 +05:30