The T4 has added devices to previous corenet implementations:
* SEC has 3 more DECO units
* New PMAN device
* New DCE device
This doesn't add full support for the new devices. Just some
preliminary support.
Move PMAN LIODN to upper half of register
Despite having only one LIODN, the PMAN LIODN is stored in the
upper half of the register. Re-use the 2-LIODN code and just
set the LIODN as if the second one is 0. This results in the
actual LIODN being written to the upper half of the register.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only
async mode is supported.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Create new files to handle 2nd generation Chassis as the registers are
organized differently.
- Add SerDes protocol parsing and detection
- Add support of 4 SerDes
- Add CPRI protocol in fsl_serdes.h
The Common Public Radio Interface (CPRI) is publicly available
specification that standardizes the protocol interface between the
radio equipment control (REC) and the radio equipment (RE) in wireless
basestations. This allows interoperability of equipment from different
vendors,and preserves the software investment made by wireless service
providers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Corenet 2nd generation Chassis has different RCW and registers for SerDes.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The QCSP registers are expanded and moved from offset 0 to offset 0x1000
for SoCs with QMan v3.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Expand the reference clock select to three bits
000: 100 MHz
001: 125 MHz
010: 156.25MHz
011: 150 MHz
100: 161.1328125 MHz
All others reserved
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Corenet based SoCs have different core clocks starting from Chassis
generation 2. Cores are organized into clusters. Each cluster has up to
4 cores sharing same clock, which can be chosen from one of three PLLs in
the cluster group with one of the devisors /1, /2 or /4. Two clusters are
put together as a cluster group. These two clusters share the PLLs but may
have different divisor. For example, core 0~3 are in cluster 1. Core 4~7
are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2
are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group
A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have
PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1.
PME and FMan blocks can take different PLLs, configured by RCW.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Panic if the number of cores is more than CONFIG_MAX_CPUS because it will
surely overflow gd structure.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Chassis generation 2 has different mask and shift. Use macro instead of
magic numbers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.
Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
These assembly macros simplify codes to add and delete temporary TLB entries.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
FSL_HW_PORTAL_PME is used even when CONFIG_SYS_DPAA_PME is not defined.
Remove the #ifdef.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add a new device tree property named "fsl,liodn-offset-list"
holding a list of per pci endpoint permitted liodn offsets.
This property is useful in virtualization scenarios
that implement per pci endpoint partitioning.
The final liodn of a partitioned pci endpoint is
calculated by the hardware, by adding these offsets
to pci controller's base liodn, stored in the
"fsl,liodn" property of its node.
The liodn offsets are interleaved to get better cache
utilization. As an example, given 3 pci controllers,
the following liodns are generated for the pci endpoints:
pci0: 193 256 259 262 265 268 271 274 277
pci1: 194 257 260 263 266 269 272 275 278
pci2: 195 258 261 264 267 270 273 276 279
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The P5040 does not have SRIO support, so there are no SRIO LIODNs.
Therefore, the functions that set the SRIO LIODNs should not be compiled.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The liodn for the new PCIE controller included in P5040DS is no longer set
through a register in the guts register block but with one in the PCIE
register block itself. Update the PCIE CCSR structure to add the new liodn
register and add a new dedicated SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Commit 709389b6 unintentionally used the Unicode version of the
apostrophy. Replace it with the normal ASCII version.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Erratum: A-004034
Affects: SRIO
Description: During port initialization, the SRIO port performs
lane synchronization (detecting valid symbols on a lane) and
lane alignment (coordinating multiple lanes to receive valid data
across lanes). Internal errors in lane synchronization and lane
alignment may cause failure to achieve link initialization at
the configured port width.
An SRIO port configured as a 4x port may see one of these scenarios:
1. One or more lanes fails to achieve lane synchronization.
Depending on which lanes fail, this may result in downtraining
from 4x to 1x on lane 0, 4x to 1x on lane R (redundant lane).
2. The link may fail to achieve lane alignment as a 4x, even
though all 4 lanes achieve lane synchronization, and downtrain
to a 1x. An SRIO port configured as a 1x port may fail to complete
port initialization (PnESCSR[PU] never deasserts) because of
scenario 1.
Impact: SRIO port may downtrain to 1x, or may fail to complete
link initialization. Once a port completes link initialization
successfully, it will operate normally.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Fix usb device-tree fixup:
- wrong modification of dr_mode and phy_type when
"usb1" is not mentioned inside hwconfig string;
now allows hwconfig strings like:
"usb2:dr_mode=host,phy_type=ulpi"
- add warning message for using usb_dr_mode
and usb_phy_type env variables (if either is used)
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The command declaration now uses the new LG-array method to generate
list of commands. Thus the __u_boot_cmd section is now superseded and
redundant and therefore can be removed. Also, remove externed symbols
associated with this section from include/command.h .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
This patch converts the old method of creating a list of command
onto the new LG-arrays code. The old u_boot_cmd section is converted
to new u_boot_list_cmd subsection and LG-array macros used as needed.
Minor adjustments had to be made to the common code to work with the
LG-array macros, mostly the fixup_cmdtable() calls are now passed the
ll_entry_start and ll_entry_count instead of linker-generated symbols.
The command.c had to be adjusted as well so it would use the newly
introduced LG-array API instead of directly using linker-generated
symbols.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Add section for the linker-generated lists into all possible linker
files, so that everyone can easily use these lists. This is mostly
a mechanical adjustment.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
P4080 Rev3.0 fixes ESDHC13 errata, so update the code to make the
workaround conditional.
In formal release document, the errata number should be ESDHC13 instead
of ESDHC136.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
We should only write TSR_WIS to the SPRN_TSR register in
reset_85xx_watchdog.
The old code would cause the timer interrupt to be acknowledged when the
watchdog was reset, and we would then get no more timer interrupts.
This bug would affect all mpc85xx boards that have the watchdog enabled.
Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Users of familiar with the Linux gpiolib API expect that value parameter
to gpio_direction_output reflects the initial state of the output pin.
gpio_direction_output was always driving the output low, now it drives
it high or low according to the value provided.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This doesn't need to be a long, so change it.
Also adjust bi_baudrate to be unsigned.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
This doesn't need to be a long, so change it.
Also adjust bi_baudrate to be unsigned.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
This doesn't need to be a long, so change it.
Also adjust bi_baudrate to be unsigned.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
This does not need to be a long, so change it.
Also adjust bi_baudrate to be unsigned.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
These don't need to be longs, so change them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Tom Rini <trini@ti.com>
Rather than leave the fdt down next to the code/data, we really should
relocate it along with everything else. For CONFIG_OF_EMBED this happens
automatically, but for CONFIG_OF_SEPARATE it does not.
Add code to copy the fdt and point to the new copy after relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
The following warning was produced, fix it:
board.c: In function 'board_init_r':
board.c:390:8: warning: unused variable 's' [-Wunused-variable]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com>
Cc: Jason Jin <jason.jin@freescale.com>
The following warning was produced, fix it:
speed.c: In function 'get_clocks':
speed.c:94:15: warning: variable 'bPci' set but not used [-Wunused-but-set-variable]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com>
Cc: Jason Jin <jason.jin@freescale.com>
The fbcs variable was unused, producing the following warning:
cpu_init.c: In function 'cpu_init_f':
cpu_init.c:52:10: warning: unused variable 'fbcs' [-Wunused-variable]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com>
Cc: Jason Jin <jason.jin@freescale.com>
The jmp _fault generated the following error message, thus change it
to bra _fault:
start.S: Assembler messages:
start.S:310: Error: Conversion of PC relative displacement to absolute
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com>
Cc: Jason Jin <jason.jin@freescale.com>
When the environment sectors in the flash are big, one get those errors :
mcf547x_8x/start.S:173: relocation truncated to fit: R_68K_PC16 against
symbol `cpu_init_f' defined in .text section in libmcf547x_8x.a(cpu_init.o)
mcf547x_8x/start.S:174: relocation truncated to fit: R_68K_PC16 against
symbol `board_init_f' defined in .text section in libm68k.a(board.o)
Fix that.
Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com>
Cc: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: David Müller <d.mueller@elsoft.ch>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Oliver Brown <obrown@adventnetworks.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
move most of mpc8xx hooks from cmd_ide.c into ide_preinit() and newly created
ide_init_postreset() (invoked after calling ide_reset after ide_preinit),
some cleanup to make checkpatch happy, enable IDE init hooks in configs of
affected boards.
confusingly, these hooks are used by more than just mpc8xx-based boards, and
therefore are placed in arch/ppc/lib/
note: checkpatch still emits warnings about using volatile
Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com>
Replace the in-place ad-hoc implementation of serial_puts() within
the drivers with default_serial_puts() call. This cuts down on the
code duplication quite a bit.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Tom Rini <trini@ti.com>
As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: James F. Dougherty <jfd@broadcom.com>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
With almost all the architecture and board BOARD_LATE_INIT does not use.
CONFIG_BOARD_LATE_INIT is used instead.
This changed CONFIG_BOARD_LATE_INIT from BOARD_LATE_INIT.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Macpaul Lin <macpaul@andestech.com>
[trini: Fixup for context changes]
Signed-off-by: Tom Rini <trini@ti.com>
Since commit 957731ed (ARM: remove broken "lpd7a40x" boards),
lh7a40x cpu and serial driver have become unused. Remove them.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Prepare for upcoming mips64 support. This patch add mips64 address
support.
Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
[daniel.schwierzeck@gmail.com: prefer _MIPS_SZLONG in posix_types.h to fix some warnings]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Clean up mx25 lowlevel_init:
- Add comments.
- Do not use write32 repeatedly with the same value in order not to increase
code size.
- Make register values configurable.
- Use macro parameters with default values instead of literal constants.
- Use defined macros instead of duplicating code.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: John Rigby <jcrigby@gmail.com>
Cc: Matthias Weisser <weisserm@arcor.de>
The CSI PODF bit-field used by the previous code for the i.MX31 CCM PDR0
register is actually composed of two bit-fields: one pre-divider and one
post-divider. This patch fixes the CCM access macros and the code using them
accordingly.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Optimize mx5 lowlevel_init.S code size:
- Compute values at compile time rather than at runtime where possible.
- Assign r4 to hold the zero value rather than setting registers to 0 again and
again.
- Associate a function to setup_pll rather than expanding its large macro code
multiple times.
- Allocate constant values in section only if used.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
The MMC driver appropriate for the i.MX25 is fsl_esdhc, which has nothing to do
with mxcmmc.
Also, each eSDHC instance has a dedicated clock, so gd->sdhc_clk must be set
accordingly. This is good for the case only a single SDHC instance is used
(initialization made with fsl_esdhc_mmc_init()). A future patch will fix the
multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
The FEC is the only SoC Ethernet support available on i.MX25, so define
cpu_eth_init() only for it instead of returning a misleading success code.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Use the standard mxc_get_clock() instead of exporting internal functions and
using literal constant values.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
mxc_get_clock(MXC_FEC_CLK) should return the IPG clock, not the AHB clock.
Also, imx_get_fecclk() was correct but reimplemented the calculation of the IPG
clock, so remove the duplicated code.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Avoid possible overflow in clock calculations, and do not waste calls to lldiv()
to divide simple ulongs.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
The MFN bit-field of the PLL registers represents a signed value. See the
reference manual.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
The i.MX5 eSDHC clocks were considered as coming from the IPG clock although
they have dedicated clock paths.
Also, on i.MX5/6, each SDHC instance has a dedicated clock, so gd->sdhc_clk must
be set accordingly. This is good for the case only a single SDHC instance is
used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix
the multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
There are only 2 I²C instances on i.MX51, but 3 on i.MX53.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
The FEC clock does not come from PLL1, but from the IPG clock. The previous code
was even inconsistent with itself, returning the IPG clock as expected for
imx_get_fecclk(), but the PLL1 clock for mxc_get_clock(MXC_FEC_CLK).
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
The code handling the dividers was duplicated for each possible input clock, and
this function can benefit from the newly introduced get_standard_pll_sel_clk()
function instead of duplicating this mux handling code.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
This function returned 66500000 instead of the correct lp_apm clock frequency if
the CCM.CSCMR1.uart_clk_sel mux is set to 3.
This patch fixes this issue by introducing the get_standard_pll_sel_clk()
function that will be used by future patches to handle identical muxes used by
many other clocks.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
This fixes the "IPG PERCLK" frequency printed by the clocks command. The issue
was that get_ipg_per_clk() used periph_clk instead of lp_apm in the case
CCM.CBCMR.perclk_lp_apm_sel is set.
It also fixes I²C support.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
In the case periph_clk comes from periph_apm_clk, the latter is selected by the
CCM.CBCMR.periph_apm_sel mux, which can source the lp_apm clock from its
input ♯2. get_periph_clk() returned 0 instead of the lp_apm clock frequency in
this case.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
If CCM.CCSR.lp_apm is set, the lp_apm clock is not necessarily 32768 Hz x 1024.
In that case:
- on i.MX51, this clock comes from the output of the FPM,
- on i.MX53, this clock comes from the output of PLL4.
This patch fixes the code accordingly.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
This fixes config_pll_clk(), which used 0x20 instead of 0x200 for PLL4_CLOCK.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks
have different clock gate control bit-fields.
The existing code was correct only for i.MX53, so this patch fixes the i.MX51
use case.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Jana Rapava <fermata7@gmail.com>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
The clock gate values are 2-bit bit-fields. Hence, setting or clearing only one
of these bits like what was done is wrong and can lead to unpredictable behavior
depending on the original value of these bit-fields.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Use clock gate definitions having names showing clearly the gated clock instead
of names giving only a register field index.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Clean up the i.MX5 clock driver:
- Use readl() and writel() instead of their __raw_ counterparts.
- Use the clr/setbits_le32() family of macros rather than expanding code.
- Use accessor macros for bit-fields instead of _MASK and _OFFSET.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Define default SoC input clock frequencies for i.MX5/6 in order to get rid of
duplicated definitions.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jason Liu <r64343@freescale.com>
Cc: Matt Sealey <matt@genesi-usa.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using
MXC_I2C_CLK on all imx systems using i2c.
Signed-off-by: Matthias Weisser <weisserm@arcor.de>
Acked-by: Stefano Babic <sbabic@denx.de>
tested on a MCIMX257CJM4A which now reports :
CPU: Freescale i.MX25 rev1.2 at 399 MHz
Signed-off-by: Eric Bénard <eric@eukrea.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Register CCM_CHSCCDR (offset 0x34 in CCM) is named CCM_CHSCCDR in
reference manual, but was named chscdr in struct mxc_ccm_reg.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add meaningful constants for each clock channels and use them for
enabling and disabling i.MX6 clocks.
Includes an update to enable/disable the IPU1 clock in
drivers/video/ipu_common to remove IMX5x register access
when used on i.MX6 as discussed in V1:
http://patchwork.ozlabs.org/patch/185129/
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Boards may require a different pinmux setup for NAND than the default one.
Add a way to call into board specific code to set this up.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The prototypes used in board files were all scattered out, which lead to
code duplication between SPL and normal U-Boot and some prototypes not actually
being used. Consolidate this in a common board header.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
