Judging from its name and parameters, device_is_compatible looks like it
is compatible with a live device tree, but it actually isn't.
Make it compatible with a live device tree.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
There are some whitespace-related style violations in read.c; fix those.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The Makefile entries in the clk driver directory were not alphabetically
sorted. Correct this.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The clk uclass was converted to support a live device tree recently,
hence the global data pointer declarations are no longer needed.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
checkpatch.pl complains that the clk_ops structures used in clk-uclass.c
ought to be const, so we mark them as const.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The function dev_read_addr calls ofnode_get_addr_index in the live tree
case, which does not apply bus translations to the address read from the
device tree. This results in illegal addresses on boards that rely on
bus translations being applied.
Fix this situation by applying bus translations in the live tree case as
well.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Tested-by: Stephen Warren <swarren@nvidia.com>
Now this driver is used across stm32f4, stm32f7 and stm32h7
SoCs family, give it a generic name.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
The command portion of the GPIO driver can only be used in full SPL so
re-work to guard the command related portions and mark it as static.
Cc: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
The command portion of the GPIO driver can only be used in full SPL so
re-work to guard the command related portions and mark it as static.
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add support for simple memory fill operation. With large data sizes
it is much faster to use EDMA for memory fill rather than CPU.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
omap_hsmmc driver uses "|" in a couple of places for disabling a bit.
While it's okay to use it in "mmc_reg_out" (since mmc_reg_out has a
_mask_ argument to take care of resetting a bit), it's incorrectly used
for resetting flags in "omap_hsmmc_send_cmd".
Fix it here by using "&= ~()" to reset a bit.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Instead of sending STOP TRANSMISSION command from MMC core, enable
the auto command feature so that the Host Controller issues CMD12
automatically when last block transfer is completed.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The omap hsmmc host controller can have the ADMA2 feature. It brings better
read and write throughput.
On most SOC, the capability is read from the hl_hwinfo register. On OMAP3,
DMA support is compiled out.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Update the calculation for tWR and tPD. This improves the DDR refresh
interval and brings the initialization into line with the binary blobs
currently being supplied by Marvell.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The RD_SAMPLE_DELAY field is 5 bits so it needs to be masked with 0x1f
instead of 0xf. Rather than checking the read sample delay for all DDR
chip selects use the values for the chip selects that are actually
configured. Finally continue searching for the max_phase value even if the
current read_sample is the same as the max_read_sample.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The ternary operation had the HIGH/LOW values the
wrong way round. Update it to use the correct value.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
When using only a single DDR chip select only assert M_ODT[0] on write.
Do not assert it on read and do not assert M_ODT[1] at all. Also set
tODT_OFF_WR to 0x9 which contradicts the recommendation from the
functional spec but is what Marvell's binary training blob does and
seems to give better results when ODT is active during writes.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Update default AXI, TUN, ARC clock set options:
instead of changing only IDIV divider settings adjust also domain PLL
settings.
Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL)
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This reverts commit 46831c1a4c.
This reserved area at the beginning of struct hsmm, will be used later to
support ADMA
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The number 4 is dedicated on i.MX7ULP, but lpi2c will be reused on i.MX8,
4 is not valid. The seq number could be configured by alias node.
The following patch will use i2c4 as the begin for i.MX7ULP.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Identify and distinguish between platform device type of MX7ULP
and LS1021A.
This is a fix to commit 7edf5c45("serial: lpuart: add i.MX7ULP
support").
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This adds SH_ETHER to drivers/net/Kconfig and convert to Kconfig.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When we using network on board using sh-eth, it prints a lot of
"CACHE: Misaligned operation at range" messages.
This commit fixes this problem.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This changes Change structure used in sh_eth_read and sh_eth_write function
from struct sh_eth_dev to struct sh_eth_info. This is necessary to convert
to Driver Model.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
bd_t is not used in sh_eth_config(). This deletes bd_t from sh_eth_config()
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This fixes the chord style checked by checkpatch.pl.
Details of change details are as follows:
- Fix typo
Change from alligned to aligned.
- Remove whitespace before ','
- Add spaces preferred around that '|'
- Fix missing a blank line after declarations
- Remove space after a cast declaration
- Fix format of block comments
- Add a blank line after function/struct/union/enum declarations
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add a b53_reg read/write command which allows inspecting the switch
registers. Because the Broadcom BCM53xx registers have different sizes,
we need to split the accesses in 8, 16, 32, 48 or 64 bits to obtain
expected results.
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Make sure that we pad small packets to a minimum length of 60 bytes
(without FCS). This is necessary to interface with Ethernet switches
that will reject RUNT frames unless padded correctly.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add a minimalistic Broadcom BCM53xx (roboswitch) switch driver similar
to the Marvell MV88E617x. This takes care of configuring the minimum
amount out of the switch hardware such that each user visible port
(configurable) and the CPU port can forward packets between each other
while preserving isolation with other ports.
This is useful for e.g: the Lamobo R1 board featuring a Broadcom
BCM53125 switch.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This implementation manages several clocks, disable and
free all of them in case of error during probe and in remove
callback.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch fixes a problem in the mvneta driver where if more than
one packet arrives between calls to mvneta_recv(), the additional
descriptors will be marked as free even though only one descriptor
has been read and processed from the receive queue. This causes
the additional packet(s) to be delayed until the next packet arrives.
>From this point on all packets will be delayed because the receive
queue will contain unprocessed packets but the hardware shows no
busy descriptors.
Signed-off-by: Jason Brown <jason.brown@apcon.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Since the return value is a signed int, if the leading MSB of rdreg is a 1,
it will get signed extended and will return a negative value which is an
error even though we read the correct value.
Fixes: dfcc496ed7 ("net: mii: Changes not made by spatch")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
First, this table could never be included in the build anyway because
SH_ETH_TYPE_RZ is not defined until later in the file.
Second, the register PIR was missing, so PHY MDIO never worked.
Third, after adding the PIR register, the table is EXACTLY the same as
sh_eth_offset_gigabit, so there is no value to it.
Therefore, just delete it use the gigabit one.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The macros inl and outl maybe already be defined from file
arch/arm/include/asm/io.h so there may be no reason to define them.
And if you do try defined them here, you get a redefined complier warning.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit allows extended Marvell registers to be read with:
foo > mdio rx FEC 3.10
Reading from bus FEC
PHY at address 0:
3.16 - 0x1063
foo > mdio wx FEC 3.10 0x1011
The above code changes the way ETH connector LEDs blink.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Although Xilinx Zynq SoC was using MACB similar hardware. However,
U-boot MACB driver was not supporting Xilinx Zynq SoC. This patch is
to add support for the Xilinx Zynq SoC to the existing MACB network
driver.
This patch is to add Zynq GEM DMA Config, provide callback
function for different linkspeed for case of using Xilinx Zynq
Programmable Logic as GMII to RGMII converter.
This patch convert the return value to use error codes.
Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init,
then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has
already set VSELECT to 1.8v before running the u-boot. This reset in
USDHC driver causes a short 2.2v pulse on CMD pin.
Fix this issue by not reset VSELECT to 0 when 1.8v flag is set.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
In order to discard this code when unused in SPL we need to guard the
command with a check for CONFIG_SPL_BUILD and we rearrange the code
slightly to make this cleaner.
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
By default, the subordinate is set equally to the secondary bus (1) when
the RC boots, and does not alter afterwards.
This means that theoretically, the highest bus reachable downstream is
bus 1.
Force the PCIe RC subordinate to 0xff, otherwise no downstream
devices will be detected behind bus 1 if the booting OS does not allow
enumerating a higher busnr than the subordinate value of the primary
bus.
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
The QSPI module on i.MX7D is modified from i.MX6SX. The module used on
i.MX6UL/6ULL is reused from i.MX7D. They share same tx buffer size.
The endianness is not set at qspi driver initialization. So if we don't
boot from QSPI, we will get wrong endianness when accessing from AHB
address directly.
Add the compatible entry for 6ul/7d.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Before use GPIO, we need to request gpio first. Free gpio after use.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <ssbabic@denx.de>
On i.MX7ULP, the fuse words (except bank 0 and 1) only supports to
write once, because they use ECC mode. Multiple writes may damage
the ECC value and cause a wrong fuse value decoded when reading.
This patch adds a checking before the fuse word programming, only
can write when the word value is 0.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
hc_wp_grp_size is needed only if hardware partitionning is used.
On ARM removing it saves about 30 bytes of code space.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This information is only used by the "mmc info" command.
On ARM removing this information from SPL saves about 140 of code space.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Also remove erase_grp_size and write_bl_len from struct mmc as they are
not used anymore. On ARM, removing them saves about 100 bytes of code
space in SPL.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
The content of ssr is useful only for erase operations.
on ARM, removing sd_read_ssr() saves around 300 bytes.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This allows using CONFIG_IS_ENABLED(MMC_WRITE) to compile out code
needed only if write support is required.
The option is added for u-boot and for SPL
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
struct mmc_data contains the block size to use for the data transfer.
Use this information instead of using the default value or the block length
information stored in struct mmc.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
The SDcard initialization procedure does a few more things than it did earlier:
* switch the bus width even for 1-bit bus width
* check that speed has been properly set (in resp[4] of SD_CMD_SWITCH_FUNC)
Update the SD simulator to handle those requests gracefully.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Not all boards have an eMMC and not all users have a need for this.
Allow to compile it out. By default it is still included.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Supporting USH and HS200 increases the code size as it brings in IO voltage
control, tuning and fatter data structures.
Use Kconfig configuration to select which of those features should be
built in.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This allows to compile out the log message by tweaking the LOGLEVEL.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Not using this function reduces the size of the binary. It's replaces by
a standard malloc() and the alignment requirement is handled by an
intermediate buffer on the stack.
Also make sure that the allocated buffer is freed in case of error.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
The ext_csd is allocated only for MMC above version 4. The compare will
crash or fail for older MMCs.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Make sure that those basic capabilities are advertised by the host.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
As the legacy modes were not added to the list of supported modes, old
cards that do not support other modes could not be used.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
* convert to livetree API
* don't fail because of an invalid bus-width, instead default to 1-bit.
* recognize 1.2v DDR and 1.2v HS200 flags
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This is a useful information while debugging the initialization process or
performance issues.
Also dump this information with the other mmc info if the verbose option
is selected
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add a new function to parse host controller dt node and
set mmc_config. This function can be used by mmc controller
drivers to set the generic mmc_config.
This function can be extended to set other UHS mode caps
once UHS mode support is added.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
HS200/SDR104 requires tuning command to be sent to the card.
Add a simple function to send tuning command and to read and
compare the received data with the tuning block pattern.
This function can be used by platform driver to perform DLL
tuning.
This patch is similar to
commit 996903de92f0 ("mmc: core: add core-level function for
sending tuning commands") added in linux kernel.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
HS200 only supports 1.2v and 1.8v signal voltages. DDR52 supports 3.3v/1.8v
or 1.2v signal voltages.
Select the lowest voltage available when using those modes.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
With certain SD cards like Kingston 8GB/16GB UHS card, it is seen that
MMC_CMD_ALL_SEND_CID cmd fails on first attempt, but succeeds
subsequently. Therefore, retry MMC_CMD_ALL_SEND_CID cmd a few time
as done in Linux kernel.
Similarly, it is seen that MMC_CMD_SET_BLOCKLEN may fail on first
attempt, therefore retry this cmd a few times as done in kernel.
To make it clear that those are optionnal workarounds, a new Kconfig
option 'MMC_QUIRKS' is added (enabled by default).
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Boot partitions do not support HS200. Changing to a lower performance mode
is required to access them.
mmc_select_mode_and_width() and sd_select_mode_and_width() are modified to
make it easier to call them outside of the initialization context.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If a power cycle cannot be done on Vcc, it is safer not to try the UHS
modes because we wouldn't be able to recover from an error occurring
during the UHS initialization.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add UHS modes to the list of supported modes, get the UHS capabilites of
the SDcard and implement the procedure to switch the voltage (UHS modes
use 1v8 IO lines)
During the voltage switch procedure, DAT0 is used by the card to signal
when it's ready. The optional card_busy() callback can be used to get this
information from the host driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add HS200 to the list of supported modes and introduce tuning in the MMC
startup process.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tuning is a mandatory step in the initialization of SDR104 and HS200 modes.
This callback execute the tuning process.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
There is no point in having the mmc clock enabled during
power off. Disable the mmc clock. This is similar to how it's
programmed in Linux Kernel.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
mmc clock has to be disabled in certain cases like during
the voltage switch sequence. Modify mmc_set_clock function
to take disable as an argument that signifies if the
clock has to be enabled or disabled.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
mmc/sd specification requires vdd to be disabled for 1 ms
and then enabled again during power cycle. Add a
function in mmc core to perform power cycle and set
the io signal to it's initial state.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add a new callback function *send_init_stream* which start a sequence of
at least 74 clock cycles.
The mmc core uses *mmc_send_init_stream* in order to invoke the callback
function. This will be used during power cycle where the specification
requires such a sequence after power up.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add a new function *mmc_set_signal_voltage* in mmc core
which can be used during mmc initialization to select the
signal voltage. Platform driver should use the set_ios
callback function to select the signal voltage.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
set_ios callback has a return value of 'int' but the mmc_set_ios()
function ignore this. Modify mmc_set_ios() and the callers of mmc_set_ios() to
to return the error status.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The MMC startup process currently handles 4 modes. To make it easier to
add support for more modes, let's make the process more generic and use a
list of the modes to try.
The major functional change is that when a mode fails we try the next one.
Not all modes are tried, only those supported by the card and the host.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The SDcard startup process currently handles only 2 modes. To make it
easier to add support for more modes, let's make the process more generic
and use a list of the modes to try.
The major functional change is that when a mode fails we try the next one.
Not all modes are tried, only those supported by the card and the host.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds a simple helper function to display information (bus width and
mode) based on a capability mask. Useful for debug.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
no functionnal changes.
In order to add the support for the high speed SD and MMC modes, it is
useful to track this information.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This will be reused later in the selection of high speed and ddr modes.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The ext csd is used for comparison many times. Keep a reference content
of the ext csd in the struct mmc to avoid reading multiple times
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
no functionnal change. This is only to further reduce the size o
mmc_startup().
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
No functionnal change here. The function is really big and can be split.
The part related to bus configuration are put in 2 separate functions: one
for MMC and one for SD.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Get a reference to the regulator devices from the dts and store them
in the struct mmc for later use.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
data is defined as struct mmc_data *data.
So it should not be compared to 0.
Problem identified with Coccinelle.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Fixes emmc initialization regression on the db410c platform.
Clearing this register while SDHCI_PRESENT_STATE reports
SDHCI_CMD_INHIBIT leads to undefined behaviour on the db410c.
When commit 7dde50 was merged (mmc: sdhci: Wait for SDHCI_INT_DATA_END
when transferring), SDHCI transfers transitioned to wait for bit
SDHCI_INT_DATA_END before flagging transfers done.
Without this patch, the db410 platform fails to initialize its eMMC
due to all of its transfers timing out (SDHCI_INT_DATA_END is never
raised after all the blocks have been transferred).
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
This patch fixes some warnings when building boards that do not define
DM_I2C_COMPAT i.e. boards that entirely rely on the new i2c layer.
Signed-off-by: Felix Brack <fb@ltec.ch>
priv pointer should be freed before returning with an error value
from exynos_dwmci_get_config().
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
Signed-off-by: Raghu Bharadwaj <raghu@techveda.org>
__be32_to_cpu() accepts argument of type __be32. This patch changes
type of the buffer in ALLOC_CACHE_ALIGN_BUFFER macro to __be32, which
is then passed to __be32_to_cpu().
This prevents sparse build warnings.
drivers/mmc/mmc.c: warning: cast to restricted __be32
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
Signed-off-by: Karthik Tummala <karthik@techveda.org>
The LCDC IP-core an be feed from several clock sources, one of those is
a dedicated DPLL for generating a dividable base-clock for this IP-core.
The TRM specifies the maximum input frequency for the LCCD with 200 MHz,
so we must not exceed this value with the PLL frequency (which can lock
much higher).
This patch tries every combination of multipliers and divisors of the
PLL and the IP-core itself for getting as near as possible the the
requested panel->pxl_clk.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
The CONFIG_SYS_DPAA_QBMAN define is used by DPAA1 freescale SOCs to
add device tree fixups that allow deep sleep in Linux. The define was
placed in header files included by a number of boards, but was not
explicitly documented in any of the Kconfigs. A description was added
to the drivers/networking menuconfig and default selection for
current SOCs that have this part
Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch adds changes necessary to move functionality present in
PowerPC folders with ARM architectures that have DPAA1 QBMan hardware
- Create new board/freescale/common/fsl_portals.c to house shared
device tree fixups for DPAA1 devices with ARM and PowerPC cores
- Add new header file to top includes directory to allow files in
both architectures to grab the function prototypes
- Port inhibit_portals() from PowerPC to ARM. This function is used in
setup to disable interrupts on all QMan and BMan portals. It is
needed because the interrupts are enabled by default for all portals
including unused/uninitialised portals. When the kernel attempts to
go to deep sleep the unused portals prevent it from doing so
Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Last user of this option went away in 2015 in commit:
d928664f41 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
This allows to controls the memory internal mapping at
address 0x0000 0000.
We can either map at 0x0000 0000 :
_ main flash memory
_ system flash memory
_ FMC bank1 (NOR/PSRAM 1 and 2)
_ embedded SRAM
_ FMC/SDRAM bank1
This is needed for future STM32F469-disco board
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Use available DM stm32f7_gpio.c and pinctrl_stm32.c drivers
instead of board GPIO initialization.
Remove stm32_gpio.c which is no more used and migrate
structs stm32_gpio_regs and stm32_gpio_priv into
arch-stm32f4/gpio.h to not break compilation.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Use available DM clk_stm32f.c driver instead of dedicated
mach-stm32/stm32f4/clock.c.
Migrate periph_clock defines from stm32_periph.h directly in
CLK driver. These periph_clock defines will be removed when STMMAC,
TIMER2 and SYSCFG drivers will support DM CLK.
Enable also CLK flag.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Remove serial_stm32.c driver and uart init from board file,
use available DM serial_stm32x7.c driver compatible for
STM32F4/F7 and H7 SoCs.
The serial_stm32x7.c driver will be renamed later with a more
generic name as it's shared with all STM32 Socs.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
STM32F4 SoCs uses the same pinctrl block as found into
STM32F7 and H7 SoCs.
We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl"
compatible string into pinctrl_stm32.c.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
this patch implement rockusb protocol on the device side. this is based on
USB download gadget infrastructure. the rockusb function implements the rd,
wl, rid commands. it can work with rkdeveloptool
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that the musb sunxi glue driver is completely device model / device
tree driven, we should use the base address from the device tree,
instead of hard-coding it in the source code.
Fixes: 3a61b080ac ("musb: sunxi: switch to the device model")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Armada pinctrl drivers shall not be compiled without the entire pinctrl
framework and thus lack a "depends on" condition, otherwise the driver
will simply not be probed.
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Until now, Armada 3700 SoCs could not enable the mvneta driver, and thus
did not benefit from Ethernet support. Add ARMADA_3700 in the
"depends on" list of the MVNETA Kconfig entry.
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
When enable CONFIG_HAS_FSL_DR_USB, we might encounter below compile
warning, apply this patch can fix it:
drivers/usb/host/ehci-fsl.c:109:4: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
^
drivers/usb/host/ehci-fsl.c:108:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
hcor = (struct ehci_hcor *)
^
drivers/usb/host/ehci-fsl.c:115:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
(u32)hccr, (u32)hcor,
^
include/log.h:131:26: note: in definition of macro 'debug_cond'
printf(pr_fmt(fmt), ##args); \
^~~~
drivers/usb/host/ehci-fsl.c:114:2: note: in expansion of macro 'debug'
debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
^~~~~
drivers/usb/host/ehci-fsl.c:115:19: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
(u32)hccr, (u32)hcor,
^
include/log.h:131:26: note: in definition of macro 'debug_cond'
printf(pr_fmt(fmt), ##args); \
^~~~
drivers/usb/host/ehci-fsl.c:114:2: note: in expansion of macro 'debug'
debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
^~~~~
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Bind rockchip reset to clock-controller with rockchip_reset_bind().
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
It is not much needed to print nand size in SPL during nand boot,
and most of nand spl drivers doesn't print the same.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The blob_encap and blob_decap functions were not flushing the dcache
before passing data to CAAM/DMA and not invalidating the dcache when
getting data back.
Therefore, blob encapsulation and decapsulation failed with errors like
the following due to data cache incoherency:
"40000006: DECO: desc idx 0: Invalid KEY command"
To ensure coherency, we require the key_mod, src and dst buffers to be
aligned to the cache line size and flush/invalidate the memory regions.
The same requirements apply to the job descriptor.
Tested on an i.MX6Q board.
Reviewed-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Since commit 051ba9e082 ("Kconfig: mx6ull: Deselect MX6UL from
CONFIG_MX6ULL") CONFIG_MX6ULL does not select CONFIG_MX6UL anymore, so
take this into consideration in all the checks for CONFIG_MX6UL.
This fixes a boot regression.
Reported-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Tested-by: Breno Lima <breno.lima@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Tested-by: Jörg Krause <joerg.krause@embedded.rocks>
The calculation of left space for version string is not correct, should
use VIDEO_COLS not VIDEO_LINE_LEN / 2, otherwise we will get larger space
than actual have and cause string to overlay logo picture.
Also current version string display only supports two lines words at max.
This also causes overlay when the LCD pixel column size is not enough.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Anatolij Gustschin <agust@denx.de>
The clk_set_rate function dereferences the clk pointer without
checking whether it is NULL. This may cause problem when clk is NULL.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
The patch replaces the former error() by the new pr_err().
This makes the TPS65910 driver conform to Masahiro's patch
'treewide:replace with error() with pr_err()' introduced
October 2017.
Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Simon Glass <sjg@chromium.org>
This spi-nor is 4Mbit/512KB
Fixes: b4fbcbc5a5 ("mtd/spi: add support for is25lq040b")
Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This patch is ported from the Linux patch posted at [1] and applied to
net tree as commit f1e2400a80ff.
The purpose of this change is to fix the incorrect detection of the link
partner (LP) advertised capabilities which sometimes happens with this PHY
(roughly 1 time in a dozen)
This issue may cause the link to be negotiated at 10Mbps/Full or
10Mbps/Half when 100MBps/Full is actually possible. In some case, the link
is even completely broken and no communication is possible.
To detect the corruption, we must look for a magic undocumented bit in the
WOL bank (hint given by the SoC vendor kernel) but this is not enough to
cover all cases. We also have to look at the LPA ack. If the LP supports
Aneg but did not ack our base code when aneg is completed, we assume
something went wrong.
The detection of a corrupted LPA triggers a restart of the aneg process.
This solves the problem but may take up to 6 retries to complete.
[1] https://lkml.kernel.org/r/20171208110811.30789-1-jbrunet@baylibre.com
Fixes: 8995a96d1d ("net: phy: Add Amlogic Meson GXL Internal PHY support")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
fpga:
- Enable loading bitstream via fit image for !xilinx platforms
zynq:
- Fix SPL SD boot mode
zynqmp:
- Not not reset in panic
- Do not use simple allocator because of fat changes
- Various dt chagnes
- modeboot variable setup
- Fix fpga loading on automotive devices
- Fix coverity issues
test:
- Fix env test for !hush case - Stephen's patch
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Merge tag 'xilinx-for-v2018.01-rc2-v2' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2018.01-rc2-v2
fpga:
- Enable loading bitstream via fit image for !xilinx platforms
zynq:
- Fix SPL SD boot mode
zynqmp:
- Not not reset in panic
- Do not use simple allocator because of fat changes
- Various dt chagnes
- modeboot variable setup
- Fix fpga loading on automotive devices
- Fix coverity issues
test:
- Fix env test for !hush case - Stephen's patch
This drops the limit that fpga is only loaded from FIT images for Xilinx.
This is done by moving the 'partial' check from 'common/image.c' to
'drivers/fpga/xilinx.c' (the only driver supporting partial images yet)
and supplies a weak default implementation in 'drivers/fpga/fpga.c'.
Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (On zcu102)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
