Commit graph

91605 commits

Author SHA1 Message Date
Michal Simek
04dca75ae3 arm64: zynqmp: Do not expose usbhub nodes on kr260 usb1
usb0 is already updated but forget to also update usb1.

Fixes: 4ff083f09b ("arm64: zynqmp: Do not expose usbhub nodes")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/862ca748670f18f25d88aa5b43c37e3dd6aa35eb.1706791116.git.michal.simek@amd.com
2024-02-12 09:28:32 +01:00
Michal Simek
f1c24bdf7b arm64: zynqmp: Align nvmem-fw node with dt-schema
Node name has to be renamed to be aligned with dt-schema and also
xlnx,zynqmp-nvmem-fw switched to fixed-layout.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/32899b20c1e282aab16c32074b1c9a3f45f6dac8.1706791116.git.michal.simek@amd.com
2024-02-12 09:28:32 +01:00
Michal Simek
e0cce11434 arm64: zynqmp: Remove arm,cortex-a53-edac node
There is no dt schema associated with it. Also Linux driver have been
removed in Xilinx Linux tree and never gets to upstream that's why remove
description for it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6685ee980d9b475f95eef6b2a74795adc4ac4619.1706791116.git.michal.simek@amd.com
2024-02-12 09:28:32 +01:00
Michal Simek
fb16d9321f xilinx: Fix fpga region DT nodes name
fpga-full is not aligned with the latest dt-schema. Generic name
fpga-region should be used.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/78e6e3f287f79917eb92c6c74accbaf955526aad.1706791116.git.michal.simek@amd.com
2024-02-12 09:28:32 +01:00
Michal Simek
f8e125c995 arm64: zynqmp: Fix kr260 clock wiring
kr260 revA/revA01 is using discrete oscilator for DP (27MHz) and si5332 for
other clocks but clocks are different compare to kv260 that's why fix it to
aligned with the latest schematics.

On the other handle kr260 revB/revA03 also contains 74.25 MHz discrete
clock chip for SLVC-EC output which is not defined.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e87ae94979c6efc909740bb1a569505042e4f876.1706626255.git.michal.simek@amd.com
2024-02-12 09:28:32 +01:00
Michal Simek
8e9566c981 arm64: zynqmp: Describe 25MHz fixed clock for PL GEMs
Describe 25Mhz fixed oscilator which is providing clock for PL based
ethernet IPs. Physicially it is one chip but it is described as 2 fixed
clock to be aligned with other SOM versions which were using integrated
clock generators where clocks could be adjusted via i2c (si5332 chips).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c430aeacaa76d9f61ed3f874f721a33049f45eb9.1706514396.git.michal.simek@amd.com
2024-02-12 09:28:32 +01:00
Michal Simek
0845f5c803 arm64: zynqmp: Sync clock labels with kr260 revB
Board description describes the hard part of chip (PS) but programmable
logic (PL) part is not described in this file. But clocks on the board are
not only connected to PS but also wired to PL. And because two revisions
are available where revA is using one si5332 and revB multiple clock chips
using the same clock labels helping with keeping only one device tree
overlay which targets PL. That's why synchronize clock labels and use
labels from revB which are more generic.
Unfortunately if there is driver for si5332 chip split could happen again
but it is still worth to do it now and solve this issue when occurs.

Reported-by: Sagar Karmarkar <sagar.karmarkar@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/abac6069e6029ed4076ec7b9d6b33604b6072aa3.1706253871.git.michal.simek@amd.com
2024-02-12 09:28:32 +01:00
Saeed Nowshadi
cbd87dae91 arm64: zynqmp: Add 'silabs, skip-recall' to all si570 clk nodes
Without 'silabs,skip-recall' property, the driver on System Controller
re-calibrates the output clock frequency at probe() time based on the NVRAM
setting.  This re-calibration causes a glitch on the output clock.  At
power-on, Versal is also booting and expecting a glitch-free clock for
its correct operation.  System Controller should skip the re-calibration
step to prevent any clock instability for Versal.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/bbb2322c94503f0e6b369c60312b7546500fad95.1706170068.git.michal.simek@amd.com
2024-02-12 09:28:32 +01:00
Michal Simek
98f7bf5da4 arm64: xilinx: Enable EFI_HTTP_BOOT by default
Enable EFI_HTTP_BOOT to be able to booting OS via http.
In case of that dhcp server is not providing dns server IP set it up via
setenv dnsip <ip addr>.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b78a7d8b0100c724f657c0997b273e073cf31a14.1706093917.git.michal.simek@amd.com
2024-02-12 09:28:31 +01:00
Venkatesh Yadav Abbarapu
8a58aed145 configs: versal_net: Enable CONFIG_LTO for mini qspi/ospi
Adding a tiny bit more code for mini u-boot leads to a OCM
image overflow. Fix this by enabling LTO for this board, so that such
changes still can be made to the common U-Boot code.

Enable building mini u-boot image with LTO, which results in about 8KB
reduction in size.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240126081139.3210211-1-venkatesh.abbarapu@amd.com
2024-02-12 09:28:31 +01:00
Venkatesh Yadav Abbarapu
958526f250 configs: versal: Enable CONFIG_LTO for mini qspi/ospi
Adding a tiny bit more code for mini u-boot leads to a OCM
image overflow. Fix this by enabling LTO for this board, so that such
changes still can be made to the common U-Boot code.

Enable building mini u-boot image with LTO, which results in about 8KB
reduction in size.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240126080900.3209323-1-venkatesh.abbarapu@amd.com
2024-02-12 09:28:31 +01:00
Venkatesh Yadav Abbarapu
dfc8e5f659 soc: zynqmp: Add the IDcode for dr_SE and eg_SE variants
ID code is added for zu67dr_SE, zu11eg_SE, zu19eg_SE and zu47dr_SE
variants. SE is the select edition of restricted devices with the
capabilities.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240123045715.893652-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-02-12 09:28:31 +01:00
Tom Rini
e8f2404e09 Merge branch 'master-779h0-r2' of https://source.denx.de/u-boot/custodians/u-boot-sh 2024-02-11 12:42:25 -05:00
Mathieu Othacehe
fcd377ed64 configs: imx93_var_som: Enable AHAB support
Enable AHAB support in the imx93_var_som configuration.

Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
2024-02-10 15:16:13 -03:00
Mathieu Othacehe
db783ee982 board: imx93_var_som: Probe ELE MU
Probing the MU is needed to prevent this error in the SPL:

ele dev is not initialized
Authenticate container hdr failed, return -19, resp 0x0
IND = INVALID

ele dev is not initialized
Error: release container failed, resp 0x0!
IND = INVALID

SPL: failed to boot from all boot devices

Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
2024-02-10 15:16:13 -03:00
Mathieu Othacehe
2029a4c6be imx93: Use a header for imx9_probe_mu declaration
Put imx9_probe_mu declaration in a new mu.h header file.

Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2024-02-10 15:16:13 -03:00
Marek Vasut
05d3602737 spi: mxc_spi: Add imx6ul-ecspi compatible string
Recent i.MX8MP DTs use new fsl,imx6ul-ecspi compatible string instead
of the fsl,imx51-ecspi compatible string. Add the new compatible string
to fix ECSPI operation on i.MX8MP.

For details, see Linux:
48d74376fb68 ("arm64: dts: imx8mp: update ecspi compatible and clk")
8eb1252bbedf ("spi: imx: remove ERR009165 workaround on i.mx6ul")

Fixes: 451799a6ce ("arm: dts: imx8mp: Sync the DT with kernel 6.4-rc4")
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2024-02-10 15:15:55 -03:00
Marek Vasut
0fa60e3c2a ARM: imx: Let SPL configure ECSPI1 clock on Data Modul i.MX8M Plus eDM SBC
The SPL clock code does configure the ECSPI clock frequency, which has
to match the mxc-spi driver configuration for successful SPI NOR boot.
Drop the assigned-clock from DT ecspi1 node on this board to let the
SPL clock code do the configuration and keep it aligned with the driver
expectation.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-02-10 15:15:40 -03:00
Hai Pham
53066deccb ARM: renesas: Add Renesas R8A779H0 V4M Gray Hawk board code
Add board code for the Renesas R8A779H0 V4M Gray Hawk board.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Hai Pham
9e9a92e4a3 ARM: dts: renesas: Add Renesas Gray Hawk boards support
Initial support for the Renesas Gray Hawk CPU and BreakOut boards.

The arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi is extended version of:
https://lore.kernel.org/linux-renesas-soc/b657402113267acd57aece0b4c681b707e704455.1706194617.git.geert+renesas@glider.be/
The version currenty submitted upstream lacks functionality which is
present in this series. Once the upstream support implements that
missing functionality, these DTs will be updated to match.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Hai Pham
903f98e88c ARM: dts: renesas: Add Renesas R8A779H0 V4M DT extras
Add Renesas R8A779H0 V4M DT extras for U-Boot.

Until the RPC node becomes part of main DT, keep it here as
an extension so that board code can enable and use the RPC
to access SPI NOR.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Hai Pham
1acb69d9b3 ARM: dts: renesas: Add Renesas R8A779H0 V4M SoC support
Add initial support for the Renesas R8A779H0 (R-Car V4M) SoC.

The current version is imported and modified from:
https://lore.kernel.org/linux-renesas-soc/4107bc3d7c31932da29e671ddf4b1564ba38a84c.1706194617.git.geert+renesas@glider.be/
The modifications contain nodes from previous version
which are useful in U-Boot and not part of the Linux
kernel DT yet. The following nodes were added:
- pfc
- gpio0..gpio7
- i2c0..i2c3
- avb0..avb2
- mmc0

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Hai Pham
c49f936455 mtd: spi: renesas: Add R8A779H0 V4M support
Support RPC SPI on R8A779H0 V4M SoC.

Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2024-02-10 17:08:06 +01:00
Hai Pham
e02ec8cf49 ARM: renesas: Add R8A779H0 V4M Kconfig entry and PRR ID
Add Kconfig entry and PRR ID to support R8A779H0 V4M SoC.

Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Hai Pham
995a857a01 pinctrl: renesas: Add R8A779H0 V4M PFC tables
Add pinctrl tables for R8A779H0 V4M SoC.

The current version of these PFC tables is imported and squashed from:
https://lore.kernel.org/linux-renesas-soc/cover.1706264667.git.geert+renesas@glider.be/

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Marek Vasut
0fb76cc0bc clk: renesas: Implement R8A779H0 V4M PLL7 support
Add PLL7 support to Gen3/Gen4 common clock driver. Add initial PLL7
multiplier and divider values into table in R8A779H0 V4M clock driver.

The PLL7 is new PLL added in R8A779H0 V4M SoC. Only integer multiplication
mode is supported by PLL7. The PLL reference clock are either 16.66 MHz or
20 MHz on R8A779H0 V4M SoC, and the output frequency must be 2000 MHz. The
multiplier values fitting this requirement are calculated to 120 or 100.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-02-10 17:08:06 +01:00
Hai Pham
13a014c38c clk: renesas: Add R8A779H0 V4M clock tables
Add clock tables for R8A779H0 V4M SoC.

The current version is imported from:
https://lore.kernel.org/linux-renesas-soc/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be/
The current version still contains PLL7 extras from the
previous version to provide ethernet support in U-Boot.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Duy Nguyen
42a064d1d7 dt-bindings: power: Add R8A779H0 V4M SYSC power domain definitions
Add power domain indices for R-Car V4M (R8A779H0).

The current version is imported from:
https://lore.kernel.org/linux-renesas-soc/c5cbef71178cada761e9da7bcbb6f21334f93ef8.1706194617.git.geert+renesas@glider.be/

Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Duy Nguyen
ad005d8a77 dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
V4M (R8A779H0) SoC.

The current version is imported from:
https://lore.kernel.org/linux-renesas-soc/11acbd2a30b58607474e9c32eb798b3a00e85e73.1706194617.git.geert+renesas@glider.be/

Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2024-02-10 17:08:06 +01:00
Tom Rini
d7aaaf4223 Merge tag 'u-boot-dfu-20240209' of https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20240209

- sparse error checking fix when using raw chunks
- 2 new additions (AVB, AB) of myself to the MAINTAINERS file
2024-02-09 09:00:42 -05:00
Sean Anderson
766f04a297 lib: sparse: Fix error checking for write_sparse_chunk_raw
The return value of write_sparse_chunk_raw is unsigned, so the existing
check has no effect. Use IS_ERR_VALUE to detect error instead, which is
what write_sparse_chunk_raw does itself.

Fixes: 62649165cb ("lib: sparse: Make CHUNK_TYPE_RAW buffer aligned")
Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://lore.kernel.org/u-boot/1b323ec3-59b0-490b-a2f0-fd961dafcf49@moroto.mountain/
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20240201181851.221701-1-sean.anderson@seco.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-02-09 09:42:04 +01:00
Mattijs Korpershoek
ec19e11373 MAINTAINERS: add Mattijs for Android AVB
Igor has not been active for quite some time on lore:
https://lore.kernel.org/all/?q=igor.opaniuk@gmail.com

I'm interested in helping with maintaining the android_avb
command. I'm a long time android/aosp developer and my daily job is
still doing android work.

Add myself as maintainer for Android AVB.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Acked-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240112-maintainers-ab-v1-2-f2a538eab18a@baylibre.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-02-09 09:42:04 +01:00
Mattijs Korpershoek
b1907e7304 MAINTAINERS: add Mattijs for Android AB
Igor has not been active for quite some time on lore:
https://lore.kernel.org/all/?q=igor.opaniuk@gmail.com

I'm interested in helping with maintaining the android_ab
command. I'm a long time android/aosp developer and my daily job is
still doing android work.

Add myself as maintainer for Android AB.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Link: https://lore.kernel.org/r/20240112-maintainers-ab-v1-1-f2a538eab18a@baylibre.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-02-09 09:42:04 +01:00
Andrew Davis
a4650bf65e ti: keystone2: Move common Kconfig selections to under ARCH_KEYSTONE
These select/imply settings are common to the whole architecture not just
these boards, move these settings to the architecture config.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-02-08 14:42:56 -05:00
Andrew Davis
f2ae98a682 ti: keystone2: Imply NFS command support
TI KS2 boards have the nfs command in their common environment boot
configuration, enable this command.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-02-08 14:42:56 -05:00
Tom Rini
2b51069b7c Merge tag 'u-boot-imx-master-20240208' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
- Add USB support for phycore-imx8mp
- Fix environment corruption, reset on mx6sabresd
- Print reset cause on imx8
- Extend mkimage to support generating an image for i.MXRT FlexSPI
- Add new apalis and colibri variants
- Add support for phyBOARD-Segin-i.MX93 support
- Fix when FEC is primarily used instead of EQOS on i.MX93.
2024-02-08 09:37:16 -05:00
Tom Rini
a7fb2f57ad Merge tag 'fsl-qoriq-2024-2-8' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
Add TJA1120 driver support
fsl-layerscape/soc.c: do not destroy bootcmd environment
2024-02-08 09:10:41 -05:00
Benjamin Hahn
8dcf1df48d phycore-imx8mp: add support for booting and flashing emmc via UUU
add support for Serial Downloader Boot via UUU as well as flashing emmc
via UUU on USB0 Port of phyBOARD Pollux.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2024-02-08 10:11:46 -03:00
Benjamin Hahn
199229e28b phycore-imx8mp: add USB mass storage support
add support for USB mass storage to USB0 port of phyBOARD Pollux.

tested with "ums 0 mmc 2"

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2024-02-08 10:11:46 -03:00
Benjamin Hahn
04bd6d9af4 phycore-imx8mp: add USB host support
The phyBOARD Pollux has two USB ports. Add support for USB host and USB
storage for the USB1 port.

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2024-02-08 10:11:46 -03:00
Benjamin Hahn
a519d28cdb imx8mp-phyboard-pollux-rdk: sync with kernel devicetree from v6.8-rc2
sync devicetree with kernel v6.8-rc2.

New commits on kernel v6.8-rc2:
4a58fcdb1818 arm64: dts: imx8mp-phyboard-pollux: Add support for RS232/RS485
3bd7fdcc359e arm64: dts: imx8mp-phyboard-pollux: Add gpio-line-names
f5faa633daf8 arm64: dts: imx8mp-phyboard-pollux: Enable USB support
27c0dc128d04 arm64: dts: imx8mp-phyboard-pollux: Add flexcan support
fa2a1ec50456 arm64: dts: imx8mp-phyboard-pollux: Add missing usdhc clocks assignment
055e38c76388 arm64: dts: imx8mp-phyboard-pollux-rdk: Fix led sub-node names

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2024-02-08 10:11:46 -03:00
Fabio Estevam
450af2495e mx6sabresd: Remove board_phy_config()
With Ethernet DM in place, there is no longer the need for having
the board_phy_config() anymore.

Remove it.

Confirmed that TFTP transfer still works fine without board_phy_config().

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2024-02-08 09:18:32 -03:00
Fabio Estevam
dbc4814515 mx6sabresd: Convert to watchdog driver model
Commit 68dcbdd594 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.

Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2024-02-08 09:18:32 -03:00
Fabio Estevam
41fdfae064 mx6sabresd: Fix U-Boot corruption after saving the environment
U-Boot binary has grown in such a way that it goes beyond the reserved
area for the environment variables.

Running "saveenv" and rebooting the board causes U-Boot to hang because
of this overlap.

Fix this problem by selecting CONFIG_LTO so that the U-Boot proper
size can be reduced.

Also, to prevent this same problem to happen in the future, use
CONFIG_BOARD_SIZE_LIMIT, which can detect the overlap in build-time.

CONFIG_BOARD_SIZE_LIMIT is calculated as follows:

CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot-img.dtb offset
CONFIG_BOARD_SIZE_LIMIT = 0xc000 - 69 * 1024
CONFIG_BOARD_SIZE_LIMIT = 715766

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2024-02-08 09:18:32 -03:00
Joao Paulo Goncalves
006538670d toradex: tdx-cfg-block: add 0086 i.mx8m mini sku
Add new product id 0086 Verdin iMX8M Mini DualLite 2GB IT.

Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2024-02-08 09:18:11 -03:00
Igor Opaniuk
c4bc7db966 imx: imx8: print reset cause
Add support for printing reset cause during boot.

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2024-02-08 09:17:46 -03:00
Igor Opaniuk
0bc69a1d38 imx: scu_api: add implementation of sc_pm_reset_reason
Add implementation of sc_pm_reset_reason() call for obtaining
reset reason.

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2024-02-08 09:17:46 -03:00
Mathieu Othacehe
7c1f8ce395 board: phytec: phycore-imx93: Add phyBOARD-Segin-i.MX93 support
Add initial support for the PHYTEC phyBOARD-Segin-i.MX93 board based on
the PHYTEC phyCORE-i.MX93 SoM.

Supported features:
- 1GB LPDDR4 RAM
- eMMC
- external SD
- FEC Ethernet
- debug UART
- watchdog

Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
Tested-by: Primoz Fiser <primoz.fiser@norik.com>
Reviewed-by: Yannic Moog <y.moog@phytec.de>
2024-02-08 09:05:11 -03:00
Primoz Fiser
259e101271 imx9: clock: Fix board_interface_eth_init for FEC
Commit d5eae216d8 ("net: dwc_eth_qos: Add board_interface_eth_init()
for i.MX93") implemented board_interface_eth_init for i.MX9 platforms.
However it only accounted for the EQOS interface while any board using
FEC as primary Ethernet interface was left out as return value -EINVAL
is always returned from the function in such case.

Fix this by returning 0 (success) when FEC interface is primarily used
instead of EQOS interface on i.MX93.

Fixes: d5eae216d8 ("net: dwc_eth_qos: Add board_interface_eth_init() for i.MX93")
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Tested-by: Mathieu Othacehe <m.othacehe@gmail.com>
2024-02-08 09:01:22 -03:00
Jesse Taube
b0adbd6f8e tools: mkimage: Add support for i.MXRT FlexSPI Header
Modify imx8m Flex SPI Configuration Block to work with imxrt.
Add more Flex SPI configuration options to Kconfig.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Tested-by:  Adam Ford <aford173@gmail.com> #imx8mn-beacon
2024-02-08 09:01:22 -03:00