Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-28 07:31:15 +00:00
Code Issues Projects Releases Packages Wiki Activity

clk: renesas: Implement R8A779H0 V4M PLL7 support

Browse source 
Add PLL7 support to Gen3/Gen4 common clock driver. Add initial PLL7
multiplier and divider values into table in R8A779H0 V4M clock driver.

The PLL7 is new PLL added in R8A779H0 V4M SoC. Only integer multiplication
mode is supported by PLL7. The PLL reference clock are either 16.66 MHz or
20 MHz on R8A779H0 V4M SoC, and the output frequency must be 2000 MHz. The
multiplier values fitting this requirement are calculated to 120 or 100.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2024-01-28 16:52:02 +01:00
parent 13a014c38c
commit 0fb76cc0bc
3 changed files with 13 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
drivers/clk/renesas/clk-rcar-gen3.c
View file

@ -306,6 +306,12 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
gen4_pll_config->pll6_div,
"PLL6");
case CLK_TYPE_GEN4_PLL7:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, gen4_pll_config->pll7_mult,
gen4_pll_config->pll7_div,
"PLL7");
case CLK_TYPE_FF:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, core->mult, core->div,

10
drivers/clk/renesas/r8a779h0-cpg-mssr.c
View file

@ -206,11 +206,11 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
(((md) & BIT(13)) >> 13))
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
{ 1, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 16, },
{ 1, 160, 1, 200, 1, 160, 1, 200, 1, 160, 1, 140, 1, 19, },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 2, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 32, },
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv PLL7 mult/div */
{ 1, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 16, 120, 1, },
{ 1, 160, 1, 200, 1, 160, 1, 200, 1, 160, 1, 140, 1, 19, 100, 1, },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 2, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 32, 120, 1, },
};
/*

2
drivers/clk/renesas/rcar-gen3-cpg.h
View file

@ -131,6 +131,8 @@ struct rcar_gen4_cpg_pll_config {
u8 pll6_mult;
u8 pll6_div;
u8 osc_prediv;
u8 pll7_mult;
u8 pll7_div;
};
#define CPG_RST_MODEMR 0x060