Commit graph

2480 commits

Author SHA1 Message Date
Kishon Vijay Abraham I
16ca1d09e6 ARM: OMAP5: Add support for disabling clocks in uboot
Add do_disable_clocks() to disable clock domains and module clocks.
These clocks are enabled using do_enable_clocks().

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-08-17 23:29:14 +05:30
Kishon Vijay Abraham I
fca45722fb ARM: AM43xx: Add support for disabling clocks in uboot
Add do_disable_clocks() to disable clock domains and module clocks.
These clocks are enabled using do_enable_clocks().

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-08-17 23:29:14 +05:30
Sylvain Lemieux
2783fe6903 arm: lpc32xx: gpio macro for pin mapping
Add LPC32xx GPIO interface macro for pin mapping.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2015-08-17 08:11:05 -04:00
Sylvain Lemieux
d75b532a9e arm: lpc32xx: mux: add missing registers
Add missing registers in struct definition.
Update GPIO MUX base register to match GPIO base (refer to "LPC32x0 User manual" Rev. 3 - 22 July 2011).

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2015-08-17 08:10:53 -04:00
Thomas Abraham
77b55e8cfc ARM: exynos: move SoC sources to mach-exynos
Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow
reuse of existing code for ARMv8 based Exynos platforms.

Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-08-17 13:06:52 +09:00
Hans de Goede
55ea98d8b1 sun6i: clock: Add support for the mipi pll
Add support for the mipi pll, this is necessary for getting higher dotclocks
with lcd panels.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-14 08:37:39 +02:00
Hans de Goede
49043cbad1 sunxi: clock: Add clock_get_pll3() helper function
Add a helper function to get the pll3 clock rate.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-14 08:37:38 +02:00
Hans de Goede
d8d079966f sunxi: display: Fix composite video out on sun5i
The tv-encoder on sun5i is slightly different compared to the one on
sun4i/sun7i.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-14 08:37:36 +02:00
Thierry Reding
35f590f4c3 ARM: tegra: Make pinmux.h standalone includible
This header file uses type definitions (u8, u32) from linux/types.h but
doesn't include it. If includes aren't carefully ordered this can cause
build failures.

Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-08-13 13:06:03 -07:00
Marcel Ziswiler
a1f34ed873 ARM: tegra: allow reading recovery mode boot type
Add defines to allow reading recovery mode (RCM) boot type from the boot
information table (BIT) written by the boot ROM (BR) to the IRAM.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-08-13 13:06:01 -07:00
Tom Rini
0a9e34056f gpio: omap: Drop 'method' parameter
The "method" parameter was part of the original port of the driver from
the kernel.  At some point this may have been added to allow for future
differentiation (as omap1 and omap2 have different GPIO IP blocks, so
this wasn't an unreasonable thing to do).  At this point however it's
just extra overhead, so drop.

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-08-12 20:48:06 -04:00
Nikita Kiryanov
4eaf126e06 gpio: am43xx: expand gpio support
AM43XX SoCs support up to 192 GPIO signals.
Make this amount available to the driver.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2015-08-12 20:48:04 -04:00
Peter Griffin
447da58b57 mmc: hi6220_dw_mmc: Add hi6220 glue code for dw_mmc controller.
This patch adds the glue code for hi6220 SoC which has 2x synopsis
dw_mmc controllers. This will be used by the hikey board support
in subsequent patches.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-08-12 20:48:01 -04:00
Peter Griffin
8a954eb695 hisilicon: hi6220: Add a hi6220 pinmux driver.
This patch adds basic pinmux support for the hi6220 SoC,
which is found on the hikey board.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
2015-08-12 20:48:00 -04:00
Peter Griffin
8293009baa ARM: hi6220: Add register and bitfield definition header files.
This patch adds the header files which will be used in the subsquent
board / drivers to enable support for hi6220 hikey board.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
2015-08-12 20:47:59 -04:00
Peter Griffin
152f489841 dm: gpio: hi6220: Add a hi6220 GPIO driver model driver.
This patch adds support for the GPIO perif found on hi6220
SoC.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
2015-08-12 20:47:58 -04:00
Nishanth Menon
1bbb556a6a ARM: DRA7/ OMAP5: implement Auxiliary Control Register configuration
Implement logic for ACR(Auxiliary Control Register) configuration using
ROM Code smc service.

Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-08-12 20:47:50 -04:00
Ruchika Gupta
057c220055 Correct License and Copyright information on few files
gpio.h - Added missing copyright in few files.
rsa-mod-exp.h - Corrected copyright in the file.
fsl_sec.h - Added missing license in files
drivers/crypto/fsl/Makefile - Removed the incomplete GPLv2 license and replaced it with GPLv2+ license

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
2015-08-12 20:47:46 -04:00
Paul Kocialkowski
a08af85f46 omap3: Reboot mode support
Reboot mode is written in scratchpad memory before reboot in the form of a
single char, that is the first letter of the reboot mode string as passed to the
reboot function.

This mechanism is supported on OMAP3 both my the upstream kernel and by various
TI kernels.

It is up to each board to make use of this mechanism or not.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-12 20:47:36 -04:00
Vladimir Zapolskiy
dcfd37e5ef nand: lpc32xx: add SLC NAND controller support
The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.

The driver can be included to an SPL image.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
2015-08-12 20:47:33 -04:00
Jiandong Zheng
39d0ce0659 arm: bcmcygnus: Enable Ethernet support
Enable BCM SF2 ethernet and PHY for BCM Cygnus SoC

Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-12 20:47:28 -04:00
Heiko Schocher
3b5df50ec0 arm, at91: support for sam9260 based smartweb board
add support for the at91sam9260 based board smartweb from
siemens. SPL is used without serial support, as this
SoC has only 4k sram for running SPL. Here a U-Boot
bootlog:

RomBOOT
>

U-Boot 2015.07-rc2-00109-g4ae828c (Jun 15 2015 - 09:31:16 +0200)

CPU: AT91SAM9260
Crystal frequency:   18.432 MHz
CPU clock        :  198.656 MHz
Master clock     :   99.328 MHz
       Watchdog enabled
DRAM:  64 MiB
WARNING: Caches not enabled
NAND:  256 MiB
In:    serial
Out:   serial
Err:   serial
Net:   macb0
Hit any key to stop autoboot:  0
U-Boot>

Signed-off-by: Heiko Schocher <hs@denx.de>
2015-08-12 20:47:28 -04:00
Hans de Goede
0ecb43a8d0 sunxi: display: Add a few extra register and constant defines
Add a few extra sunxi display registers and constant defines.

Also rename some existing defines (e.g. dropping _GCTRL) and make
some more generic (e.g. dropping the 2x scaling from
SUNXI_LCDC_TCON1_TIMING_V_TOTAL).

This is a preparation patch for adding composite video out support.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-08 16:26:20 +02:00
Hans de Goede
c9f8947e66 sunxi: usb-phy: Never power off the usb ports
USB devices are not really designed to get the power bounced off and on
at them. Esp. USB powered harddisks do not like this.

Currently we power off the USB ports both on a "usb reset" and when
booting the kernel, causing the usb-power to bounce off and then back
on again.

This patch removes the powering off calls, fixing the undesirable power
bouncing.

Note this requires some special handling for the OTG port:
1) We must skip the external vbus check if we've already enabled our own
vbus to avoid false positives
2) If on an usb reset we no longer detect that the id-pin is grounded, turn
off vbus as that means an external vbus may be present now

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-08 16:26:19 +02:00
Karol Gugala
ad00829971 sunxi: nand: Add pinmux and clock settings for NAND support
To enable NAND flash in sunxi SPL,
pins 0-6, 8-22 and 24 on port C are configured.

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-08-08 16:26:19 +02:00
Tom Rini
ae27120c31 Merge git://git.denx.de/u-boot-dm 2015-08-06 19:56:03 -04:00
Alexandre Courbot
a38a3c4af4 ARM: tegra: enable GPU DT node when appropriate
T124/210 requires some specific configuration (VPR setup) to
be performed by the bootloader before the GPU can be used.
For this reason, the GPU node in the device tree is disabled
by default. This patch enables the node if U-boot has performed
VPR configuration.

Boards enabled by this patch are T124's Jetson TK1 and Venice2
and T210's P2571.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-08-06 10:50:03 -07:00
Alexandre Courbot
871d78ed1b ARM: tegra: move VPR configuration to a later stage
U-boot is responsible for enabling the GPU DT node after all necessary
configuration (VPR setup for T124) is performed. In order to be able to
check whether this configuration has been performed right before booting
the kernel, make it happen during board_init().

Also move VPR configuration into the more generic gpu.c file, which will
also host other GPU-related functions, and let boards specify
individually whether they need VPR setup or not.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-08-06 10:50:03 -07:00
Simon Glass
a7a73ef85f exynos: video: Remove non-device-tree code
We always use device tree on exynos, so remove the unused code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-05 21:06:17 -06:00
Simon Glass
a507454b13 exynos: Add support for the DisplayPort hotplug detect
Allow this function to be selected using the pinmux API.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-05 21:06:14 -06:00
Tom Warren
722e000ccd Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Added PLL variables (dividers mask/shift, lock enable/detect, etc.)
to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X.

Used pllinfo struct in all clock functions, validated on T210.
Should be equivalent to prior code on T124/114/30/20. Thanks
to Marcel Ziswiler for corrections to the T20/T30 values.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-08-05 15:22:51 -07:00
Tom Warren
3e8650c0f9 Tegra: clocks: Add 38.4MHz OSC support for T210 use
Added 38.4MHz/48MHz entries to pll_x_table for CPU PLL. Needs
to be measured - should be close to 700MHz (1.4G/2).

Note that some freqs aren't in the PLLU table in T210 TRM
(13, 26MHz), so I used the 12MHz table entry for them. They
shouldn't be selected since they're not viable T210 OSC freqs.

Since there are now 2 new OSC defines, all tables (pll_x_table,
PLLU) had to increase by two entries, but since 38.4/48MHz are
not viable osc freqs on T20/30/114, etc, they're just set to 0.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-08-05 15:22:51 -07:00
Paul Kocialkowski
95de1e2f26 usb: musb-new: CONFIG_MUSB prefix replacement with CONFIG_USB_MUSB
USB-related options are usually prefixed with CONFIG_USB and platform-specific
adaptation for the MUSB controller already have a CONFIG_USB_MUSB prefix, so
this switches all MUSB-related options to a CONFIG_USB_MUSB prefix, for
consistency.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2015-08-05 17:20:34 +02:00
Nikhil Badola
f7ff0e5e96 armv8/lsch3/config: Define USB XHCI controller base address for LS2085A
Define base address of both usb xhci controllers in lsch3 config
in the format (IMMR + offset) for LS2085A

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:39 -07:00
Nikhil Badola
ca7fb12cc1 armv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085A
Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by
USB XHCI stack for alignment

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:38 -07:00
Tom Rini
7a1af7a79b Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-08-02 07:40:37 -04:00
Peng Fan
a462c34602 imx:mx6ul add dram spl configuration and header file
1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs.
2. Add a new function mx6ul_dram_iocfg to configure dram io.
3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since
   only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support
   runtime check, but not hardcoding #ifdef macros.
4. Introduce mx6ul-ddr.h, which includes the register address for DRAM
   IO configuration.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02 11:05:09 +02:00
Peng Fan
63ee5687fc imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/UL
PAD_CTL_SPEED_LOW for i.MX6SX/UL is (0 << 6)

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02 11:05:08 +02:00
Peng Fan
43cb127b75 imx:mx6ul add clock support
1. Add enet, uart, i2c, ipg clock support for i.MX6UL.
2. Correct get_periph_clk, it should account for
   MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK.
3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function,
   but not use 'ifdef'.
4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX.
5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for
   sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q)
   || defined....", only need one CONFIG_PCIE_IMX in header file.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02 11:05:07 +02:00
Peng Fan
d73d5aee3c imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL
Since i.MX6UL's cache line size is 64bytes, need to
define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02 11:05:07 +02:00
Peng Fan
bc32fc699c imx: mx6ul: Update imx registers head file
1. Update imx register base address for i.MX6UL.
2. Remove duplicated MXS_APBH/GPMI/BCH_BASE.
3. Remove #ifdef for register addresses that equal to
   "AIPS2_OFF_BASE_ADDR + 0x34000" for different chips.
4. According fuse map, complete fuse_bank4_regs.
5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX,
   because we can use runtime check

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02 11:05:07 +02:00
Peng Fan
0ca54023ab imx: mx6ul: Add pins IOMUX head file
Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
2015-08-02 11:05:06 +02:00
Peng Fan
8631c06e9b imx: mx6ul: Add i.MX6UL CPU type
Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime from
DIGPROG register. But the value has been occupied by MXC_CPU_MX6D which
is not real id from DIGPROG register, so change i.MX6D to value 0x67 which
was not occupied.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
2015-08-02 11:05:06 +02:00
Peng Fan
e1c2d68b39 imx: mx6: ccm: Change the clock settings for i.MX6QP
Since i.MX6QP changes some CCM registers, so modify the clocks settings to
follow the hardware changes.

In c files, use runtime check and discard #ifdef.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-08-02 10:43:45 +02:00
Peng Fan
d0acd99334 imx: add cpu type for i.MX6QP/DP
Add cpu type for i.MX6QP/DP.

This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP
and MXC_CPU_MX6DP, we should use:
(is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)).

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-08-02 10:42:48 +02:00
Siva Durga Prasad Paladugu
dad17fd510 armv8: caches: Added routine to set non cacheable region
Added routine mmu_set_region_dcache_behaviour() to set a
particular region as non cacheable.

Define dummy routine for mmu_set_region_dcache_behaviour()
to handle incase of dcache off.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2015-07-31 01:38:12 +02:00
Tom Rini
cc35734358 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2015-07-29 18:58:39 -04:00
Tom Warren
7aaa5a60ce ARM: Tegra210: Add support to common Tegra source/config files
Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too. This also adds misc 64-bit changes
from Thierry Reding/Stephen Warren.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-07-28 10:30:20 -07:00
Tom Warren
6c43f6c8d9 ARM: Tegra210: Add SoC code/include files for T210
All based off of Tegra124. As a Tegra210 board is brought
up, these may change a bit to match the HW more closely,
but probably 90% of this is identical to T124.

Note that since T210 is a 64-bit build, it has no SPL
component, and hence no cpu.c for Tegra210.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-07-28 10:30:19 -07:00
Tom Rini
66d10c18bf Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze 2015-07-28 11:31:21 -04:00
Michal Simek
6fe6f13509 ARM: zynqmp: Wire up SATA for the board
Enable SATA for the ZynqMP targets.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:27 +02:00
Michal Simek
cb7ea82059 ARM: zynqmp: Wire up ethernet controllers
Wire up ethernet controllers and enable MII and BOOTP options.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:27 +02:00
Michal Simek
225bf9aa65 zynqmp: Add support for IP detection via SLCR
SLCR can be used for IP configuration setting.
Add SLCR skeleton to enable run time checking.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:20 +02:00
Antonio Borneo
089fddfde2 stm32f429: pass the device unique ID in DTB
Read device unique ID and set environment variable "serial#".
Value would then be passed to kernel through DTB.

To read ID from DTB, kernel is required to have commit:
3f599875e5202986b350618a617527ab441bf206 (ARM: 8355/1: arch: Show
the serial number from devicetree in cpuinfo)
This commit is already mainline since v4.1-rc1.

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
To: Albert Aribaud <albert.u.boot@aribaud.net>
To: Tom Rini <trini@konsulko.com>
To: Kamil Lulko <rev13@wp.pl>
Cc: u-boot@lists.denx.de
2015-07-27 15:02:14 -04:00
Paul Kocialkowski
cfac375616 omap3: Definitions for SYS_BOOT-based fallback boot device selection
This introduces code to read the value of the SYS_BOOT pins on the OMAP3, as
well as the memory-preferred scheme for the interpretation of each value.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2015-07-27 15:02:07 -04:00
Paul Kocialkowski
ed19bdaea3 omap-common: SYS_BOOT-based fallback boot device selection for peripheral boot
OMAP devices might boot from peripheral devices, such as UART or USB.
When that happens, the U-Boot SPL tries to boot the next stage (complete U-Boot)
from that peripheral device, but in most cases, this is not a valid boot device.

This introduces a fallback option that reads the SYS_BOOT pins, that are used by
the bootrom to determine which device to boot from. It is intended for the
SYS_BOOT value to be interpreted in the memory-preferred scheme, so that the
U-Boot SPL can load the next stage from a valid location.

Practically, this options allows loading the U-Boot SPL through USB and have it
load the next stage according to the memory device selected by SYS_BOOT instead
of stalling.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2015-07-27 15:02:06 -04:00
Paul Kocialkowski
62c5674ea1 omap: SPL boot devices cleanup and completion
This cleans up the SPL boot devices for omap platforms and introduces support
for missing boot devices.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2015-07-27 15:02:04 -04:00
Paul Kocialkowski
60c7c30aa0 omap-common: Common boot code OMAP3 support and cleanup
This introduces OMAP3 support for the common omap boot code, as well as a
major cleanup of the common omap boot code.

First, the omap_boot_parameters structure becomes platform-specific, since its
definition differs a bit across omap platforms. The offsets are removed as well
since it is U-Boot's coding style to use structures for mapping such kind of
data (in the sense that it is similar to registers). It is correct to assume
that romcode structure encoding is the same as U-Boot, given the description
of these structures in the TRMs.

The original address provided by the bootrom is passed to the U-Boot binary
instead of a duplicate of the structure stored in global data. This allows to
have only the relevant (boot device and mode) information stored in global data.
It is also expected that the address where the bootrom stores that information
is not overridden by the U-Boot SPL or U-Boot.

The save_omap_boot_params is expected to handle all special cases where the data
provided by the bootrom cannot be used as-is, so that spl_boot_device and
spl_boot_mode only return the data from global data.

All of this is only relevant when the U-Boot SPL is used. In cases it is not,
save_boot_params should fallback to its weak (or board-specific) definition.
save_omap_boot_params should not be called in that context either.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2015-07-27 15:02:03 -04:00
Tom Rini
26473945ad Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2015-07-25 09:04:18 -04:00
Hans de Goede
d42faf3198 sunxi: musb: Move musb config and platdata to the sunxi-musb glue
Move the musb config and platdata to the sunxi-musb glue, which is where
it really belongs. This is preparation patch for adding device-model
support for the sunxi-musb-host code.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-07-25 11:22:55 +02:00
Hans de Goede
48c06c98ec sunxi: usb-phy: Add support for reading otg id pin value
Add support for reading the id pin value of the otg connector to the usb
phy code.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-07-25 11:22:54 +02:00
Daniel Kochmański
645c48f50e sunxi: Create helper function veryfing valid boot signature on MMC
This patch extracts checking for valid SD card "eGON.BT0" signature from
`board_mmc_init` into function `sunxi_mmc_has_egon_boot_signature`.

Buffer for mmc sector is allocated and freed at runtime. `panic` is
triggered on malloc failure.

Signed-off-by: Daniel Kochmański <dkochmanski@turtle-solutions.eu>
CC: Roy Spliet <r.spliet@ultimaker.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
[hdegoede@redhat.com: Small bugfix to make it work for devs other then mmc0]
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-07-24 16:17:08 +02:00
Jiandong Zheng
854cbd2977 usb: gadget: bcm_udc_otg files
Add the required files for the Broadcom UDC OTG interface.

Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2015-07-22 08:57:54 +02:00
Nikhil Badola
909a1ab2f0 include: usb: Move USB controller base address mapping
Move USB controller Base address mapping from ls102xa immap
to fsl xhci header. This is required to remove any warnings when
controller base addresses are mapped for multiple platforms
in their respective files.

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
2015-07-22 08:55:45 +02:00
Ramneek Mehresh
d09e401b43 arch: arm: fsl: Add XHCI support for LS1021A
Add base register address information for USB
XHCI controller on LS1021A

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2015-07-22 08:55:45 +02:00
Zhichun Hua
21a257b9b3 armv8: Fix TCR macros for shareability attribute
For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit
position [13:12] of TCR_ELx register.

Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:40 -07:00
Haikun Wang
e71a980a4d armv8/ls2085aqds: DSPI pin muxing configure through QIXIS
DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:39 -07:00
Haikun Wang
b0e209dc63 armv8/ls2085a: Enable DSPI get input clk form 'mxc_get_clock'
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:39 -07:00
Alison Wang
88c857df8c arm/ls102xa: Add little-endian mode support for audio IPs
As SCFG_ENDIANCR register is added to choose little-endian or big-endian
for audio IPs on Rev2.0 silion, little-endian mode is selected.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:38 -07:00
Wang Dongsheng
972af2ab51 ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted
completely into a reusable armv7 generic timer. LS1021A will use it
as well.

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:38 -07:00
Stuart Yoder
70e52d2115 armv8/fsl-lsch3: device tree fixups for PCI stream IDs
This patch adds the infrastructure to update device
tree nodes to convey SMMU stream IDs in the device
tree.  Fixups are implemented for PCI controllers
initially.

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:37 -07:00
Stuart Yoder
39da644ea8 armv8/fsl-lsch3: partition stream IDs
Stream IDs on ls2085a devices are not hardwired and are
programmed by sw.  There are a limited number of stream IDs
available, and the partitioning of them is scenario dependent.
This header defines the partitioning between legacy, PCI,
and DPAA2 devices.

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:37 -07:00
Prabhakar Kushwaha
226296656c armv8/fsl-ch3: Add support to print SoC personality
This patch adds support to print out the SoC personality.
Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can
have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A,
LS2085AE and LS2085A

Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:34 -07:00
Stefano Babic
f448c5d320 Merge branch 'master' of git://git.denx.de/u-boot 2015-07-17 11:22:56 +02:00
Tom Rini
4905dfc65d Merge branch 'master' of git://git.denx.de/u-boot-spi 2015-07-14 14:13:23 -04:00
Albert ARIBAUD \(3ADEV\)
b44e60ac04 i2c: fix vf610 support
Add support in mxc_i2c driver, iomux_v3 and vf610 architecture for the four
I2C instances available in VF610.

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-07-10 10:10:48 +02:00
Ulises Cardenas
29067abfaf iMX: adding parsing to hab_status command
hab_status command returns a memory dump of the hab event log. But the
raw data is not human-readable. Parsing such data into readable event
will help to minimize debbuging time.

Signed-off-by: Ulises Cardenas <Ulises.Cardenas@freescale.com>
2015-07-10 10:00:14 +02:00
Peng Fan
19c6ec70c5 imx: mx6 add i2c4 clock support for i.MX6SX
Add I2C4 clock support for i.MX6SX. Since we use runtime check,
but not macro, we need to remove `#ifdef ..` in crm_regs.h, or
gcc will fail to compile the code succesfully.

Making the macros only for i.MX6SX open to other i.MX6x maybe not
a good choice, but we have runtime check.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-07-10 09:36:16 +02:00
Peng Fan
2d59acc70f imx: mx6 remove duplicated enable_cspi_clock
enable_spi_clock does the same thing with enable_cspi_clock, so
remove enable_cspi_clock.
Remove enable_cspi_clock prototype in header file
convert cm_fx6/spl.c to use enable_spi_clk

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-07-10 09:35:53 +02:00
Tom Rini
3cbb15d04f Merge branch 'master' of git://git.denx.de/u-boot-arm 2015-07-07 08:42:35 -04:00
Simon Glass
b69969be5d Revert "break build if it would produce broken binary"
The root cause of this problem should now be fixed.

This reverts commit a6a4c542d3.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Pavel Machek <pavel@denx.de>
Tested-by: Pavel Machek <pavel@denx.de>
2015-07-07 11:39:36 +02:00
Tom Rini
37f4d0ec34 Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2015-07-05 21:22:22 -04:00
Chen-Yu Tsai
e506889c96 sunxi: Add support for UART0 in PB pin group on A33
The A33 adds a pinmux function for UART0 in the PB pin group.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-07-05 11:32:11 +02:00
Tom Rini
808bf7cf65 Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Conflicts:
	configs/tbs2910_defconfig
	configs/tqma6q_mba6_mmc_defconfig
	configs/tqma6q_mba6_spi_defconfig
	configs/tqma6s_mba6_mmc_defconfig
	configs/tqma6s_mba6_spi_defconfig
	include/configs/mx6_common.h

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-07-03 08:41:02 -04:00
Vikas Manocha
54afb50025 stv0991: configure clock & pad muxing for qspi
stv0991 has cadence qspi controller for flash interfacing, this
patch configures the device pads & clock for the controller.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
2015-07-03 13:50:53 +05:30
Ian Campbell
da9971d1b3 Revert "sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memory"
This reverts commit f76eba38b3.

This patch did not have a full and proper copyright/S-o-b chain.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>

Conflicts:
	include/configs/sun6i.h
	include/configs/sun8i.h
2015-06-28 11:46:31 -04:00
Peng Fan
f9a1e9f8cc imx: mx6 introuduce macro is_mx6dqp
Add a new revision CHIP_REV_2_0.
Introudce macro is_mx6dqp, dqp means Dual/Quad Plus.
Since Dual/Quad Plus use same cpu type with Dual/Quad, but different
revision(Major Lower), we use this macro for Dual/Quad Plus.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-06-27 18:18:54 +02:00
Peng Fan
b65d9d868e imx: mx6 correct is_soc_rev usage
is_soc_rev should return a bool value, so use "==", but not "-",
change (is_soc_rev(CHIP_REV_1_0) > 0) to (soc_rev() > CHIP_REV_1_0).
This patch also add space between "&" for cpu_type(rev) macro.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-06-27 18:16:31 +02:00
Tom Rini
0d3f732fd2 Merge git://git.denx.de/u-boot-usb 2015-06-15 20:45:50 -04:00
Tom Rini
7c352cd38d am33xx: Re-enable SW levelling for DDR2
The recent changes for hw leveling on am33xx were not intended for
DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config
value to check against. This lets us pass in the value we would use to
configure, when we have not yet configured the board yet.  In other cases
update the call to be as functional as before and check an already
programmed value in.

Tested-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-06-15 10:57:26 -04:00
Lokesh Vutla
37be54fd13 ARM: BeagleBoard-x15: Enable i2c5 clocks
On AM57xx evm I2C5 is used to detect the LCD board by reading the
EEPROM present on the bus.
Enable i2c5 clocks to help that.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-15 10:57:26 -04:00
Stefano Babic
212b660161 Merge branch 'master' of git://git.denx.de/u-boot 2015-06-15 12:08:11 +02:00
Lokesh Vutla
2cb3cccb8b ARM: DRA7: CPSW: Remove IO delay hack
Now all manual mode configurations are done as part of
IO delay recalibration sequence, remove the hack done for
CPSW.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-06-12 13:02:06 -04:00
Lokesh Vutla
71bed1855f ARM: DRA7: Add support for manual mode configuration
In addition to the regular mux configuration, certain pins of DRA7
require to have "manual mode" also programmed, when predefined
delay characteristics cannot be used for the interface.

struct iodelay_cfg_entry is introduced for populating
manual mode IO timings.
For configuring manual mode, along with the normal pad
configuration do the following steps:
- Select MODESELECT field of each assocaited PAD.
  CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux)
- Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL.
  And pass the offset of the CFG_XXX register in iodelay_cfg_entry.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-12 13:02:05 -04:00
Lokesh Vutla
eda6fbcc8c ARM: DRA7: Add support for IO delay configuration
On DRA7, in addition to the regular muxing of pins, an additional
hardware module called IODelay which is also expected to be
configured. This "IODelay" module has it's own register space that is
independent of the control module.

It is advocated strongly in TI's official documentation considering
the existing design of the DRA7 family of processors during mux or
IODelay recalibration, there is a potential for a significant glitch
which may cause functional impairment to certain hardware. It is
hence recommended to do muxing as part of IOdelay recalibration.

IODELAY recalibration sequence:
- Complete AVS voltage change on VDD_CORE_L
- Unlock IODLAY config registers.
- Perform IO delay calibration with predefined values.
- Isolate all the IOs
- Update the delay mechanism for each IO with new calibrated values.
- Configure PAD configuration registers
- De-isolate all the IOs.
- Relock IODELAY config registers.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-12 13:02:05 -04:00
Lokesh Vutla
61d383d0f7 ARM: DRA7: Add support for virtual mode configuration
In addition to the regular mux configuration, certain pins of DRA7
require to have "virtual mode" also programmed.
This allows for predefined delay characteristics to be used by the SoC
to meet timing characterstics needed for the interface.

Provide easy to use macro to do the same.

For configuring virtual mode, along with normal pad configuration add
the following two steps:
- Select MODESELECT field of each assocaited PAD.
  CTRL_CORE_PAD_XXX[8]:MODESELECT = 1
- DELAYMODE filed should be configured with value given in DATA Manual.
  CTRL_CORE_PAD_XXX[7:4]:DELAYMODE =[0-15] (as given in DATA manual).

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-12 13:02:05 -04:00
Lokesh Vutla
6ae4c3efbd ARM: DRA7: Add pinctrl register definitions
Adopting the pinctrl register definitions from Linux kernel
to be consistent.
Old definitions will be removed once all the pinctrl data
is adapted to new definitions.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-12 13:02:05 -04:00
Lokesh Vutla
1f68451ca0 ARM: DRA7: Make do_set_mux32() generic
do_set_mux32() is redefined in dra7xx and beagle_x15 boards.
IO delay recalibration sequence also needs this.
Making it generic to avoid duplication.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-12 13:02:05 -04:00
Lokesh Vutla
c7400e4882 ARM: DRA7: Add is_dra72x cpu check definition
A generic is_dra72x cpu check is useful for grouping
all the revisions under that. This is used in the
subsequent patches.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-12 12:43:06 -04:00
Lokesh Vutla
6213db78f4 ARM: DRA7: DDR3: Add support for HW leveling
DRA7 EMIF supports Full leveling for DDR3.
Adding support for the Full leveling sequence.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-12 12:43:06 -04:00
Simon Glass
c96d709f30 tegra: Allow board-specific init
Add a hook to allows boards to add their own init to board_init().

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-06-09 09:56:15 -07:00
Simon Glass
057772b761 tegra: Add missing tegra124 peripherals
There are some missing entries in the tables. Add them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-06-09 09:56:14 -07:00
Simon Glass
701b7b1d2c tegra: Introduce SRAM repair on tegra124
This is required in order to avoid instability when running from caches
after the kernel starts.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-06-09 09:56:14 -07:00
Simon Glass
746dc76b99 tegra: clock: Support enabling external clocks
Add a simple function to enable external clocks.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-06-09 09:56:13 -07:00
Chris Kuethe
1005ccda97 patch - arm - define SYS_CACHELINE_SIZE for mx5
mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for
adding gadget support to usbarmory, but it's a property common the the
entire SoC family - may as well make it available to all MX5 boards

Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too

Signed-off-by: Chris Kuethe <chris.kuethe@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Matthew Starr <mstarr@hedonline.com>
Cc: Andrej Rosano <andrej@inversepath.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Chris Kuethe <chris.kuethe@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-06-09 12:00:42 +02:00
Lukasz Majewski
4e633e465b arm: exynos: USB3 PHY base definition for Exynos5 SoCs
After that change it would be possible to call samsung_get_base_usb3_phy()
function to get proper base address

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
2015-06-08 15:25:41 +02:00
Tom Rini
4d80051b63 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-06-08 08:37:02 -04:00
Sanchayan Maity
09cfa8ee6a colibri_vf: Enable board specific USB initialisation for USB pen gpio
Add IOMUX for the pad used as USB pen. This needs to be driven low for
the Iris and Viola boards where it is pulled up high by default. This is
required for the USB host functionality to work on these boards. Use the
board specific weak initialisation function, to drive the pin low which
would be called on "usb start".

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
2015-06-08 08:41:56 +02:00
Bhuvanchandra DV
508f412125 arm: vf610: Add iomux support for DSPI
Add iomux definitions for DSPI second instance.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
2015-06-08 08:41:55 +02:00
Bhuvanchandra DV
098d85840e arm: vf610: Add clock support for DSPI
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
2015-06-08 08:41:55 +02:00
Bhuvanchandra DV
a7b1808ee3 colibri_vf: Add pinmux entries for GPIOs
Inorder to use the pins as GPIO, apart from setting the alt-function,
pinmuxing need to be done, this patch adds pinmux entries of
few GPIOs.

Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
2015-06-08 08:41:55 +02:00
Bhuvanchandra DV
d348a943e7 dm: gpio: vf610: Add GPIO driver support
Add GPIO driver support to Freescale VF610

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
2015-06-08 08:41:54 +02:00
Tom Rini
656ae05273 Merge branch 'rmobile' of git://git.denx.de/u-boot-sh 2015-06-01 07:16:36 -04:00
Nobuhiro Iwamatsu
a5aef73206 arm: rmobile: alt: Update to QoS revision 0.31 and 0.321
This updates r8a7794 QoS to revision 0.31 for ES1 and revision 0.321 for ES2.

Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2015-06-01 08:56:34 +09:00
Daniel Kochmański
f76eba38b3 sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memory
This commit adds support to the sunxi SPL to load u-boot from the internal
NAND. Note this only adds support to access the boot partitions to load
u-boot, full NAND support to load the kernel, etc. from the nand data
partition will come later.

Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-05-29 13:46:36 +02:00
Roy Spliet
d0f4200392 sunxi: Match sun4i, sun6i, sun9i CCI definitions for NAND and DMA
Make sure definitions for NAND clock and DMA gate bits are the same
across boards.

Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-05-29 13:46:36 +02:00
Roy Spliet
a19e735d3c sunxi: Add DMA definitions
Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-05-29 13:46:36 +02:00
Hans de Goede
1871a8ca62 sun9i: Basic sun9i (A80) support
Add initial sun9i (A80) support, only uart + mmc are supported for now.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-05-29 13:46:36 +02:00
Matt Porter
2d18ef2364 ARMv7M: add STM32F1 support
Add ARMv7M STM32F1 support including clocks, timer, gpio, and flash.

Signed-off-by: Matt Porter <mporter@konsulko.com>
2015-05-28 08:18:24 -04:00
Tom Rini
9bea236b34 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-05-26 10:38:01 -04:00
Heiko Schocher
e6c8b716c7 i2c, mxc: rework i2c base address names for different SoCs
rework and unify i2c address names for different SoCs, which
use the mxc_i2c driver.

Signed-off-by: Heiko Schocher <hs@denx.de>
2015-05-26 14:17:00 +02:00
Heiko Schocher
21a26940f9 arm, imx6, i2c: add I2C4 for MX6DL
add I2C4 modul for MX6DL based boards.

Signed-off-by: Heiko Schocher <hs@denx.de>
2015-05-26 14:16:54 +02:00
Peng Fan
ab87fc6bbd imx: dma: correct MXS_DMA_ALIGNMENT
We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee
that socs' cache line size is 32 bytes.
If on chips whose cache line size is 64 bytes, error occurs:
"
NAND:  ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0
ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
"
Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to
CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-05-26 14:14:49 +02:00
Tom Rini
a84988c76d Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-05-22 17:23:15 -04:00
York Sun
a88cc3bd90 arm/ls1021a: Remove ccsr_ddr from immap_ls102xa.h
ccsr_ddr structure is already defined in fsl_immap.h. Remove
this duplicated define. Move fixed timing into ls1021atwr.h.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
2015-05-20 10:34:09 -07:00
Hans de Goede
83edb2ace6 sunxi: video: Fix lvds panel support for sun6i+
We've never tested the lvds panel support on sun6i+ SoCs until now, and
unsurprisingly the lvds code needed some fixes to work on my ga10h A33
tablet with lvds panel. This makes the panel on that tablet actually work.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-05-19 18:46:44 +02:00
Hans de Goede
8975cdf4bc sunxi: Make DRAM_ODT_EN Kconfig setting a bool
Make DRAM_ODT_EN Kconfig setting a bool, add a separate DRAM_ODT_CORRECTION
setting for A23 SoCs and use DRAM_ODT_EN Kconfig everywhere instead of
only in dram_sun4i.c and hardcoding odt_en elsewhere.

Note this commit makes no functional changes for existing boards,
its purpose is to allow changing the odt_en value on future A33 boards.

For sun4i/sun5i/sun7i boards which set DRAM_ODT_EN=y (which no defconfigs
currently do) this patch turns on odt for both the DQ and the DQS lines,
whereas previously it was possibly (but not desirable) to turn odt on only
for one of them by setting the in DRAM_ODT_EN option to 1 or 2 instead of 3.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
2015-05-19 18:46:44 +02:00
Laurent Itti
5cd83b11f9 sunxi: add support for UART2 on A23/A33
Add support for UART2 (2-pin version but note that RTS/CTS pins are available
pn that port for possible future use), can be selected in config
by using CONFIG_CONS_INDEX=3

Signed-off-by: Laurent Itti <laurentitti@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-05-19 18:37:30 +02:00
Tim Harvey
f0e8e8944d imx: mx6: add get_cpu_temp_grade to obtain cpu temperature grade from OTP
The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480
in the Fusemap Description Table in the reference manual. Return this value
as well as min/max temperature based on the value.

Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.

This has been tested with IMX6 Automative and Industrial parts.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-05-19 15:31:40 +02:00
Tim Harvey
9b9449c3e2 imx: mx6: add get_cpu_speed_grade_hz func to return MHz speed grade from OTP
The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING
indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description
Table. Return this frequency so that it can be used elsewhere.

Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.

These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-05-19 15:31:25 +02:00
Tim Harvey
d43e0ab42d mx6: add OTP bank1 registers
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-05-19 15:28:39 +02:00
Peng Fan
7e611272dd imx: mx6sx enable SION for i2c pin mux
Enable IOMUX_CONFIG_SION for all I2C pin mux settings, otherwise
we will get erros when doing i2c operations.
error log like the following:
"
wait_for_sr_state: failed sr=81 cr=a0 state=2020
i2c_init_transfer: failed for chip 0xb retry=1
"

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-05-19 15:13:24 +02:00
Fabio Estevam
b4ed9f86df mx6: Set shared override bit in PL310 AUX_CTRL register
Having bit 22 cleared in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

This was inspired by a patch from Catalin Marinas [1] and also from recent
discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring
suggested that bootloaders should initialize the cache.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html
[2] https://lkml.org/lkml/2015/2/20/199

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
2015-05-15 19:21:24 +02:00
Peng Fan
71204e95ce i2c: mxc: refactor i2c driver and support dm
1. Introduce a new structure `struct mxc_i2c_bus`, this structure will
   used for non-DM and DM.
2. Remove `struct mxc_i2c_regs` structure, but use register offset to access
   registers based on `base` entry of `struct mxc_i2c_bus`.
3. Remove most `#ifdef I2C_QUIRK_REG`. Using driver_data to contain platform
   flags. A new flag is introduced, I2C_QUIRK_FLAG.
4. Most functions use `struct mxc_i2c_bus` as one of the parameters.
   Make most functions common to DM and non-DM, try to avoid duplicated code.
5. Support DM, but pinctrl is not included. Pinmux setting is still set
   by setup_i2c, but we do not need bus_i2c_init for DM.
6. struct i2c_parms and struct sram_data are removed.
7. Remove bus_i2c_read bus_i2c_write prototype in header file. The frist
   paramter of bus_i2c_init is modified to i2c index. Add new prototype
   i2c_idle_bus and force_bus_idle. Since bus_i2c_init is not good for
   DM I2C and pinctrl is missed, we use a weak function for i2c_idle_bus.
   Board file take the responsibility to implement this function, like this:
   "
   int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
   {
	   if (i2c_bus->index == 0)
		   force_bus_idle(i2c_pads_info0);
	   else if (i2c_bus->index == 1)
		   force_bus_idle(i2c_pads_info1);
	   else
		   xxxxxx
   }
   "
8. Introduce a weak function, enable_i2c_clk
9. Tested on an i.MX7 platform. Log info:
 => dm tree
 Class       Probed   Name
 ----------------------------------------
 root        [ + ]    root_driver
 simple_bus  [   ]    |-- soc
 simple_bus  [   ]    |   |-- aips-bus@30000000
 simple_bus  [   ]    |   |   |-- anatop@30360000
 simple_bus  [   ]    |   |   `-- snvs@30370000
 simple_bus  [   ]    |   |-- aips-bus@30400000
 simple_bus  [   ]    |   `-- aips-bus@30800000
 i2c         [   ]    |       |-- i2c@30a20000
 i2c         [   ]    |       `-- i2c@30a40000
 simple_bus  [   ]    `-- regulators
 => i2c dev 0
 Setting bus to 0
 => i2c probe
 Valid chip addresses: 08 50
 => i2c md 8 31
 0031: 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-05-14 18:49:36 -06:00
Peng Fan
e6469f390f imx: mx27 move GPIO_PORTx to gpio.h
These GPIO_PORTx macros should be in gpio.h, but not in imx-regs.h.

Also, imx-regs.h and iomux-v3.h has same macro defintion for
GPIO_PORTx, and both of them are included in mxc_i2c.c(include
mxc_i2c.h). This will incur build warnings with macro redefinition.

Since iomux-v3.h is not compatible with mx27, we can not simply
include iomux-v3.h for mx27, so move the GPIO_PORTx to gpio.h to
fix the build warning.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-05-14 18:49:36 -06:00
Simon Glass
5519912164 arm: Add a prototype for save_boot_params_ret()
It is convenient for some boards to implement save_boot_params() in C rather
than assembler. Provide a way to return in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2015-05-14 18:49:34 -06:00
Hans de Goede
6a72e804a2 sunxi: ohci: Add ohci usb host controller support
This commit adds support for the OHCI companion controller, which makes
usb-1 devices directly plugged into to usb root port work.

Note for now this switches usb-keyboard support for sunxi back from int-queue
support to the old interrupt polling method. Adding int-queue support to the
ohci code and switching back to int-queue support is in the works.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-05-14 18:49:32 -06:00
Thierry Reding
79cf644e2d ARM: tegra: Enable SMMU when going non-secure
Make sure to enable the SMMU when booting the kernel in non-secure mode.
This is necessary because some of the SMMU registers are restricted to
TrustZone-secured requestors, hence the kernel wouldn't be able to turn
the SMMU on. At the same time, enable translation for all memory clients
for the same reasons. The kernel will still be able to control SMMU IOVA
translation using the per-SWGROUP enable bits.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:16 -07:00
Ian Campbell
73169874a2 tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0
These registers can be used to prevent non-secure world from accessing a
megabyte aligned region of RAM, use them to protect the u-boot secure monitor
code.

At first I tried to do this from s_init(), however this inexplicably causes
u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine.

So instead I have added a new weak arch function protect_secure_section()
called from relocate_secure_section() and reserved the region there. This is
better overall since it defers the reservation until after the sec vs. non-sec
decision (which can be influenced by an envvar) has been made when booting the
os.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
[Jan: tiny style adjustment]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:15 -07:00
Jan Kiszka
ffdf9f9ae0 tegra124: Add PSCI support for Tegra124
This is based on Thierry Reding's work and uses Ian Campell's
preparatory patches. It comes with full support for CPU_ON/OFF PSCI
services. The algorithm used in this version for turning CPUs on and
off was proposed by Peter De Schrijver and Thierry Reding in
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/210881. It
consists of first enabling CPU1..3 via the PMC, just to powergate them
again with the help of the Flow Controller. Once the Flow Controller is
in place, we can leave the PMC alone while processing CPU_ON and CPU_OFF
PSCI requests.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:15 -07:00
Jan Kiszka
ce416fac38 ARM: Add board-specific initialization hook for PSCI
Tegra boards will have to initialize power management for the PSCI
support this way.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:15 -07:00
Jan Kiszka
91a34ed9b1 tegra: Make tegra_powergate_power_on public
Will be used for unpowergating CPUs.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:15 -07:00
Jan Kiszka
d6b72da029 virt-dt: Allow reservation of secure region when in a RAM carveout
In this case the secure code lives in RAM, and hence the memory node in
the device tree needs to be adjusted. This avoids that the OS will map
and possibly access the reservation.

Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out
such a region. We only support cutting off memory from the beginning or
the end of a RAM bank as we do not want to increase their number (which
would happen if punching a hole) for simplicity reasons

This will be used in a subsequent patch for Jetson-TK1.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:14 -07:00
Ian Campbell
bfb2c8d35d tegra124: Add more registers to struct mc_ctlr
I will need mc_security_cfg0/1 in a future patch and I added the rest while
debugging, so thought I might as well commit them.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:14 -07:00
Jan Kiszka
104d6fb6cd ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditions
CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to
be taken into account additionally. CONFIG_ARMV7_PSCI is only set on
boards that support CONFIG_ARMV7_NONSEC, and it only works on those.

CC: Tang Yuantian <Yuantian.Tang@freescale.com>
CC: York Sun <yorksun@freescale.com>
CC: Steve Rae <srae@broadcom.com>
CC: Andre Przywara <andre.przywara@linaro.org>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Tested-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:13 -07:00
Simon Glass
dedc44b466 tegra124: video: Add full link training for eDP
Add full link training as a fallback in case the fast link training
fails.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:12 -07:00
Simon Glass
e7e8823c7c tegra: video: support eDP displays on Tegra124 devices
Connect up the clocks and the eDP driver to make these displays work with
Tegra124-based devices.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:11 -07:00
Simon Glass
2eb70de6b1 tegra: Move display controller header into common
Allow this to be used by other Tegra SoCs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:10 -07:00
Simon Glass
96e82a253a tegra124: clock: Add display clocks and functions
Add functions to provide access to the display clocks on Tegra124 including
setting the clock rate for an EDP display.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:09 -07:00
Simon Glass
7bb6199bd6 tegra: clock: Split the clock source code into a separate function
Create a function which sets the source clock for a peripheral, given
the number of mux bits to adjust. This can then be used more generally.
For now, don't export it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:09 -07:00