Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping
generic enable()/disable(). Add a different driver because ops are
different respect to GENERIC/USB.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Before set_rate() pllv3 needs enable() to power the pll up.
Add enable() taking into account different power_bit and
different powerup_set, because some pll needs its power_bit to be
set or reset to be powered on.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
div_mask is different for GENERIC and USB pll, so set it according.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Better to register the 2 clock as 2 different drivers because they work
slightly differently depending on power_bit and powerup_set bits coming
on next patches.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
When no GPIO is used to read the card detect status the following
error is seen:
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... MMC: no card present
*** Warning - No block device, using default environment
Fix it by handling the "broken-cd" property in the same way
that drivers/mmc/sdhci.c does, which considers that the SD card
is present when the "broken-cd" property is passed.
Tested on a imx6ul-evk board.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Remove probe function dm_scan_fdt_dev from zynqmp-firmware driver.
It is just binding its subnode zynqmp-clk.
As a result one extra node is showing up in dm tree.
This is not required, it is anyway bound from it's own zynqmp-clk driver.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove hardcoded base addresses of smc controller and nand controller.
Get those addresses from dt and replace wherever they are used.
Remove smc and nand base address from header file too.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When two instances of AXI QSPI with flash are added and tested
simultaneously the spi driver operations are relocated twice.
As a result code is accessing addresses outside of RAM when
relocated second time which is causing a crash.
Tested on Microblaze.
Similar change was done in past by:
commit f238b3f0fb ("watchdog: dm: Support manual relocation for watchdogs")
commit 2588f2ddfd ("dm: sf: Add support for all targets which requires MANUAL_RELOC")
commit 1b4c2aa25b ("gpio: dm: Support manual relocation for gpio")
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove hardcoded base address of nand and replace it with the
value taken from device tree. Remove base address from header
file too.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Make changes to arasan nand driver to move it to driver model.
Select DM_MTD if arasan nand driver is selected.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
DS3232 is an i2c RTC with 236 bytes of battery-backed SRAM.
Add an RTC driver for DS3232 device, which provides time and
date support. Also read and write functions are provided,
which can be used to access the SRAM memory.
Signed-off-by: Nandor Han <nandor.han@vaisala.com>
This driver allows the use of i2c eeprom device or partition as backing
store for boot counter values with DM enabled.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Add specific dm code, but maintaining this driver as is, so more in the
shape of a mii library. Can be moved to dm in a further step.
Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
This pull request provides:
* support for FIT images for UEFI binaries
* drivers for hardware random number generators
* an implementation of the EFI_RNG_PROTOCOL
* a sub-command for efidebug to display configuration tables
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Merge tag 'efi-2020-04-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-04-rc1
This pull request provides:
* support for FIT images for UEFI binaries
* drivers for hardware random number generators
* an implementation of the EFI_RNG_PROTOCOL
* a sub-command for efidebug to display configuration tables
- Various fixups for amlogic boards
- Unnecessary header includes drop into video/meson
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Merge tag 'u-boot-amlogic-20200108' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- Khadas VIM3L based on Amlogic S905D3 support
- Various fixups for amlogic boards
- Unnecessary header includes drop into video/meson
In the initialization of sata driver, we want to initialize all port
probes, Therefore, any detection failure between of them should continue
initialization by skipping the current port instead of exit.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
In the initialization of sata driver, we want to initialize all port
probes, Therefore, any detection failure between of them should continue
initialization by skipping the current port instead of exit.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
PCA9450 PMIC series is used to support iMX8MM (PCA9450A) and
iMX8MN (PCA9450B). Add the PMIC driver for both PCA9450A and PCA9450B.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
We will generate DRAM 4000MT/s as default for i.MX8MP.
So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8MP use similar ocotp as i.MX8MN, but has changed fuse banks
and ctrl register bit definitions, so update to reflect that.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The current mpc83xx_clk driver is broken for any board for which
mpc83xx_has_pci() is true, i.e. anything not MPC8308:
When is_clk_valid() reports that MPC83XX_CLK_PCI is valid,
init_all_clks() proceeds to call init_single_clk(), but that doesn't
know about either MPC83XX_CLK_PCI or has any handling of the
TYPE_SCCR_ONOFF mode correctly returned by retrieve_mode(). Hence
init_single_clk() ends up returning -EINVAL, and the whole board hangs
in serial_init().
The quickest fix is to simply pretend that clock is invalid for
all, since nobody can have been relying on it. Adding proper support
seems to be a bit more involved than just handling TYPE_SCCR_ONOFF:
- The power-on-reset value of SCCR[PCICM] is 0, so
mpc83xx_clk_enable() would probably need to be tought to enable the
clock.
- The frequency of PCI_SYNC_OUT is either SYS_CLK_IN or SYS_CLK_IN/2
depending on the CFG_CLKIN_DIV configuration input, but that can't
be read from software, so to properly fill out
->speed[MPC83XX_CLK_PCI] I think one would need guidance from
Kconfig or dtb.
Partially fixes: 07d538d281 clk: Add MPC83xx clock driver
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
This adds a message to lists_bind_fdt when it skips initializing a device
pre-relocation. I've had a couple errors where a device didn't initialize
properly because one of its dependencies was missing.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we only support two phases where devres can be used:
bind and probe. This is handled with a boolean. We want to add a new
phase (platdata), so change this to an enum.
Signed-off-by: Simon Glass <sjg@chromium.org>
The devres functionality has very few users in U-Boot, but it still should
have tests. Add a few basic tests of the main functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present when CONFIG_DEBUG_DEVRES is enabled, U-Boot prints log messages
to the console with every devres allocation/free event. This causes most
tests to fail since the console output is not as expected.
In particular this prevents us from adding a device to sandbox which uses
devres in its bind method.
Move devres over to use U-Boot's logging feature instead, and add a new
category for devres.
Signed-off-by: Simon Glass <sjg@chromium.org>
We want to avoid allocating platform data twice. This could happen if
device_probe() is called after device_ofdata_to_platdata() for the same
device.
Add a flag to track whether device_ofdata_to_platdata() has been called on
a device. Check the flag to make sure it doesn't happen twice, and clear
the flag when the data is freed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a new internal function, device_ofdata_to_platdata() to handle
allocating private space associated with each device and reading the
platform data from the device tree.
Call this new function from device_probe().
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the parent is probed before the child's ofdata_to_platdata()
method is called. Adjust the logic slightly so that probing parents is
not done until afterwards.
Signed-off-by: Simon Glass <sjg@chromium.org>
This method is supposed to extract platform data from the device tree. It
should be done before the device itself is probed. Move it earlier in the
device_probe() function.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the clock driver reads its ofdata in the probe() method. This
is not correct although it is often harmless.
However in this case it causes a problem, something like this:
- ast_get_scu() is called (from somewhere) to get the SCI address
- this probes the clock
- first sets up ofdata (which does nothing at present)
- DM marks clock device as active
- DM calls pinctrl
- pinctrl probes and calls ast_get_scu() in ast2500_pinctrl_probe()
- ast_get_scu() probes the clock, but sees it already marked as
probed
- ast_get_scu() accesses the clock's private data, with scu as NULL
- DM calls clock probe function ast2500_clk_probe() which reads scu
By putting the read of scu into the correct method, scu is read as part of
ofdata setup, and everything is OK.
Note: This problem did not matter until now since DM always probed all
parents before reading a child's ofdata. The fact that pinctrl is a child
of clock seems to trigger this strange bug.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
It is not possible to access a device on a PCI bus that has not yet been
probed, since the bus number is not known. Add a warning to catch this
error.
Signed-off-by: Simon Glass <sjg@chromium.org>
These macros use __FILE__ which inserts the full path of the object file
into U-Boot, thus increasing file size. Drop these usages.
An older version of this patch was submitted here:
http://patchwork.ozlabs.org/patch/1205784/
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a driver for the virtio-rng device on the qemu platform. The
device uses pci as a transport medium. The driver can be enabled with
the following configs
CONFIG_VIRTIO
CONFIG_DM_RNG
CONFIG_VIRTIO_PCI
CONFIG_VIRTIO_RNG
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Add a sandbox driver for random number generation. Mostly aimed at
providing a unit test for rng uclass.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a driver for the rng device found on stm32mp1 platforms. The
driver provides a routine for reading the random number seed from the
hardware device.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Remove a superfluous blank line
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add an entry for allowing clock enablement for the random number
generator peripheral, RNG1.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Add a uclass for reading a random number seed from a random number
generator device.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Load the optional resource table from the firmware, and write its
address in the dedicated backup register.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Update the dedicated backup register to track the coprocessor state and
rely on that register to compute the .is_running() value (which expects
a return value of 0 -not 1- if the processor is running).
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Add rproc_elf_load_rsc_table(), which searches for a resource table in
an elf64/elf32 image, and if found, copies it to device memory.
Add also the elf32 and elf64 variants of this API.
Add a test for this.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
This function will be used by the SPL to get the names of images to load
from the FIT. This allows to load different images based on runtime HW
detection.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Make the board driver available in the SPL too. The board driver is a way
to provide useful information about the board and that can be useful in
the SPL too.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Merge tag 'u-boot-atmel-2020.04-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
First set of u-boot-atmel features for 2020.04 cycle
This feature set is a patch series from Tudor Ambarus which includes
parsing of the spi flash SFDP parser for SST flashes, and using those
tables to retrieve unique saved per device MAC address. This is then
used as base mac address on the SAMA5D2 Wireless SOM EK board.
The ECC registers in the SDRAM HMC Adapter should always
be accessible (both when ECC is enabled and disabled).
Currently, the registers are accessible only when ECC is enabled.
The ECC Enabled bit is used to determine the status of
ECC by later OSes so always allow access.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Enable TCU access through the Stratix10 CCU so that the
SMMU can access the SDRAM.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add SDRAM driver for Agilex SoC.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Restructure Stratix 10 SDRAM driver. Move common code to separate
file, in preparation to support SDRAM driver for Agilex.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add Cache Coherency Unit (CCU) driver.
CCU is to ensures consistency of shared data between multi masters
in the system.
Driver initializes CCU's directories and coherency agent
interfaces in CCU IP.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.
agilex-clock.h is from Linux commit ID cd2e1ad12247.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Move Stratix10 and Agilex system manager common code to
system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Move firewall related code to new firewall.c, to share
code in Stratix 10 and Agilex.
SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC
to allow DMA transfer to OCRAM.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get clock manager base address from DT node instead of using
#define.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get system manager base address from DT node instead of
using #define.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get reset manager base address from DT node instead of using
#define.
spl_early_init() initializes the DT setup. So, move spl_early_init() to
beginning of function and before get base address from DT.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add an option for building cache drivers in SPL.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
When the `dfu` command is called from the U-Boot environment,
it now accepts an optional parameter that specifies a timeout (in seconds).
If a DFU connection is not made within that time the `dfu` command exits
(as it would if Ctrl+C was pressed). If the timeout is left empty or being
zero the `dfu` command behaves as it does now.
This is useful for allowing U-Boot to check to see if anything wants to
upload new firmware before continuing to boot.
The patch is based on the commit
5e966ccc3c
by Sebastien Colleur, which has been heavily reworked due to U-Boot changes
in the past.
Signed-off-by: Brad Campbell <bradjc5@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
These files should not be included in meson header files. Drop them and
tidy up the affected C files.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
In cases when the same SPL should run on boards with i.MX8MM, that
differ in DDR configuration, it is necessary to try different
parameters and check if the training done by the firmware suceeds or
not.
Therefore we return the DDR training/initialization success to the
upper layer in order to be able to retry with different settings if
necessary.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
The driver works fine with iMX6SX, add the missing compatible string.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Bring in the following merges:
commit 8fbbec12f7
Merge: 87f69f467a63618e71e8
Author: Tom Rini <trini@konsulko.com>
Date: Fri Jan 3 09:48:47 2020 -0500
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next
- updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support
commit 87f69f467a
Merge: c0912f9bbf4466b99703
Author: Tom Rini <trini@konsulko.com>
Date: Tue Dec 24 08:18:19 2019 -0500
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next
- Enable DM driver on ppc/km boards
- Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x,
T104x, P4080, P2041, P2020, P1020, P3041
- Some updates in mpc85xx-ddr driver, km boards
commit c0912f9bbf
Merge: 533c9f5714a1d6dc3f84
Author: Tom Rini <trini@konsulko.com>
Date: Wed Dec 18 07:20:19 2019 -0500
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next
- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coral
commit 533c9f5714
Merge: 553cb06887033e18b47b
Author: Tom Rini <trini@konsulko.com>
Date: Tue Dec 17 07:53:08 2019 -0500
Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next
i2c: for next
- misc: i2c_eeprom:
Add partition support and add ability to query size
of eeprom device and partitions
- i2c common:
add support for offset overflow in to address and add
sandbox tests for it.
commit 553cb06887
Merge: f39abbbc53b4f98b3b16
Author: Tom Rini <trini@konsulko.com>
Date: Thu Dec 12 08:18:59 2019 -0500
Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next
buildman improvements including toolchain environment feature
sandbox unicode support in serial
Adam Ford reports that this change breaks booting on da850-evm and
Bartosz Golaszewski agrees that with the impending release we should
revert the change for now. With that noted:
This reverts commit 21a4d80a71.
Cc: Bartosz Golaszewski <brgl@bgdev.pl>
Tested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
The scripts/Makefile.lib generates an assembler file (*.S) to wrap the
font data for each file of type ttf defined in Kconfig.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
This code does not really need to use #ifdef. We can use if() instead and
gain build coverage without impacting code size.
Change the #ifdefs to use IS_ENABLED(), etc., instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
This code does not really need to use #ifdef. We can use if() instead and
gain build coverage without impacting code size.
Change the #ifdefs to use CONFIG_IS_ENABLED() instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
This code does not really need to use #ifdef. We can use if() instead and
gain build coverage without impacting code size.
Change the #ifdefs to use IS_ENABLED() instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
This code does not really need to use #ifdef. We can use if() instead and
gain build coverage without impacting code size.
Change the #ifdefs to use IS_ENABLED() instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Most x86 boards that use video make use of 32bpp graphics. Enable this by
default. This fixes missing graphics output on some x86 boards.
Also remove the unnecessary 'default n' while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
The ep node device tree name is governed by these bindings:
https://github.com/torvalds/linux/blob/master/Documentation/
devicetree/bindings/pci/layerscape-pci.txt#L24
As per above the ep compatible node contains platform name.
Therefore, define the ep node compatible as CONFIG to find the
pcie ep node in device tree during device tree fixup.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
move the PCIE related config from arch Kconfig to PCI Kconfig.
As the PCI_LAYERSCAPE driver is being used in platform other than
fsl-layerscape platforms like ls102xa.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
The Rockchip SPI controller's length register only supports 16-bits,
yielding a maximum length of 64KiB (the CTRLR1 register holds "length -
1"). Trying to transfer more than that (e.g., with a large SPI flash
read) will cause the driver to hang.
Now, it seems that while theoretically we should be able to program
CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to
cause the core to choke, so stick with a maximum of 64K - 1 bytes --
i.e., 0xffff.
Note, that the size is further divided into 'minus 1' while writing
into CTRLR1.
This change fixed two different read issues,
1. sf read failure when with > 0x10000
2. Boot from SPI flash failed during spi_flash_read call in
common/spl/spl_spi.c
Observed and Tested in
- Rockpro64 with Gigadevice flash
- ROC-RK3399-PC with Winbond flash
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Static checker warns 'ret' variable may be used uninitialized in
spi_nor_erase() and spi_nor_write() in case of zero length requests.
Fix these warnings by checking for zero length requests and returning
early.
Reported-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Currently inside ddr_init() there is a mix of printf() and debug()
level messages.
Since this type of information is useful for debug purposes,
convert all of them to debug level for consistency.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
As per "Table 26-7. SATA PHY Subsystem Low-Level Programming Sequence"
in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX.
[1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf
Signed-off-by: Roger Quadros <rogerq@ti.com>
For increased DPLL stability use the settings recommended in
the TRM [1] for PHY_RX registers for SATA and USB.
For SATA we need to use spread spectrum settings even
though we don't have spread spectrum enabled. The
suggested non-spread spectrum settings don't work.
[1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf
Signed-off-by: Roger Quadros <rogerq@ti.com>
Introduce a mode property in the driver data so that
we don't have to keep using "of_device_is_compatible()"
throughtout the driver.
No functional change.
Signed-off-by: Roger Quadros <rogerq@ti.com>
The AM572x Technical Reference Manual, SPRUHZ6H,
Revised November 2016 [1], shows recommended settings for the
SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings.
Use those settings in the driver. The TRM does not show
a value for 20MHz SYS_CLK so we use something close to the
26MHz setting.
[1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf
Signed-off-by: Roger Quadros <rogerq@ti.com>
Update API names for layerscape gen4 fixup.
Suffix layerscape_gen4 fixup API names with _ls_gen4.
This is required to organize device tree fixup in common, layerscape
and layerscape_gen4 specific code.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Suffix layerscape fixup API names with _ls.
This is required to organize device tree fixup in common,
layerscape and layerscape_gen4 specific code.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add stream_id_cur field to ls_pcie structure and initialize
it with 0 for all pcie controllers. This field will be used
for streamId calculation.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
lx2160a rev1 uses pcie_layerscape_gen4 driver and lx2160a rev2 uses
pcie_layerscape driver.
Enable pcie_layerscape code for CONFIG_PCIE_LAYERSCAPE_GEN4.
Based on SoC and revision pcie controller probe will be invoked.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Add support for DPSPARSER object (create/destroy, open/close, apply spb)
which is required to configure Soft Parser by using MC.
Also add uboot command to apply Soft Parser Blob with command:
fsl_mc apply spb <spb_load_addr>
Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Some of t1042 boards fails DDR init with an Automatic calibration error
every now and then. Investigations revealed that true Warm boots
never failed. Warm boots has some extra steps performed, one being
to start DDRC in Self Refresh and then clearing SR right after.
Applying this SR method unconditionally made all our boards
stable again, regardless of Cold/Warm boot.
Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface
initialization code would handle them properly along with UNKNOWN
type by default if none of the user/board doesn't need to use the
phy interfaces at all.
The current code is masking the 8/16-bit UTMI+ interface bits globally
which indeed effect the UNKNOWN cases, therefore it effects the platforms
which are not using phy interfaces at all.
So, handle the phy masking bits accordingly on respective interface
type cases.
Fixes: 6b7ebff001 ("usb: dwc3: Add phy interface for dwc3_uboot")
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Since, commit 62f9b65447 ("common: Move older CPU functions to their own header")
cache ops functions are declared in a separate header. Include the same
to avoid build warnings.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Passing 0 to PHY connect used to trigger a MDIO scan due to a bug fixed in
the meantime. It's unclear if bcm-sf2 wants to connect to PHY @ addr 0 or
is scanning the bus, passing -1 here should keep it functional either way.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Cc: Jiandong Zheng <jdzheng@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
PHY address 0 is a valid PHY address, to scan for all PHYs, pass -1 to
phy_connect(). Passing 0 used to work before be accident, but does no
longer.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add gd25q128 128Mbit chip to spi-nor id table.
Tested on Pinebook Pro
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coral
JESD216 allow vendors to define their own SFDP tables.
Add SST SFDP parser. The vendor table is allocated using resource-managed
kmalloc - the table will be freed on driver detach. It will be accessible
by getting the UCLASS_SPI_FLASH's private data.
The SST's SFDP table is particularly of interest because contains
pre-programmed globally unique EUI-48 and EUI-64 identifiers.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Add ability to query size of eeprom device and partitions
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add support for setting the chip address offset mask to EEPROM sumulator
and add tests to test it.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Improve i2c EEPROM simulator testing by providing access functions to
check the previous chip addr and offset.
Given that we can now directly test the offsets, also simplified the
offset mapping and allow for wrapping acceses.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Some devices (2 wire eeproms for example) use some bits from the chip
address to represent the high bits of the offset instead of or as well
as using multiple bytes for the offset, effectively stealing chip
addresses on the bus.
Add a chip offset mask that can be set for any i2c chip which gets
filled with the offset overflow during offset setup.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Signed-off-by: Ian Ray <ian.ray@ge.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
For Apollo Lake we need to take the I2C bus controller out of reset before
using this. Add this functionality to the driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver for the Apollo Lake pinctrl. This mostly makes use of the
common Intel pinctrl support.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a driver for the Apollo Lake SoC. It supports the basic operations and
can use device tree or of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a GPIO driver which uses the pinctrl driver to access the pad
information. This driver relies on the GPIO nodes being subnodes to the
pinctrl device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Recent Intel SoCs share a pinctrl mechanism with many common elements. Add
an implementation of this core functionality, allowing SoC-specific
drivers to avoid adding common code.
As well as a pinctrl driver this provides a GPIO driver based on the same
code.
Once other SoCs use this driver we may consider moving more properties to
the device tree (e.g. the community info and pad definitions).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With of-platdata we need to create drivers for particular chips, or at
least drivers that are separate from the standard code, since C structures
are created by dtoc which are private to that driver.
To avoid duplicating the probing code, export this probe function for use
by these drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add support for Apollo Lake to the ICH driver. This involves adjusting the
mmio address and skipping setting of the bbar.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
In TPL we want to reduce code size and support running with CONFIG_PCI
disabled. Add special code to handle this using a fixed BAR programmed
into the SPI on boot. Also cache the SPI flash to speed up boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add this method so that the memory-mapped location of the SPI flash can
be queried.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Apollo Lake (APL) only supports hardware sequencing. Add support for this
into the SPI driver, as an option.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The Intel Fast SPI interface is similar to ICH. Add of-platdata support
for this using the "intel,fast-spi" compatible string.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This incorrectly shortens read operations if there is a maximum write size
but no maximum read size. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It is useful to store the mmio base in platdata. It reduces the amount of
casting needed. Update the code and move the struct to the C file at the
same time, as we will need to use with of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Use debug() instead of printf() to reduce code size and change a bool
return value to the use the 'bool' type. Also drop the global data
declaration since it not actually used. Finally, set the log category.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Use dev_get_driver_data() to obtain the device type. It has the same
effect and is shorter.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reduce the size of the probe function but putting this code into its own
function.
Also remove the assumption that the PCH is always a parent of the SPI
controller, as this is not the case APL platforms. Use driver model to
find the PCH instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It is annoying to have some of the init code in a different part of the
file. Move ich_init_controller() to just above probe() to keep things
together.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't normally need this on x86 unless the size of SPI flash devices is
larger than 16MB. This can be enabled by particular SoCs as needed, since
it adds to code size.
Drop the default enabling of this option on x86.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we have to have an xfer() method even if it does nothing. This
is not correct, so fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These drivers are not needed on all platforms. While they are small, it
is useful in TPL to drop then. Add Kconfig control to allow this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Update this uclass to support the needs of the Apollo Lake ITSS. It
supports four operations.
Move the uclass into a separate directory so that sandbox can use it too.
Add a new Kconfig to control it and enable this on x86.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a sandbox driver and PCI-device emulator for p2sb. Also add a test
which uses a simple 'adder' driver to test the p2sb functionality.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The Primary-to-Sideband bus (P2SB) is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added in
the device tree as subnodes of the p2sb.
This adds a uclass and enables it for sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Intel x86 SoCs have a power manager/controller which handles several
power-related aspects of the platform. Add a uclass for this, with a few
useful operations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Most of the timer-calibration methods are not needed on recent Intel CPUs
and just increase code size. Add an option to use the known-good way to
get the clock frequency in TPL. Size reduction is about 700 bytes.
Note that version 1 of this commit caused bootstage to crash since the CPU
was not identified. This is corrected by changes previously applied to
make sure that the CPU is identified before spl_init() is called, such as
39146a2e0b x86: Move CPU init to before spl_init()
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On x86 platforms the timer is reset to 0 when the SoC is reset. Having
this as the timer base is useful since it provides an indication of how
long it takes before U-Boot is running.
When U-Boot sets the timer base to something else, time is lost and we
no-longer have an accurate account of the time since reset. This
particularly affects bootstage.
Change the default to not read the timer base, leaving it at 0. Add an
option for when U-Boot is the secondary bootloader.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present these options cannot be enabled for SPL/TPL, but this can be
useful in some cases. Add Kconfig options to allow it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Allow this driver to set up an IO address in SPL using an 'early-regs'
property. This allows SPL to use the I2C driver without having to enable
the full PCI stack.
Also split out ofdata_to_platdata in designware driver since this is more
correct, and more convenient for the new logic.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Drivers are not allowed to use static data since they may be used in SPL
where BSS is not available.
It is possible that driver model may provide support for numbering devices
in the future. But for now, move this to global_data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is hacked into the driver at present. It seems better to have it as
a separate driver that uses the base driver. Create a new file and put
the X86 code into it.
Actually the Baytrail settings should really come from the device tree.
Note that 'has_max_speed' is added as well. This is currently always false
but since only Baytrail provides the config, it does not affect operation
for other devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Early in boot it is necessary to decode the PCI device/function values for
particular peripherals in the device tree or of-platdata. This is needed
in TPL where CONFIG_PCI is not defined.
To handle this, move pci_get_devfn() into a file that is built even when
CONFIG_PCI is not defined.
Also add a function for use by of-platdata, to convert a reg property to
a pci_dev_t.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present PCI auto-configuration happens in U-Boot both before and after
relocation. This is a waste of time and may mess up static addresses used
in board_init_f(). Adjust the code to supporting doing auto-configuration
once, after relocation, under control of a device-tree property.
This is needed for Apollo Lake for debugging the silicon-init code. Once
the UART is moved to a different MMIO address the debug UART does not work
and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass
is included in SPL/TPL without any control for boards. Some boards may
want to disable this to reduce code size where GPIOs are not needed in
SPL or TPL.
Add a new Kconfig option to permit this. Default it to 'y' so that
existing boards work correctly.
Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to
preserve the current behaviour. Also update the 74x164 GPIO driver since
it cannot build with SPL.
This allows us to remove the hacks in config_uncmd_spl.h and
Makefile.uncmd_spl (eventually those files should be removed).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
sandbox unicode support in serial
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Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next
buildman improvements including toolchain environment feature
sandbox unicode support in serial
i2c bugfixes for 2020.01
- i2c: i2c_cdns: fix write timeout on fifo boundary
fixes timout issue when writting number of bytes is multiple
of the FIFO depth.
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Merge tag 'u-boot-atmel-fixes-2020.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
- First set of u-boot-atmel fixes for 2020.01 cycle:
This set includes a small fix for gpio bank names, one for removing
unused headers (also touches some other boards), and a fix for the QSPI
env read on one of the boards.
This fixes an issue that would cause I2C writes to timeout when the
number of bytes is a multiple of the FIFO depth (i.e. 16 bytes).
Within the transfer loop, after writing the data register with a new
byte to transfer, if the transfer size equals the FIFO depth, the loop
pauses until the INTERRUPT_COMP bit asserts to indicate data has been
sent. This same check is performed after the loop as well to ensure data
has been transferred prior to returning.
In the case where the amount of data to be written is a multiple of the
FIFO depth, the transfer loop would wait for the INTERRUPT_COMP bit to
assert after writing the final byte, and then wait for this bit to
assert once more. However, since the transfer has finished at this
point, no new data has been written to the data register, and hence
INTERRUPT_COMP will never assert.
Fix this by only waiting for INTERRUPT_COMP in the transfer loop if
there's still data to be written.
Signed-off-by: Michael Auchter <michael.auchter@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Chromium EC commands can be up to 16-bits, so using a uint8_t here can
cause truncation. Update to use a uint instead.
It looks like this should likely have been done as a part of
9fea76f5d3, but this function was skipped
for some reason.
Signed-off-by: Michael Auchter <michael.auchter@ni.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
bigger than the framebuffer resolution
- reduce dead code in video and console uclass routines
(tested on mx53cx9020, sama5d2_xplained, stm32mp157c-ev1,
stm32f746-disco, stm32f769-disco and wandboard)
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Merge tag 'fixes-for-2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-video
- fix crash and board reset when drawing RLE8 bitmaps
bigger than the framebuffer resolution
- reduce dead code in video and console uclass routines
(tested on mx53cx9020, sama5d2_xplained, stm32mp157c-ev1,
stm32f746-disco, stm32f769-disco and wandboard)
Due to a conversion error the sandbox does not accept byte values 0x80-0xff
from the keyboard. The UEFI extended text input unit test requires Unicode
support.
Use unsigned char for the serial buffer.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
- Increase stack size to avoid a stack overflow during distro boot.
- Add hifive-unleashed-a00.dts for SIFIVE FU540.
- Add OF_SEPARATE support for SIFIVE FU540.
- Add SPL support for Andes AX25 AE350.
- Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.
When ax25-ae350 try to enable v5l2 cache
driver in SPL configuration, it need this
option for cache support in SPL.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
Get flow ID information for RX DMA channel using dma_get_cfg() interface
instead of reading from DT. This is required in order to avoid DT update
whenever there is change in the range of flow ID allocated to the host.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Implement dma_get_cfg() interface to pass flow id information for DMA
clients to use. This is needed because on K3 SoCs, CPSW (ethernet) and
UDMA (DMA provider) support "flows" within a given RX DMA channel. This
allows different network packets to be segregated while using same RX
DMA channel. In order for basic ethernet to work, CPSW slave must be
aware of the flow ID allocated for the RX channel by the DMA driver.
This interface allows CPSW to query flow ID from DMA provider and
configure it in CPSW HW.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Sometimes, there would be a need to exchange data between DMA provider
and DMA client which are very specific to DMA driver of the SoC/platform
and are not generic enough to be put into struct dma. Therefore, introduce
dma_get_cfg() interface to get DMA provider specific data from client
device. Clients can use unique configuration ID flags to get different
configuration data from DMA driver.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Fixes: e766849713 ("net: ftgmac100: convert the RX/TX descriptor arrays")
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This bus is used to access internal SoC PHYs. These PHYs are configured
by the ENETC driver directly, but it's useful to have command line access
to this MDIO to debug the system especially when using new external PHYs.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
On some boards MDIO may get stuck if it detects echo on the line. This is
a know hardware issue, there is a board fix for it. In case we're running
on a board that doesn't have the fix, we don't want to loop here forever
and freeze U-Boot.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This reduces the time needed to establish a link as we don't reset the link
each time the interface is used. Our Link capabilities do not change at
run-time so there is no need to re-apply PHY configuration each time.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The original code enabled link speeds up to 1Gbps, but the interface can
go up to 2.5G, enable that speed to in PHY AN mask.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Uses the new dm_eth_phy_connect helper to connect to the PHY to simplify
the code.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In some cases the link on the system interface of the aquantia PHY comes up
after the link on line interface. The link state loop only checks the line
side, which may result in first packet sent being lost.
Use aquantia_link_is_up instead, which checks both system and line side on
gen 2/3 PHYs to avoid losing the 1st packet.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Aquantia PHYs have a SMBus interface mostly used for debug. The addresses
on this interface are normally set up by PHY firmware, but depending on the
board they may end up not being unique. Add an optional DT property used
to change SMBus address if needed.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
MDI pins up to the RJ45 connector may be reversed on the board and the
default PHY configuration applied by firmware may or may not match that.
Add an optional DT property to configure MDI reversal for this case.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
If PHY is not ready for data by the time _config is called, reconfigure the
PHY system interface to use the proper protocol based on phydev->interface,
just in case the defaults set by PHY firmware don't match current
configuration.
Signed-off-by: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Uses the data field in phy_driver structure to identify the PHY generation.
This is useful for custom configuration as non-generic PHY registers are
not 100% compatible between generations.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The PHY supports XFI and USXGMII, the notable difference being that USX AN
is enabled for USXGMII. Legacy code uses XGMII for any 10G proto and
detects whether USX AN should be enabled or not using a PHY status
register. Keep that functionality too, so we don't break existing drivers.
Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fix vendor name in MV88E61xx option description.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Support probing and init for 88E6071 switch.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
On mv88E6071 the 'EDet' field offset, width and sense control
bits are different, adjust the driver to init the PHY control
register as needed. This fixes not working link detection and
tftp transfers.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
On 88E6071 chip the port status register bit field offsets
for duplex and link bits differ. Extend the driver to use
88E6071 specific offset values. The width of bit fields for
speed status differ, too. Adapt for proper port speed
detection on 88E6071.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Extend the driver to init switch register offsets from variables
instead of compile time macros and enable detection of 88E6071 and
compatible devices. Ethernet transfer (e.g. tftp) does not work yet,
so enable the registration of the 'indirect mii' bus for easier PHY
register access by 'mii' command.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The KSZ8081 PHY has a factory test mode which is set at the de-assertion
of the reset line based on the RXER (KSZ8081RNA/RND) or TXC
(KSZ8081MNX/RNB) pin. If a pull-down is missing, or if the pin has a
pull-up, the factory test mode should be cleared by manually writing a 0
(according to the datasheet).
Create another ksz8081_config function to handle this case.
Suggested-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Aquantia quad-phys may take longer to initialize. This commit adds
a polling mechanism for a global alarm bit that tells if phy init
sequence is completed.
Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
