I lately noticed, that newer 4xx board with GBit support sometimes don't
finish link autonegotiation in 4 seconds. Changing this timeout to 5
seconds seems fine here.
Signed-off-by: Stefan Roese <sr@denx.de>
The POST ethernet test needed to be changed to dynamically determine
the count of ethernet devices. This code is cloned from the 4xx
ethernet driver.
Signed-off-by: Stefan Roese <sr@denx.de>
We now use a value in the gd (global data) structure for the UART input
frequency, since the PPC4xx_SYS_INFO struct is always rewritten completely
in get_sys_info().
Signed-off-by: Stefan Roese <sr@denx.de>
The Haleakala is nearly identical with the Kilauea eval board. The only
difference is that the 405EXr only supports one EMAC and one PCIe
interface. This patch adds support for the Haleakala board by using
the identical image for Kilauea and Haleakala. The distinction is done
by comparing the PVR.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch also adds a note to the fixed DDR setup for Bamboo NAND booting:
Note:
As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
modules are still plugged in. So it is recommended to remove the DIMM
modules while using the NAND booting code with the fixed SDRAM setup!
Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Change 4xx_uart.c:
- Use in_8/out_8 macros instead of in8/out8
- No need for UART_BASE marco anymore, now really handled via function
parameter
- serial_init_common() introduced
- Further coding style cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
Change all linker scripts to reference the changed driver name 4xx_uart.o.
Note: In most cased all these explicit referencing of these object files
in the linker scripts is not neccessary. Only for manually embedded
environment into the U-Boot image, which is not done is most cases.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch starts the rework of the PPC4xx serial driver. First we split
the file into two seperate files, one 4xx_uart.c with the 405/440 UART
handling code and the other one iop480_uart.c with the UART code for the
PLX-Tech IOP480 PPC (PPC403 based).
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds support for the Xicor/Intersil X1205 RTC used on the
AMCC Makalu eval board. This driver is basically cloned from the Linux
driver version (2.6.23).
This patch also introduces the Linux bcd.h header for the BCD2BIN/
BIN2BCD conversions. In the future some of the other U-Boot RTC driver
should be converted to also use this header instead of implementing
their own local copy of these functions/macros.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch moves some common 4xx macros and the PPC405_SYS_INFO/
PPC440_SYS_INFO structure into the common ppc4xx.h header.
Lot's of other macros are good candidates to be consolidated this way
in the future.
Signed-off-by: Stefan Roese <sr@denx.de>
The size was initilized wrong. Instead of 256MB, the DDR2 controller
was setup to 512MB. Now the correct values is used.
This patch also does a little cleanup and adds a comment here.
Signed-off-by: Stefan Roese <sr@denx.de>
CONFIG_BOOKE must be defined for PPC440 processors so that the proper SPR
number is used to access system registers.
Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
On Yucca & Katmai, the inbound memory map pointed to 0x4.0000.0000, which
is the internal SRAM. Since I now ported and tested this endpoint mode
on Kilauea successfully to map to 0 (SDRAM), I also changed this for
Katmai.
Yucca will stay at internal SRAM for now. Not sure if somebody relies on
this setup.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds endpoint support for the AMCC Kilauea eval board. It can
be tested by connecting a reworked PCIe cable (only 1x lane singles
connected) to another root-complex.
In this test setup, a 64MB inbound window is configured at BAR0 which maps
to 0 on the PLB side. So accessing this BAR0 from the root-complex will
access the first 64MB of the SDRAM on the PPC side.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds support for dynamic configuration of PCIe ports for the
AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe
boards Yucca & Katmai and the 405EX board Kilauea.
This dynamic configuration is done via the "pcie_mode" environement
variable. This variable can be set to "EP" or "RP" for endpoint or
rootpoint mode. Multiple values can be joined via the ":" delimiter.
Here an example:
pcie_mode=RP:EP:EP
This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2
as endpoint.
Per default Yucca will be configured as:
pcie_mode=RP:EP:EP
Per default Katmai will be configured as:
pcie_mode=RP:RP:REP
Per default Kilauea will be configured as:
pcie_mode=RP:RP
Signed-off-by: Tirumala R Marri <tmarri@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch enables the fdt support on the AMCC Kilauea eval board.
Additionally now EBC ranges fdt fixup is included to support NOR
FLASH mapping via the Linux physmap_of driver.
This Kilauea port now support booting arch/ppc and arch/powerpc
Linux kernels. The default environment "net_nfs" is for arch/ppc
and "net_nfs_fdt" is for arch/powerpc. In the long run, arch/ppc
support will be removed.
Signed-off-by: Stefan Roese <sr@denx.de>
128MB seems to be the smallest possible value for the memory size
for on PCIe port. With this change now the BAR's of the PCIe cards
are accessible under U-Boot.
One big note: This only works for PCIe port 0 & 1. For port 2 this
currently doesn't work, since the base address is now 0xc0000000
(0xb0000000 + 2 * 0x08000000), and this is already occupied by
CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean
to change the base addresses completely and this change would have
too much impact right now.
This patch adds debug output to the 4xx pcie driver too.
Signed-off-by: Stefan Roese <sr@denx.de>
These files were introduced with the IBM 405GP but are currently used on all
4xx PPC platforms. So the name doesn't match the content anymore. This patch
renames the files to 4xx_pci.c/h.
Signed-off-by: Stefan Roese <sr@denx.de>
(3) This patch introduces macros like SDRN_PESDR_DLPSET(port) to access
the SDR registers of the PCIe ports. This makes the overall design
clearer, since it removed a lot of switch statements which are not
needed anymore.
Also, the functions ppc4xx_init_pcie_rootport() and
ppc4xx_init_pcie_entport() are merged into a single function
ppc4xx_init_pcie_port(), since most of the code was duplicated.
This makes maintainance and porting to other 4xx platforms
easier.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.
(2) This patch renames the functions from 440spe_ to 4xx_ with a
little additional cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.
(1) This patch renames the files from 440spe_pcie to 4xx_pcie
Signed-off-by: Stefan Roese <sr@denx.de>
With this patch PSC3 is configured as UART. This is done, because if
the pins of PSC3 are not configured at all (-> all pins are GPI),
due to crosstalk, spurious characters may be send over the RX232_2_TXD
signal line.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
