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https://github.com/AsahiLinux/u-boot
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ppc4xx: Fix small merge problems with CPCI440 and Acadia boards
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
1941cce71b
commit
db3232ddb0
2 changed files with 1 additions and 257 deletions
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@ -79,7 +79,7 @@ int checkboard (void)
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printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000);
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printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000);
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printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000);
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printf("\tEPB: %lu MHz\n", sysinfo.freqEPB/1000000);
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printf("\tEBC: %lu MHz\n", sysinfo.freqEBC/1000000);
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/*
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* Disable sleep mode in LXT971
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256
include/ppc405.h
256
include/ppc405.h
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@ -742,10 +742,6 @@
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/******************************************************************************
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* Control
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******************************************************************************/
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#define CNTRL_DCR_BASE 0x0C
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#define cprcfga (CNTRL_DCR_BASE+0x0) /* CPR addr reg */
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#define cprcfgd (CNTRL_DCR_BASE+0x1) /* CPR data reg */
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/* CPR Registers */
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#define cprclkupd 0x020 /* CPR_CLKUPD */
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#define cprpllc 0x040 /* CPR_PLLC */
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@ -757,12 +753,6 @@
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#define cprmisc0 0x181 /* CPR_MISC0 */
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#define cprmisc1 0x182 /* CPR_MISC1 */
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/*
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* Macro for accessing the indirect CPR register
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*/
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#define mtcpr(reg, data) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,data); } while (0)
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#define mfcpr(reg, data) do { mtdcr(cprcfga,reg);data = mfdcr(cprcfgd); } while (0)
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#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
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#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
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#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
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@ -783,252 +773,6 @@
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#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
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#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
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#if 0 /* Deprecated */
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#define CNTRL_DCR_BASE 0x0f0
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#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
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#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
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#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
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#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
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#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
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#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
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#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
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#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
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#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
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#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
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#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
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#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
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#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
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#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
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#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
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#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
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/* Bit definitions */
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#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
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#define PLLMR0_CPU_DIV_BYPASS 0x00000000
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#define PLLMR0_CPU_DIV_2 0x00100000
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#define PLLMR0_CPU_DIV_3 0x00200000
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#define PLLMR0_CPU_DIV_4 0x00300000
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#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
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#define PLLMR0_CPU_PLB_DIV_1 0x00000000
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#define PLLMR0_CPU_PLB_DIV_2 0x00010000
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#define PLLMR0_CPU_PLB_DIV_3 0x00020000
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#define PLLMR0_CPU_PLB_DIV_4 0x00030000
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#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
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#define PLLMR0_OPB_PLB_DIV_1 0x00000000
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#define PLLMR0_OPB_PLB_DIV_2 0x00001000
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#define PLLMR0_OPB_PLB_DIV_3 0x00002000
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#define PLLMR0_OPB_PLB_DIV_4 0x00003000
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#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
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#define PLLMR0_EXB_PLB_DIV_2 0x00000000
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#define PLLMR0_EXB_PLB_DIV_3 0x00000100
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#define PLLMR0_EXB_PLB_DIV_4 0x00000200
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#define PLLMR0_EXB_PLB_DIV_5 0x00000300
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#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
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#define PLLMR0_MAL_PLB_DIV_1 0x00000000
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#define PLLMR0_MAL_PLB_DIV_2 0x00000010
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#define PLLMR0_MAL_PLB_DIV_3 0x00000020
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#define PLLMR0_MAL_PLB_DIV_4 0x00000030
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#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
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#define PLLMR0_PCI_PLB_DIV_1 0x00000000
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#define PLLMR0_PCI_PLB_DIV_2 0x00000001
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#define PLLMR0_PCI_PLB_DIV_3 0x00000002
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#define PLLMR0_PCI_PLB_DIV_4 0x00000003
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#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
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#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
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#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
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#define PLLMR1_FBMUL_DIV_16 0x00000000
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#define PLLMR1_FBMUL_DIV_1 0x00100000
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#define PLLMR1_FBMUL_DIV_2 0x00200000
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#define PLLMR1_FBMUL_DIV_3 0x00300000
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#define PLLMR1_FBMUL_DIV_4 0x00400000
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#define PLLMR1_FBMUL_DIV_5 0x00500000
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#define PLLMR1_FBMUL_DIV_6 0x00600000
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#define PLLMR1_FBMUL_DIV_7 0x00700000
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#define PLLMR1_FBMUL_DIV_8 0x00800000
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#define PLLMR1_FBMUL_DIV_9 0x00900000
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#define PLLMR1_FBMUL_DIV_10 0x00A00000
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#define PLLMR1_FBMUL_DIV_11 0x00B00000
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#define PLLMR1_FBMUL_DIV_12 0x00C00000
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#define PLLMR1_FBMUL_DIV_13 0x00D00000
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#define PLLMR1_FBMUL_DIV_14 0x00E00000
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#define PLLMR1_FBMUL_DIV_15 0x00F00000
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#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
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#define PLLMR1_FWDVA_DIV_8 0x00000000
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#define PLLMR1_FWDVA_DIV_7 0x00010000
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#define PLLMR1_FWDVA_DIV_6 0x00020000
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#define PLLMR1_FWDVA_DIV_5 0x00030000
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#define PLLMR1_FWDVA_DIV_4 0x00040000
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#define PLLMR1_FWDVA_DIV_3 0x00050000
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#define PLLMR1_FWDVA_DIV_2 0x00060000
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#define PLLMR1_FWDVA_DIV_1 0x00070000
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#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
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#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
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/* Defines for CPC0_EPRCSR register */
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#define CPC0_EPRCSR_E0NFE 0x80000000
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#define CPC0_EPRCSR_E1NFE 0x40000000
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#define CPC0_EPRCSR_E1RPP 0x00000080
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#define CPC0_EPRCSR_E0RPP 0x00000040
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#define CPC0_EPRCSR_E1ERP 0x00000020
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#define CPC0_EPRCSR_E0ERP 0x00000010
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#define CPC0_EPRCSR_E1PCI 0x00000002
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#define CPC0_EPRCSR_E0PCI 0x00000001
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/* Defines for CPC0_BOOR Register */
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#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
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/* Defines for CPC0_PLLMR1 Register fields */
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#define PLL_ACTIVE 0x80000000
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#define CPC0_PLLMR1_SSCS 0x80000000
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#define PLL_RESET 0x40000000
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#define CPC0_PLLMR1_PLLR 0x40000000
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/* Feedback multiplier */
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#define PLL_FBKDIV 0x00F00000
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#define CPC0_PLLMR1_FBDV 0x00F00000
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#define PLL_FBKDIV_16 0x00000000
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#define PLL_FBKDIV_1 0x00100000
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#define PLL_FBKDIV_2 0x00200000
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#define PLL_FBKDIV_3 0x00300000
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#define PLL_FBKDIV_4 0x00400000
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#define PLL_FBKDIV_5 0x00500000
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#define PLL_FBKDIV_6 0x00600000
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#define PLL_FBKDIV_7 0x00700000
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#define PLL_FBKDIV_8 0x00800000
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#define PLL_FBKDIV_9 0x00900000
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#define PLL_FBKDIV_10 0x00A00000
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#define PLL_FBKDIV_11 0x00B00000
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#define PLL_FBKDIV_12 0x00C00000
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#define PLL_FBKDIV_13 0x00D00000
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#define PLL_FBKDIV_14 0x00E00000
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#define PLL_FBKDIV_15 0x00F00000
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/* Forward A divisor */
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#define PLL_FWDDIVA 0x00070000
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#define CPC0_PLLMR1_FWDVA 0x00070000
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#define PLL_FWDDIVA_8 0x00000000
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#define PLL_FWDDIVA_7 0x00010000
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#define PLL_FWDDIVA_6 0x00020000
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#define PLL_FWDDIVA_5 0x00030000
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#define PLL_FWDDIVA_4 0x00040000
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#define PLL_FWDDIVA_3 0x00050000
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#define PLL_FWDDIVA_2 0x00060000
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#define PLL_FWDDIVA_1 0x00070000
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/* Forward B divisor */
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#define PLL_FWDDIVB 0x00007000
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#define CPC0_PLLMR1_FWDVB 0x00007000
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#define PLL_FWDDIVB_8 0x00000000
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#define PLL_FWDDIVB_7 0x00001000
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#define PLL_FWDDIVB_6 0x00002000
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#define PLL_FWDDIVB_5 0x00003000
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#define PLL_FWDDIVB_4 0x00004000
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#define PLL_FWDDIVB_3 0x00005000
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#define PLL_FWDDIVB_2 0x00006000
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#define PLL_FWDDIVB_1 0x00007000
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/* PLL tune bits */
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#define PLL_TUNE_MASK 0x000003FF
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#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
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#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
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#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
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#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
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#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
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#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
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#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
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/* Defines for CPC0_PLLMR0 Register fields */
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/* CPU divisor */
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#define PLL_CPUDIV 0x00300000
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#define CPC0_PLLMR0_CCDV 0x00300000
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#define PLL_CPUDIV_1 0x00000000
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#define PLL_CPUDIV_2 0x00100000
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#define PLL_CPUDIV_3 0x00200000
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#define PLL_CPUDIV_4 0x00300000
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/* PLB divisor */
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#define PLL_PLBDIV 0x00030000
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#define CPC0_PLLMR0_CBDV 0x00030000
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#define PLL_PLBDIV_1 0x00000000
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#define PLL_PLBDIV_2 0x00010000
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#define PLL_PLBDIV_3 0x00020000
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#define PLL_PLBDIV_4 0x00030000
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/* OPB divisor */
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#define PLL_OPBDIV 0x00003000
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#define CPC0_PLLMR0_OPDV 0x00003000
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#define PLL_OPBDIV_1 0x00000000
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#define PLL_OPBDIV_2 0x00001000
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#define PLL_OPBDIV_3 0x00002000
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#define PLL_OPBDIV_4 0x00003000
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/* EBC divisor */
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#define PLL_EXTBUSDIV 0x00000300
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#define CPC0_PLLMR0_EPDV 0x00000300
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#define PLL_EXTBUSDIV_2 0x00000000
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#define PLL_EXTBUSDIV_3 0x00000100
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#define PLL_EXTBUSDIV_4 0x00000200
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#define PLL_EXTBUSDIV_5 0x00000300
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/* MAL divisor */
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#define PLL_MALDIV 0x00000030
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#define CPC0_PLLMR0_MPDV 0x00000030
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#define PLL_MALDIV_1 0x00000000
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#define PLL_MALDIV_2 0x00000010
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#define PLL_MALDIV_3 0x00000020
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#define PLL_MALDIV_4 0x00000030
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/* PCI divisor */
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#define PLL_PCIDIV 0x00000003
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#define CPC0_PLLMR0_PPFD 0x00000003
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#define PLL_PCIDIV_1 0x00000000
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#define PLL_PCIDIV_2 0x00000001
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#define PLL_PCIDIV_3 0x00000002
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#define PLL_PCIDIV_4 0x00000003
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/*
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*-------------------------------------------------------------------------------
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* PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
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* assuming a 33.3MHz input clock to the 405EP.
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*-------------------------------------------------------------------------------
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*/
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#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
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PLL_MALDIV_1 | PLL_PCIDIV_4)
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#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
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PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
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#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
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PLL_MALDIV_1 | PLL_PCIDIV_4)
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#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
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PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
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#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
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PLL_MALDIV_1 | PLL_PCIDIV_4)
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#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
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PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
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#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
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PLL_MALDIV_1 | PLL_PCIDIV_4)
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#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
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PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
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#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
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PLL_MALDIV_1 | PLL_PCIDIV_2)
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#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
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PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
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/*
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* PLL Voltage Controlled Oscillator (VCO) definitions
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* Maximum and minimum values (in MHz) for correct PLL operation.
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*/
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#define VCO_MIN 500
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#define VCO_MAX 1000
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#endif /* #if 0 */
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#else /* #ifdef CONFIG_405EP */
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/******************************************************************************
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* Control
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