The R40's CPU controls are a combination of sun6i and sun7i.
All controls are in the CPUCFG block, and it seems the R40 does not
have a PRCM block. The core reset, power gating and clamp controls
are grouped like sun6i.
Last, the R40 does not have a secure SRAM block.
This patch adds a PSCI implementation for CPU bring-up and hotplug
for the R40.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that we can do DRAM initialization for the R40, we can enable
SPL support for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
These values were taken from the Banana Pi M2 Ultra fex file
found in the released vendor BSP. This is the only publicly
available R40 device at the time of this writing.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The PIO is generally compatible with the A20, except that it routes the
full 8 bits and eMMC reset pins for mmc2.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The R40 SoC uses the AXP221s in I2C mode to supply power.
Some regulator's common usages have changed, and also the recommended
voltage for existing usages have changed. Update the defaults to match.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The R40 is the successor to the A20. It is a hybrid of the A20, A33
and the H3.
The R40's PIO controller is compatible with the A20,
Reuse the A20 UART and I2C muxing code by adding the R40's macro.
The display pipeline is the newer DE 2.0 variant.
Block enabling video on R40 for now.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Currently we have some lines in board/sunxi/Kconfig that are very long.
These line either provide default values for a set of SoCs, or limit
some option to a subset of sunxi SoCs.
Fortunately Kconfig makes it easy to split them. The Kconfig language
document states
If multiple dependencies are defined, they are connected with '&&'.
This means we can split existing dependencies at "&&" symbols. This
applies to both the "depends on" lines and "if" expressions.
This patch splits them up to one symbol per line. This will make it
easier to add, remove, or modify one item at a time.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Convert the CONFIG_MACPWR to Kconfig and update all the sunxi defconfigs
that used it in SYS_EXTRA_OPTIONS.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Convert the CONFIG_SATAPWR into kconfig.
Thanks to that, many SYS_EXTRA_OPTIONS can be removed from some
defconfigs.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
As board-specific reset logic, it needs to issue reset signal
via CPLD when issuing 'reset' command in u-boot, this patch
solves the issue of reset command not working on T1024RDB.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
- Add SD secure boot target for ls1046ardb.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size
as header is appended to u-boot image. So header will also be
copied from SD to DDR.
- CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM
(128K) where 32K are reserved for use by boot ROM and 6K for the
header.
- Reduce the size of CAAM driver for SPL Blobification functions
and descriptors, that are not required at the time of SPL are
disabled. Further error code conversion to strings is disabled
for SPL build.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add NAND secure boot target for ls1043ardb.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size as
header is appended to u-boot image. So header will also be copied
from SD to DDR.
- MACRO for CONFIG_BOOTSCRIPT_COPY_RAM is enabled to copy Bootscript
from NAND to DDR. Offsets for Bootscript on NAND and DDR have been
also defined.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
- Add SD secure boot target for ls1043ardb.
- Implement FSL_LSCH2 specific spl_board_init() to setup CAAM stream
ID and corresponding stream ID in SMMU.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size as
header is appended to u-boot image. So header will also be copied
from SD to DDR.
- CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM
(128K) where 32K are reserved for use by boot ROM and 6K for secure
boto header.
- Error messages during SPL boot are limited to error code numbers
instead of strings to reduce the size of SPL image.
Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Using changes in this patch we were able to reduce approx 4k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1046ardb/Makefile to remove
compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescale/ls1046ardb/ls1046ardb.c to keep
only ddr_init and board_early_init_f funcations in case of SPL
build.
3. Changes in ls1046a_common.h & ls1046ardb.h to remove driver
specific macros due to which static data was being compiled in
case of SPL build.
4. Disable MMC driver from bieng compiled in case of SPL NAND
build and NAND driver from bieng compiled in case of SPL MMC build.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Using changes in this patch we were able to reduce approx 10k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1043ardb/Makefile to remove
compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescale/ls1043ardb/ls1043ardb.c to keep
only ddr_init and board_early_init_f funcations in case of SPL
build.
3. Changes in ls1043a_common.h & ls1043ardb.h to remove driver
specific macros due to which static data was being compiled in
case of SPL build.
4. Disable MMC driver from bieng compiled in case of SPL NAND
build and NAND driver from bieng compiled in case of SPL MMC build.
5. Remove I2C driver support from SPL in case of LS1043ARDB.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The RK3399-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
Rockchip RK3399.
It provides the following feature set:
* up to 4GB DDR3
* on-module SPI-NOR flash
* on-module eMMC (with 8-bit interace)
* SD card (on a baseboad) via edge connector
* Gigabit Ethernet w/ on-module Micrel KSZ9031 GbE PHY
* HDMI/eDP/MIPI displays
* 2x MIPI-CSI
* USB
- 1x USB 3.0 dual-role (direct connection)
- 2x USB 3.0 host + 1x USB 2.0 (on-module USB 3.0 hub)
* on-module STM32 Cortex-M0 companion controller, implementing:
- low-power RTC functionality (ISL1208 emulation)
- fan controller (AMC6821 emulation)
- USB<->CAN bridge controller
Note that we use a multi-payload FIT image for booting and have
Cortex-M0 payload in a separate subimage: we thus rely on the FIT
image loader to put it into the SRAM region that ATF expects it in.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fixed build warning on puma-rk3399:
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Update the configuration files to support the device tree and driver
model, so do SPL. The device clock and pins configuration are handled
by the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Fix build error with sama5d3_xplained_mmc:
Signed-off-by: Simon Glass <sjg@chromium.org>
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Remove CONFIG_PHY_MICREL as per previous patch:
Signed-off-by: Simon Glass <sjg@chromium.org>
Update the configuration files to support the device tree and
driver model, so do SPL. The device clock and pins configuration
are handled by the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Add back CONFIG_PHY_MICREL to prevent a build error:
Signed-off-by: Simon Glass <sjg@chromium.org>
The Vybrid SoC family has the same display controller unit (DCU)
like the LS1021A SoC. This patch adds platform data, pinmux defines
and clock control to enable the driver for Toradex Colibri Vybrid
module.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Rename CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB
and convert it to Kconfig.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Update the configuration files to support the device tree and driver
model, so do SPL. The device clock and pins configuration are handled
by the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Update the configuration files to support the device tree and
driver model, so do SPL. The device clock and pins configuration
are handled by the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
The intention of the removal is the preparation to introduce the
new AT91 PIO pinctrl driver.
Use the union to make the PIO3 and PIO2's registers be together
and make their offset aligned.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This allows us to use the same DRAM init function on all archs. Add a
dummy function for arc, which does not use DRAM init here.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Dummy function on nios2]
Signed-off-by: Tom Rini <trini@konsulko.com>
This function name shadows a global name but is in fact different. This
is very confusing. Rename it to help with the following refactoring.
Signed-off-by: Simon Glass <sjg@chromium.org>
Logic PD has an i.MX6Q system on module (SOM) with a development kit. The
SOM has a built-in microSD socket, DDR and NAND flash. The development kit
has an SMSC Ethernet PHY, serial debug port and a variety of peripherals.
This have been verified to boot the i.MX6Q version over either SD
on the development kit or NAND built into the SOM. Items in the dtsi file
are specific to the SOM itself. Items in the dts file are in the baseboard.
Future versions of the SOM will come out supporting the same basebord and
potentially future base boards will come out supporting the same SOM.
Signed-off-by: Adam Ford <aford173@gmail.com>
Explain how to flash the eMMC and how to boot from it.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
to avoid the voltage peak issue while we do the IEEE PHY comformance test
Signed-off-by: Ken Lin <yungching0725@gmail.com>
Acked-by: Akshay Bhat <akshay.bhat@timesys.com>
Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet
Signed-off-by: Ken Lin <yungching0725@gmail.com>
Acked-by: Akshay Bhat <akshay.bhat@timesys.com>
Change the PMIC bulk configuration from auto mode to sync mode to avoid the voltage shutdown issue
Signed-off-by: Ken Lin <yungching0725@gmail.com>
Acked-by: Akshay Bhat <akshay.bhat@timesys.com>
Add the configuration options for display initialization in case we need to
do the display initialization in kernel to support different timing settings
Signed-off-by: Ken Lin <yungching0725@gmail.com>
Acked-by: Akshay Bhat <akshay.bhat@timesys.com>
spl_mmc.c calls mmc_initialize(). This symbol is provided in
drivers/mmc/mmc.c when CONFIG_GENERIC_MMC is enabled.
The sunxi Kconfig case is an oddball because it redefines
SPL_MMC_SUPPORT.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
[trini: Update arch/arm/cpu/armv8/zynqmp/Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
BeagleBone Blue is next grenation of boards from BeagleBoard.org, focusing
on robotics with a TI wl1835 wireless module for connectivity.
This board can be indentified by the BLAx value after A335BNLT (BBB)
in the at24 eeprom:
BLAx: [aa 55 33 ee 41 33 33 35 42 4e 4c 54 42 4c 41 30 |.U3.A335BNLTBLA2|]
http://beagleboard.org/bluehttps://github.com/beagleboard/beaglebone-blue
firmware: https://github.com/beagleboard/beaglebone-black-wireless/tree/master/firmware
wl18xx mac address: /proc/device-tree/ocp/ethernet@4a100000/slave@4a100200/mac-address
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
CC: Tom Rini <trini@konsulko.com>
CC: Jason Kridner <jkridner@beagleboard.org>
CC: Will Newton <willn@resin.io>
Reviewed-by: Tom Rini <trini@konsulko.com>
SeeedStudio BeagleBone Green Wireless (BBGW) is an expansion of the
SeeedStudio Green (BBG) with the Ethernet replaced by a TI wl1835
wireless module.
This board can be indentified by the GW1x value after A335BNLT (BBB)
in the at24 eeprom:
GW1x [aa 55 33 ee 41 33 33 35 42 4e 4c 54 47 57 31 41 |.U3.A335BNLTGW1A|]
http://beagleboard.org/green-wirelesshttp://wiki.seeed.cc/BeagleBone_Green_Wireless/
firmware: https://github.com/beagleboard/beaglebone-black-wireless/tree/master/firmware
wl18xx mac address: Stored in at24 eeprom at address 5-16:
hexdump -e '8/1 "%c"' /sys/bus/i2c/devices/0-0050/eeprom | cut -b 5-16
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
CC: Tom Rini <trini@konsulko.com>
CC: Jason Kridner <jkridner@beagleboard.org>
CC: Will Newton <willn@resin.io>
Reviewed-by: Tom Rini <trini@konsulko.com>
BeagleBone Black Wireless is clone of the BeagleBone Black (BBB) with
the Ethernet replaced by a TI wl1835 wireless module.
This board can be indentified by the BWAx value after A335BNLT (BBB)
in the at24 eeprom:
BWAx [aa 55 33 ee 41 33 33 35 42 4e 4c 54 42 57 41 35 |.U3.A335BNLTBWA5|]
http://beagleboard.org/black-wirelesshttps://github.com/beagleboard/beaglebone-black-wireless
firmware: https://github.com/beagleboard/beaglebone-black-wireless/tree/master/firmware
wl18xx mac address: /proc/device-tree/ocp/ethernet@4a100000/slave@4a100200/mac-address
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
CC: Tom Rini <trini@konsulko.com>
CC: Jason Kridner <jkridner@beagleboard.org>
CC: Will Newton <willn@resin.io>
Reviewed-by: Tom Rini <trini@konsulko.com>
As per the latest pinmux data available for AM572x EVM,
rev A3, input should be enabled on MMC clock lines for
MMC2/2/3 for stable operation.
Further, AM572x TRM, SPRUHZ6, Revised June 2016, in
section 18.4.6.1.1 "Pad Configuration Registers" states
that input should be enabled for MMC 2/3/4 clock lines.
Enable input on MMC1 and MMC3 clock to match the latest
pinmux data. Input is already enabled on MMC2 clock for
BeagleBoard x15. Further, input is already enabled on all
MMCx clocks for other AM57xx boards (AM572x and AM571x
IDK).
Tested with HS and UHS SD card on AM572x EVM Rev A3.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
The Sunchip CX-A99 is a board used in some media players. It features:
An Allwinner A80 ARM SoC (4 * Cortex-A7 + 4 * Cortex-A15 cores)
2 GiB or 4 GiB DDR3 DRAM
AXP808 PMIC
16 GB or 32 GB eMMC
SDIO Wifi/Bluetooth/FM module
SD card slot
1 USB 3.0 connector
2 USB 2.0 connectors
SATA connector
UART connector (internally) for serial console
Ethernet connector (10/100/1000 Mbit/s)
HDMI connector
Composite video and analog audio connector
S/PDIF connector
IR remote control receiver
This patch adds a defconfig for the board. The DRAM settings are as found
in the vendor sys_config.fex file.
It has a preliminary device tree for use until a device tree is accepted
upstream, after which it can be replaced by the upstream version.
Signed-off-by: Rask Ingemann Lambertsen <rask@formelder.dk>
[squash commits, and edited new meanful commit message]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Introduce a new sunxi-spl-with-ecc.bin image with already the right header,
ECC, randomizer and padding for the BROM to be able to read it.
It needs to be flashed using a raw access to the NAND so that the
controller doesn't change a thing to it, since we already have all the
right parameters.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Remove the board_power_init() function.
It will be initialized with device-tree.
In future, it will be controlled with regulator API.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Remove the unused functions.
Never call the get_soft_i2c_scl/sda_pin() aynwhere.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Remove the board_i2c_init() function.
i2c should be initialized with device-tree file.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
With d53ecad92f some unused interrupt related code was removed.
However all of these options are currently unused. Rather than migrate
some of these options to Kconfig we just remove the code in question.
The only related code changes here are that in some cases we use
CONFIG_STACKSIZE in non-IRQ related context. In these cases we rename
and move the value local to the code in question.
Fixes: d53ecad92f ("Merge branch 'master' of git://git.denx.de/u-boot-sunxi")
Signed-off-by: Tom Rini <trini@konsulko.com>
By making dram_init_banksize() return an error code we can drop the
wrapper. Adjust this and clean up all implementations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
At present we cannot use this function as an init sequence call without a
wrapper, since it returns the RAM size. Adjust it to set the RAM size in
global_data instead, and return 0 on success.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
It looks like only cm5200 and tqm8xx use this feature, so we don't really
need it in generic code. Drop it and have the users access gd->board_type
directly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
This is not used by any board. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Clean up board_f sequence a little
This series tries to remove #ifdefs from the board_f init sequence. It
gets as far as I2C and then we need to discuss whether we can start to
remove the old I2C framework.
I think that ideally each entry in the init sequence should be enabled by
at most one CONFIG, which is in Kconfig and is not arch-specific.
END
Acked-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
There is no good reason to use a different name on PowerPC. Change it to
timer_init() like the others.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The OpenRISC architecture is currently unmaintained, remove.
Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
Add a (64-bit only) defconfig defining the required options to build
the U-Boot proper.
Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi
and changing the differing components accordingly.
This is a preliminary device tree mostly for U-Boot's own sake, it
is expected to be updated once the official DT gets accepted upstream.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[squash the commits, update the commit message]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The Allwinner H5 Soc is bascially an H3 with high SRAM and ARMv8 cores.
As the peripherals and the pinmuxing are almost identical, we piggy
back on the shared MACH_SUN8I_H3_H5 config symbol.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores.
To allow sharing the clocks, GPIO and driver code easily, create an
architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol.
Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and
let it be selected by a new shared Kconfig option.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Traditionally Allwinner SoCs have their boot ROM mapped just below 4GB,
while the first SRAM region is mapped at address 0.
With the extended physical memory support of the A80 this was changed,
so the BROM is now at address 0 and the SRAM region starts right behind
this at 64KB. This configuration seems to be called "high SRAM".
Instead of enumerating the SoCs which have copied this configuration,
let's call a spade a spade and introduce a Kconfig option for this setup.
SoCs implementing this (A80, A64 and H5, so far), can then select this
configuration.
Simplify the config header definition on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Instead of enumerating all SoC families that need that bit set, let's
just express this more clearly: The SMP bits needs to be set on
SMP capable ARMv7 CPUs. It's much easier in Kconfig to express it the
other way round, so we use ! CPU_IS_UP and ! ARM64.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Many ARMv8 boards define a constant COUNTER_FREQUENCY to specify the
frequency of the ARM Generic Timer (aka. arch timer).
ARMv7 boards traditionally used CONFIG_TIMER_CLK_FREQ for the same
purpose. It seems useful to unify them.
Since there are less occurences of the latter version, lets convert all
users over to COUNTER_FREQUENCY.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
expansion ports.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The Rock is a RK3188 based single board computer by Radxa.
Currently it still relies on the proprietary DDR init and
cannot use the generic SPL, but at least is able to boot
a linux kernel and system up to a regular login prompt.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix sort order in defconfig, enable CONFIG_SPL_TINY_MEMSET:
Signed-off-by: Simon Glass <sjg@chromium.org>
i2c should be initialized with device-tree.
This function doesn't need anymore.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Convert to driver model for controlling phy.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
These codes are unnecessary, because max8997 should be initialized with
dt-file.
Remove max8997_init() function.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds board support for the Toradex Apalis TK1 a computer on
module which can be used on different carrier boards.
The module consists of a Tegra TK1 SoC, a PMIC solution, 2 GB of DDR3L
RAM, a bunch of level shifters, an eMMC, a TMP451 temperature sensor
chip, an I210 gigabit Ethernet controller and a SGTL5000 audio codec.
Furthermore, there is a Kinetis MK20DN512 companion micro controller for
analogue, CAN and resistive touch functionality.
For the sake of ease of use we do not distinguish between different
carrier boards for now as the base module features are deemed
sufficient enough for regular booting.
The following functionality is working so far:
- eMMC boot, environment storage and Toradex factory config block
- Gigabit Ethernet
- MMC/SD cards (both MMC1 as well as SD1 slot)
- USB client/host (dual role OTG port as client e.g. for DFU/UMS or host,
other two ports as host)
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
In axs103 v1.1 procedure to kick-start slave cores has changed quite a bit
compared t previous implementation.
In particular:
* We used to have a generic START bit for all cores selected by CORE_SEL
mask. But now we don't touch CORE_SEL at all because we have a dedicated
START bit for each core:
bit 0: Core 0 (master)
bit 1: Core 1 (slave)
* Now there's no need to select "manual" mode of core start
Additional challenge for us is how to tell which axs103 firmware we're
dealing with. For now we'll rely on ARC core version which was bumped
from 2.1c to 3.0.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* Rely on default pulse polarity value
* Don't mess with "multicore" value as it doesn't affect execution
In essence we now do a bare minimal stuff:
1) Select HS38x2_1 with CORE_SEL=1 bits
2) Select "manual" core start (via CREG) with START_MODE=0
3) Generate cpu_start pulse with START=1
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
For validating images from uboot (Such as Kernel Image), either keys
from SoC fuses can be used or keys from a verified table of public
keys can be used. The latter feature is called IE Key Extension
Feature.
For Layerscape Chasis 3 based platforms, IE table is validated by
Bootrom and address of this table is written in scratch registers 13
and 14 via PBI commands.
Following are the steps describing usage of this feature:
1) Verify IE Table in ISBC phase using keys stored in fuses.
2) Install IE table. (To be used across verification of multiple
images stored in a static global structure.)
3) Use keys from IE table, to verify further images.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Moved the ifdef into ppa.h and removed the duplicated macros.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Moves sec_init to board_init rather than in misc_init function beacuse
PPA will be initialised in board_init function and for PPA validation
sec_init has to be done prior to PPA init.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
to avoid the voltage peak issue while we do the IEEE PHY comformance test
Signed-off-by: Ken Lin <yungching0725@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Ian Ray <ian.ray@ge.com>
Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet
Signed-off-by: Ken Lin <yungching0725@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Ian Ray <ian.ray@ge.com>
This replaces legacy arch/arc/lib/timer.c implementation and allows us
to describe ARC Timers in Device Tree. Among other things that way we
may properly inherit Timer's clock from CPU's clock s they really run
synchronously.
We want to use the same device tree blobs in both Linux and U-Boot for
ARC boards.
Earlier device tree sources in U-Boot were very simplified and hadn't been
updated for quite a long period of time.
So this commit is the first step on the road to unified device tree blobs.
First of all we re-organize device tree sources for AXS10X boards.
As AXS101 and AXS103 boards consist of AXS10X motherboard and AXC001 and
AXC003 cpu tiles respectively we add corresponding device tree source
files: axs10x_mb.dtsi for motherboard, axc001.dtsi and axc003.dtsi for
cpu tiles and axs101.dts and axs103.dts to represent actual boards.
Also we delete axs10x.dts as it is no longer used.
One more important change - we add timer device to ARC skeleton device
tree sources as both ARC700 and ARCHS cores contain such timer.
We add core_clk nodes to abilis_tb100, nsim, axc001 and axc003 device tree
sources as it is referenced via phandle from timer node in common
skeleton.dtsi file.
Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The gdsys ControlCenter Digital board is based on a Marvell Armada 38x
SOC.
It boots from SPI-Flash but can be configured to boot from SD-card for
factory programming and testing.
On board peripherals include:
- 2 x GbE
- Xilinx Kintex-7 FPGA connected via PCIe
- mSATA
- USB3 host
- Atmel TPM
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
This board specific command tests for the presence of a specified PCIe
device (via vendor-ID and device-ID). If the device is not detected,
this will get printed. If the device is detected, the board will get
resetted so that an easy loop test can be done. The board will reboot
until the PCIe device is not detected.
Signed-off-by: Stefan Roese <sr@denx.de>
Define a board-specific detection pulse-width array for the SerDes PCIe
interfaces. If not defined in the board code, the default of currently 2
is used. Values from 0...3 are possible (2 bits).
In this case of the theadorable board, PEX interface 0 needs a value
of 0 for the detection pulse width so that the PCIe device (Atheros
WLAN PCIe device) is consistantly detected.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Adam Shobash <adams@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Bypass XHCI and AHCi board configuration flow on ESPRESSOBin
community board.
The community board does not have i2c expander and USB VBUS
is always on, so the scan for AHCi and USB devices can be
faster without unneded configurations.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Implement the board-specific network init function for
ESPRESSOBin community board, setting the on-board Topaz
switch port to forward mode and allow network connection
through any of the available Etherenet ports.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Fix the default pin control values in a board-specific
function on early board init stage.
This fix allows the NETA driver to work in RGMII
mode until the full-featured pin control driver gets
introduced.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Modify the file names and deifinitions relater to Marvell
db-77f3720 board support. Convert these names to more generic
armada-37xx platform for future addition of more boards
based on the same SoC family.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Add support for the Broadcom Northstar2 SoC and SVK (bcm958712k). The
BCM5871X is a series of quad-core 64-bit 2GHz ARMv8 Cortex-A57
processors targeting a broad range of networking applications.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
PRU ethernet MAC address range is present in the
board EEPROM. Parse it and setup eth?addr
environment variables.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
In stead of defining the board EEPROM address in the board headers
let's define them in the board config files and make them
configurable by Kconfig.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
AM571x IDK and AM572x IDK have optional LCD Kits that can be purchased.
These can be one of OSD101T2045 or the newer OSD101T2587. The LCD panel
itself has no registers that can be used to identify the panel, however,
the touchscreen controllers on the panels are different.
Hence to ease user experience, we can use the touch screen controller's
ID information to detect what kind of panel we use and select the
appropriate kernel dtb for the platform configuration.
NOTE: AM572x IDK default configuration is for LCD Connectivity, however
the AM571x IDK has a jumper (J51) that needs to be mounted for the IDK
to operate with LCD (Vs two PRUSS ethernet port option).
Touchscreen ID information is documented in:
http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Use the same convention that was used for ICSS1 Ethernet
- If pin is output, set as PIN_OUTPUT
- If pin is input and external pull resistor present set as PIN_INPUT
- If pin is input and external pull resistor absent, set pull to same
as that of the external PHY's internall pull.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
The board can support either ICSS1 Ethernet ports or LCD
based on J51 jumper. Factory default is ICSS1 Ethernet ports
(i.e. Jumper not populated).
Use the GPIO to detect the jumper setting and configure the
pinmux accordingly. Also select the right DT blob based on
the chosen configuration.
J51 absent -> ICSS1 Ethernet, no LCD on VOUT -> am571x-idk.dtb
J51 present -> LCD on VOUT, no ICSS1 Ethernet -> am571x-idk-lcd-osd.dtb
At present we only support the assume it is the Legacy LCD.
LCD detection mechanism needs to be added later to differentiate
between legacy vs new LCD.
For ICSS1 Ethernet pins use the following convention to set the pinmux
as PMT data is not yet finalized.
- If pin is output, set as PIN_OUTPUT
- If pin is input and external pull resistor present set as PIN_INPUT
- If pin is input and external pull resistor absent, set pull to same
as that of the external PHY's internall pull.
- Do not use SLEW_CONTROLon any pin.
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Keystone and OMAP platforms will need this to set ethernet
MAC addresses from board EEPROM.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Non OMAP platforms i.e. Keystone will also need to use the board
EEPROM helpers so let's make the macro platform independent.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enable more DM drivers. The imx I2C/MMC DM drivers needs DM_GPIO
enabled. So needs to enable them together.
DM FEC and SPI are not enabled, but they use gpio in board code.
So use gpio_request first to request the gpio, because DM_GPIO
is enabled.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
To keep a consistent MMC device mapping in SPL and in u-boot, let's
register the MMC controllers the same way in u-boot and in the SPL.
In terms of boot time, it doesn't hurt to register more controllers than
needed because the MMC device is initialized only prior being accessed for
the first time.
Having the same device mapping in SPL and u-boot allows us to use the
environment in SPL whatever the MMC boot device.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Move Freescale/NXP Vybrid to a standard arch/board approach, similar
to what has been done to i.MX 6 earlier in commit 89ebc82137 ("ARM:
mx6: move to a standard arch/board approach").
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Use device-tree fixup to communicate the MTD partitions to the
kernel. Remove mtdparts from the kernel command line.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Implement board level USB PHY mode callback. On USB OTG Port 1
the Colibri standard foresees GPIO USBC_DET to decide whether the
port should run in Host or Device mode.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
OPOS6UL is an i.MX6UL based SoM with 256MB RAM, 4GB eMMC and an ethernet
phy. OPOS6ULDev is carrier board for the OPOS6UL.
U-Boot SPL 2017.03-rc3-00002-g5085c26 (Mar 07 2017 - 09:48:09)
Trying to boot from MMC1
U-Boot 2017.03-rc3-00002-g5085c26 (Mar 07 2017 - 09:48:09 +0100)
CPU: Freescale i.MX6UL rev1.0 528 MHz (running at 396 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 40C
Reset cause: POR
Model: Armadeus Systems OPOS6UL SoM on OPOS6ULDev board
DRAM: 256 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Video: 800x480x18
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang. Also included is SPL support for rk3399 and a fix for
rk3288 to get it booting again (spl_early_init()).
Before clock driver availability it was required to enable usart1 clock
for serial init but now with clock driver is taking care of usart1 clock.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
This patch adds device tree support for stm32f7 serial driver & removes serial
platform data structure.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds support for TQMa6DL using i.MX6DL and 1GiB DRAM
Since The module will use the same devicetree, we patch
the ram size in ft_board_setup.
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
We have a Kconfig name for the module types. Let's Use it.
Some feature selections and configurations are based on the
module. Module selection selects the CPU type.
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
Add board_mmc_get_env_dev
Switch the mmc env based on the mmc devno, instead of separately
defining a config item in include/configs using board_mmc_get_env_dev
- devno 0: sd/esd
- devno 1: mmc/emmc
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Let the runtime code can set the mmcdev and mmcroot based
on the devno using mmc_get_env_dev instead of defining
separately in build-time configs using mmc_late_init func.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add runtime, modeboot env which is setting mmcboot based
on the bootdevice so-that conditional macros for MMC via
CONFIG_BOOTCOMMAND should be avoided in config files.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Boot from eMMC:
--------------
U-Boot SPL 2017.01-00318-g8e243f8 (Jan 26 2017 - 11:53:21)
Trying to boot from MMC2
U-Boot 2017.01-00318-g8e243f8 (Jan 26 2017 - 11:53:21 +0100)
CPU: Freescale i.MX6D rev1.2 at 792 MHz
Reset cause: POR
Model: Engicam i.CoreM6 Quad/Dual RQS Starter Kit
DRAM: 512 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
switch to partitions #0, OK
mmc1(part 0) is current device
Net: No ethernet found.
Hit any key to stop autoboot: 0
Booting from mmc ...
switch to partitions #0, OK
mmc1(part 0) is current device
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Since the CS are not in use, do not map them. User of starterkit
mainboard is free to use them otherwise. When using these pins later
in the OS for instance as GPIO IRQ pin, they need to be input.
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
The current driver stength is too high, leading to spec violations
on the falling edge. Fix it with values from HW
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
SPL mmc device index is get based on the boot device, like
- BOOT_DEVICE_MMC1 for mmc device 0
- BOOT_DEVICE_MMC2 for mmc device 1
Currently BOOT_DEVICE_MMC1 is setting both SD/eSD and MMC/eMMC
boot devices in i.MX, So u-boot is loading from mmc device 0 even
"if the board booting from SD/eSD or MMC/eMMC"
So, this patch set BOOT_DEVICE_MMC2 for MMC/eMMC so for MMC/eMMC
the u-boot is loading from mmc device 1 and the board file need to
take care if the board have different mmc device order intialization.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add board_mmc_get_env_dev
Switch the mmc env based on the mmc devno, instead of separately
defining a config item in include/configs using board_mmc_get_env_dev
- devno 0: sd/esd
- devno 1: mmc/emmc
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Let the runtime code can set the mmcdev and mmcroot based
on the devno using mmc_get_env_dev instead of defining
separately in build-time configs using mmc_late_init func.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add runtime, modeboot env which is setting mmcboot, or
nandboot based on the bootdevice so-that conditional
macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should
be avoided in config files.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
SPL mmc device index is get based on the boot device, like
- BOOT_DEVICE_MMC1 for mmc device 0
- BOOT_DEVICE_MMC2 for mmc device 1
Currently BOOT_DEVICE_MMC1 is setting both SD/eSD and MMC/eMMC
boot devices in i.MX, So u-boot is loading from mmc device 0 even
"if the board booting from SD/eSD or MMC/eMMC"
So, this patch set BOOT_DEVICE_MMC2 for MMC/eMMC so for MMC/eMMC
the u-boot is loading from mmc device 1 and the board file need to
take care if the board have different mmc device order intialization.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
dts files related to i.MX6 engicam boards are maintined
under board, so include them under board/engicam/*/MAINTAINERS
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Boot from MMC:
-------------
U-Boot SPL 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33)
Trying to boot from MMC1
U-Boot 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33 +0100)
CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 33C
Reset cause: POR
Model: Engicam Is.IoT MX6UL Starterkit
DRAM: 512 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
isiotmx6ul>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
evb-rk3328 is an evb from Rockchip based on rk3328 SoC:
- 2 USB2.0 Host port;
- 1 USB3.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;
Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Leave only detected flash type enabled in FTD as otherwise GPMC CS is
claimed (and never freed) by Linux, causing 'concurent' flash type
not to be probed.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
This is a 96Board compliant board based on STiH410 SoC:
- 1GB DDR
- On-Board USB combo WiFi/Bluetooth RTL8723BU
with PCB soldered antenna
- Ethernet 1000-BaseT
- SATA
- HDMI
- 2 x USB2.0 type A
- 1 x USB2.0 type micro-AB
- SD card slot
- High speed connector (SD/I2C/USB interfaces)
- Low speed connector (UART/I2C/GPIO/SPI/PCM interfaces)
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like
LS2088A, LS2080A differs from existing logic.
-VDD voltage array is different
-Registers are different
-VDD calculation logic is different
Add new function adjust_vdd() for LSCH3 compliant SoCs
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Arpit Goel <arpit.goel@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
In early MMU table, DDR has to be mapped as device memory to avoid
speculative access. After DDR is initialized, it needs to be updated
to normal memory to allow code execution. To simplify the code,
dram_init() is moved into a common file as a weak function.
Signed-off-by: York Sun <york.sun@nxp.com>
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved
at the end of DDR. DDR is spit into two or three banks. This patch
reverts commit aabd7ddb and simplifies the calculation of reserved
memory, and moves the code into common SoC file. Secure memory is
carved out first. DDR bank size is reduced. Reserved memory is then
allocated on the top of available memory. U-Boot still has access
to reserved memory as data transferring is needed. Device tree is
fixed with reduced memory size to hide the reserved memory from OS.
The same region is reserved for efi_loader.
Signed-off-by: York Sun <york.sun@nxp.com>
The option that we had set in board/ti/common/Kconfig as default y are
best done with imply under the appropriate main Kconfig option instead.
Signed-off-by: Tom Rini <trini@konsulko.com>
These particular SPL options are part of what the ROM provides, but for
compatibility with how we have previously used them, move them to being
implied by the board being selected.
Signed-off-by: Tom Rini <trini@konsulko.com>
In some cases this is absolutely required, so select this for some secure
features. This also requires migration of RSA_FREESCALE_EXP
Cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: Naveen Burmi <NaveenBurmi@freescale.com>
Cc: Po Liu <po.liu@freescale.com>
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: Priyanka Jain <Priyanka.Jain@freescale.com>
Cc: Sumit Garg <sumit.garg@nxp.com>
Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
Cc: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Feng Li <feng.li_2@nxp.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Mingkai Hu <Mingkai.Hu@freescale.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Saksham Jain <saksham.jain@nxp.freescale.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
The da850 soc's can boot from a external mmc card, but
the AIS image should be written to the correct sector.
Add instructions to copy the AIS image to a MMC card.
Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
serial# variable is used to correctly display device ID in
"fastboot devices". It also can be used further for displaying device ID
in "adb devices" (should be passed as "androidboot.serialno" to kernel
cmdline, via "bootargs" variable).
Serial number generating algorithm is described at [1].
[1] http://lists.denx.de/pipermail/u-boot/2015-March/207462.html
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
We repeated partial moves for CONFIG_SYS_NO_FLASH, but this is
not completed. Finish this work by the tool.
During this move, let's rename it to CONFIG_MTD_NOR_FLASH.
Actually, we have more instances of "#ifndef CONFIG_SYS_NO_FLASH"
than those of "#ifdef CONFIG_SYS_NO_FLASH". Flipping the logic will
make the code more readable. Besides, negative meaning symbols do
not fit in obj-$(CONFIG_...) style Makefiles.
This commit was created as follows:
[1] Edit "default n" to "default y" in the config entry in
common/Kconfig.
[2] Run "tools/moveconfig.py -y -r HEAD SYS_NO_FLASH"
[3] Rename the instances in defconfigs by the following:
find . -path './configs/*_defconfig' | xargs sed -i \
-e '/CONFIG_SYS_NO_FLASH=y/d' \
-e 's/# CONFIG_SYS_NO_FLASH is not set/CONFIG_MTD_NOR_FLASH=y/'
[4] Change the conditionals by the following:
find . -name '*.[ch]' | xargs sed -i \
-e 's/ifndef CONFIG_SYS_NO_FLASH/ifdef CONFIG_MTD_NOR_FLASH/' \
-e 's/ifdef CONFIG_SYS_NO_FLASH/ifndef CONFIG_MTD_NOR_FLASH/' \
-e 's/!defined(CONFIG_SYS_NO_FLASH)/defined(CONFIG_MTD_NOR_FLASH)/' \
-e 's/defined(CONFIG_SYS_NO_FLASH)/!defined(CONFIG_MTD_NOR_FLASH)/'
[5] Modify the following manually
- Rename the rest of instances
- Remove the description from README
- Create the new Kconfig entry in drivers/mtd/Kconfig
- Remove the old Kconfig entry from common/Kconfig
- Remove the garbage comments from include/configs/*.h
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
We don't ever search for these so there is no need for a 4KB alignment.
It just wastes space.
Drop this and use the standard 4-byte alignment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Miniarm is the internal project code. Now it is officially named Tinker board.
So rename it.
Signed-off-by: Eddie Cai <eddie.cai@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is wrong at present, so genboardscfg.py gives the following warnings:
WARNING: no status info for 'chromebook_minnie'
WARNING: no maintainers for 'chromebook_minnie'
Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
The sequence erroneously launched the DDR controller
initialization before the pad muxing was done, causing
DRAM size computation to hang.
Configuring the pads first then launching DDR controller
initialization prevents the DRAM hanging.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a new board config which uses 64-bit U-Boot. Supported features
are the same as the other 64-bit board (Google Chromebook Link).
It is a start for us to test 64-bit U-Boot easily without the need
to access a real hardware.
Note CONFIG_SPL_ENV_SUPPORT is required for QEMU 64-bit as without
this the SPL build fails at the end. This is just a workaround as
CONFIG_SPL_ENV_SUPPORT is not needed at all.
common/built-in.o:(.data.env_htab+0xc): undefined reference to 'env_flags_validate'
lib/built-in.o: In function `hsearch_r':
lib/hashtable.c:380: undefined reference to 'env_callback_init'
lib/hashtable.c:382: undefined reference to 'env_flags_init'
make[1]: *** [spl/u-boot-spl] Error 1
Except those SPL options required by 64-bit, compared to 32-bit
config, the following options are different:
- CONFIG_SYS_MALLOC_F_LEN has to be increased to 0x1000 for SPL.
- CONFIG_DEBUG_UART has to be included due to the weird issue.
See TODO comments in arch/x86/cpu/x86_64/cpu.c:arch_setup_gd().
Once this issue gets fixed, debug uart can be optional.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Set up the 64-bit U-Boot text base if building for that target.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a new board config which uses 64-bit U-Boot. This is not fully
functional but is it a start. Missing features:
- SDRAM sizing
- Booting linux
- EFI support
- SCSI device init
(and others)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Set up the 64-bit U-Boot text base if building for that target.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The PPA implements PSCI which requires for power managment.
Added support of PPA for LS1012AQDS, LS1012ARDB and LS1012AFRDM.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
PPA binary needs to be relocated on secure DDR, hence marking out
a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag
is set
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch adds a function to the TPM library, which allows U-Boot to
flush resources, e.g. keys, from the TPM.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Set cpo_sample as suggested by the driver
"WARN: pls set popts->cpo_sample = 0x58 in <board>/ddr.c to optimize
cpo".
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
This patch adds glue code required for enabling the designware
mac on stm32f7 devices.
Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
