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imx6: isiotmx6ul: Add NAND support
Add NAND support for Engicam Is.IoT MX6UL board. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Jagan Teki
Stefano Babic
parent
0421a164de
commit
6788a7e4e9
6 changed files with 186 additions and 2 deletions
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@ -317,7 +317,8 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
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imx6q-icore-rqs.dtb \
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imx6sx-sabreauto.dtb \
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imx6ul-geam-kit.dtb \
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imx6ul-isiot-mmc.dtb
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imx6ul-isiot-mmc.dtb \
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imx6ul-isiot-nand.dtb
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dtb-$(CONFIG_MX7) += imx7-colibri.dtb
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50
arch/arm/dts/imx6ul-isiot-nand.dts
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50
arch/arm/dts/imx6ul-isiot-nand.dts
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@ -0,0 +1,50 @@
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/*
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* Copyright (C) 2016 Amarula Solutions B.V.
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* Copyright (C) 2016 Engicam S.r.l.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "imx6ul-isiot.dtsi"
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/ {
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model = "Engicam Is.IoT MX6UL NAND Starterkit";
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compatible = "engicam,imx6ul-isiot", "fsl,imx6ul";
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};
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@ -4,5 +4,7 @@ S: Maintained
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F: board/engicam/isiotmx6ul
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F: include/configs/imx6ul_isiot.h
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F: configs/imx6ul_isiot_mmc_defconfig
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F: configs/imx6ul_isiot_nand_defconfig
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F: arch/arm/dts/imx6ul-isiot.dtsi
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F: arch/arm/dts/imx6ul-isiot-mmc.dts
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F: arch/arm/dts/imx6ul-isiot-nand.dts
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@ -37,11 +37,80 @@ int board_early_init_f(void)
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return 0;
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}
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#ifdef CONFIG_NAND_MXS
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#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
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#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
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PAD_CTL_SRE_FAST)
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#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
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static iomux_v3_cfg_t const nand_pads[] = {
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MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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};
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static void setup_gpmi_nand(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* config gpmi nand iomux */
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imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
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clrbits_le32(&mxc_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
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/*
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* config gpmi and bch clock to 100 MHz
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* bch/gpmi select PLL2 PFD2 400M
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* 100M = 400M / 4
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*/
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clrbits_le32(&mxc_ccm->cscmr1,
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MXC_CCM_CSCMR1_BCH_CLK_SEL |
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MXC_CCM_CSCMR1_GPMI_CLK_SEL);
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clrsetbits_le32(&mxc_ccm->cscdr1,
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MXC_CCM_CSCDR1_BCH_PODF_MASK |
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MXC_CCM_CSCDR1_GPMI_PODF_MASK,
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(3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
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(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
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/* enable gpmi and bch clock gating */
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setbits_le32(&mxc_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
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/* enable apbh clock gating */
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setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
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}
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#endif /* CONFIG_NAND_MXS */
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_NAND_MXS
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setup_gpmi_nand();
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#endif
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return 0;
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}
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39
configs/imx6ul_isiot_nand_defconfig
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39
configs/imx6ul_isiot_nand_defconfig
Normal file
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@ -0,0 +1,39 @@
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CONFIG_ARM=y
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CONFIG_ARCH_MX6=y
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CONFIG_SPL_GPIO_SUPPORT=y
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_TARGET_MX6UL_ISIOT=y
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CONFIG_SPL_SERIAL_SUPPORT=y
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CONFIG_SPL_WATCHDOG_SUPPORT=y
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CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-nand"
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
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CONFIG_BOOTDELAY=3
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CONFIG_DEFAULT_FDT_FILE="imx6ul-isiot-nand.dtb"
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CONFIG_SPL=y
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CONFIG_SPL_DMA_SUPPORT=y
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CONFIG_HUSH_PARSER=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_FIT_SIGNATURE=y
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CONFIG_SYS_PROMPT="isiotmx6ul> "
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# CONFIG_CMD_IMLS is not set
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CONFIG_CMD_MEMTEST=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_NAND=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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# CONFIG_BLK is not set
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# CONFIG_DM_MMC_OPS is not set
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CONFIG_NAND_MXS=y
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CONFIG_FEC_MXC=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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CONFIG_MXC_UART=y
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CONFIG_IMX_THERMAL=y
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@ -27,6 +27,10 @@
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/* Environment in MMC */
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# if defined(CONFIG_ENV_IS_IN_MMC)
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# define CONFIG_ENV_OFFSET 0x100000
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/* Environment in NAND */
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# elif defined(CONFIG_ENV_IS_IN_NAND)
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# define CONFIG_ENV_OFFSET 0x400000
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# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
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# endif
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#endif
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@ -128,6 +132,21 @@
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# define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#endif
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/* NAND */
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#ifdef CONFIG_NAND_MXS
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# define CONFIG_SYS_MAX_NAND_DEVICE 1
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# define CONFIG_SYS_NAND_BASE 0x40000000
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# define CONFIG_SYS_NAND_5_ADDR_CYCLE
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# define CONFIG_SYS_NAND_ONFI_DETECTION
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# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
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/* APBH DMA */
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# define CONFIG_APBH_DMA
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# define CONFIG_APBH_DMA_BURST
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# define CONFIG_APBH_DMA_BURST8
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#endif
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/* Ethernet */
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#ifdef CONFIG_FEC_MXC
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# define CONFIG_FEC_MXC_PHYADDR 0
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@ -140,7 +159,11 @@
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/* SPL */
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#ifdef CONFIG_SPL
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# define CONFIG_SPL_MMC_SUPPORT
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# ifdef CONFIG_NAND_MXS
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# define CONFIG_SPL_NAND_SUPPORT
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# else
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# define CONFIG_SPL_MMC_SUPPORT
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# endif
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# include "imx6_spl.h"
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# ifdef CONFIG_SPL_BUILD
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