Commit graph

1858 commits

Author SHA1 Message Date
Alim Akhtar
061091098a DMC: Exynos5: Enable update mode for DREX controller
As per Exynos5800 UM ver 0.00 section 17.13.2.1
CONCONTROL register bit 3 [update_mode], Exynos5800 does not
support the PHY initiated update. And it is recommanded to
set this field to 1'b1 during initialization. This patch sets this bit.
Applying MC-initiated mode makes DDL tracking ON, that helps in
compensate MIF voltage variation.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-11-17 19:03:38 +09:00
Akshay Saraswat
aa14b42d53 Exynos5800: Introduce new proid for Exynos5800
This patch intends to add a new proid for Exynos5800 which is a
variant of Exynos5420. Product id for Exynos5800 is 0x5422.
Both Exynos5420 and Exynos5800 are pin to pin compitable. This
gives us an advantage of reusing Exynos5420 clock, pinmux, memory
and other settings.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-11-17 19:03:38 +09:00
Tom Rini
0d485b9095 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2014-11-13 10:35:13 -05:00
Tom Rini
3ad207a2bf Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-11-13 09:32:45 -05:00
Hans de Goede
76946dfe69 sun6i: ehci: Add sun6i ehci support
Add support for the 2 ehci controllers found on the sun6i (A31) soc.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Marek Vasut <marex@denx.de>
2014-11-13 14:49:02 +01:00
Hans de Goede
9a07eb0ba0 sun6i: Add dram initialization code
Add full support for dram initialization, using a fixed clock and autodetection
of the memory organization (numbers of channels, bus-width, etc.).

This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK,
extended with extra initialization sequences and the autodetect algorithm
from boot0.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-13 14:49:01 +01:00
Hans de Goede
bec72c7994 sun4i: Rename dram files to dram_sun4i.x
In preparation for adding sun6i dram support.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-13 14:49:01 +01:00
Hans de Goede
9d8a533e3f sun6i: Add cpucfg register definitions
Not used atm, for future use (e.g. PSCI).

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-13 14:49:01 +01:00
Hans de Goede
62c87ef2e9 sun6i: Add clock functions needed for SPL / DRAM init
Add clock_init_safe and clockset_pll5 functions, as these are needed for
SPL support resp. DRAM init (which is needed for SPL too).

Also add some extra clock register constant defines.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-13 14:49:01 +01:00
Oliver Schinagl
3b10e6eb68 sun6i: Add new p2wi controller driver
The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
bytes each time, this driver will only see very little use and thus is
limited to single byte transmission only.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-13 14:49:01 +01:00
Thierry Reding
25026fa9f1 ARM: cache-cp15: Use more accurate types
size_t is the canonical type to represent variables that contain a size.
Use it instead of signed integer. Physical addresses can be larger than
32-bit, so use a more appropriate type for them as well. phys_addr_t is
a type that is 32-bit on systems that use 32-bit addresses and 64-bit if
the system is 64-bit or uses a form of physical address extension to use
a larger address space on 32-bit systems. Using these types the same API
can be implemented on a wider range of systems.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-12 07:25:42 +01:00
Tom Rini
c88eaea0a0 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2014-11-11 16:59:44 -05:00
Masahiro Yamada
2d5d1c9e29 ARM: UniPhier: add set_pinsel macro for use in assembly code
The function sg_set_pinsel is useful for switching I/O pins
but it can be only used in C code.  This commit adds a simple
macro that is available in asm code.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-12 00:22:23 +09:00
Masahiro Yamada
048899ba8c usb: UniPhier: add UniPhier on-chip EHCI host driver support
Support EHCI host driver used on Panasonic UniPhier platform.
Since Device Tree is not supported on UniPhier yet, the base address
of USB cores are passed from board files (platdevice.c).

TODO for me:
Move the base address to device trees.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
2014-11-12 00:21:28 +09:00
Masahiro Yamada
113ef59e45 ARM: UniPhier: add MIO register file
This commit adds register defines of MIO (Media I/O) block
of UniPhier platform.  This file is necessary to control
the reset signals of the USB cores.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-12 00:21:28 +09:00
Tom Rini
2db8c2d61a Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-11-10 16:25:28 -05:00
Tom Rini
cfa1bd0774 Merge git://git.denx.de/u-boot-ti 2014-11-07 16:18:35 -05:00
Stefan Roese
a877bec3ec arm: socfpga: Add socfpga_spim_enable() to reset_manager.c
This function will be needed by the upcoming Designware master SPI
driver. As the SPI master controller is held in reset by the current
Preloader implementation. So we need to release the reset for the
driver to communicate with the controller.

This function is called from arch_early_init_r() if the SPI
driver is enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
2014-11-07 16:09:10 +01:00
Stefan Roese
51c580c6c9 arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target
This patch includes the latest DT sources for socfpga from the current
Linux kernel. And enables CONFIG_OF_CONTROL for the new build target
"socfpga_socrates" (the EBV SoCrates board) to make use of this new DT
support.

Until this patch, the only SoCFPGA U-Boot target in mainline is
"socfpga_cyclone5". This build target is not (yet) changed to support
DT. So nothing changes for this target. Even though the long-term
goal should be to move all SoCFPGA targets over to DT.

One of the reasons to enable DT support in SoCFPGA is, that I need to
support multiple different SPI controllers for this platform. This is
the QSPI Cadence controller and the Designware SPI master controller.
Both are implemented in the SoCFPGA. And enabling both controllers is
only possible by using the new driver model (DM). The DM SPI code
only supports DT based probing. So it was easier to move SoCFPGA to
DT than to add the (deprecated) platform-data based probing to the
DM SPI suport.

Note that the image with the dtb embedded is u-boot-dtb.img. This needs
to be used now for those DT enabled boards instead of u-boot.img.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2014-11-07 15:58:31 +01:00
Igor Grinberg
52d848695c am335x: make get_board_rev() function weak
Current get_board_rev() function returns a hard coded value which is
obviously incorrect for the majority of boards.
Allow boards to provide a correct implementation by making this
function weak.
In addition open code the trivial and useless BOARD_REV_ID define and
adjust the comment.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
2014-11-06 11:04:40 -05:00
Tom Rini
11ada9225a Merge branch 'rmobile' of git://www.denx.de/git/u-boot-sh 2014-11-05 13:11:18 -05:00
Khoronzhuk, Ivan
6c0fb41a0a net: keystone_net: add Keystone2 K2L SoC support
The Keystone2 Lamar SoC uses the same keystone net driver.
This patch adds opportunity to use it by K2L SoCs.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-11-05 13:09:42 -05:00
Khoronzhuk, Ivan
87ac27bd5b net: keystone_serdes: add keystone K2L SoC support
Keystone2 Lamar SoC uses the same keystone SerDes driver.
All Keystone2 EVM boards currently use SerDes driver, so move
CONFIG_TI_KEYSTONE_SERDES to common configuration file.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-11-05 13:09:42 -05:00
Khoronzhuk, Ivan
f324f2c00b ARM: keystone2: keysonte_nav: add support for K2L SoC
The Keystone2 Lamar SoC uses the same keystone navigator.
Move queue numbers to common hardware file, as all Keystone2 SoCs
have the same ones.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-11-05 13:09:42 -05:00
Tom Rini
625509ab0e Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-11-05 12:48:09 -05:00
Simon Glass
bf38891af2 dm: sunxi: Add pinmux functions which take a bank parameter
With driver model we will have access to a bank pointer, so we want to
use it rather than converting back to a number, and then back to a
bank pointer. Add functions to provide this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-11-05 13:09:58 +01:00
Ian Campbell
ed41e62f51 sunxi: Use CONFIG_MACH_SUN?I from Kconfig instead of CONFIG_SUN?I
Mostly automatic with:
    sed -i -e 's/CONFIG_\(SUN[45678]I\)/CONFIG_MACH_\1/g' $(git grep -l CONFIG_SUN[45678]I)
followed by removing the relevant #defines from include/configs/sun?i.h by
hand.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-11-05 13:09:58 +01:00
Tom Rini
0798082442 Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging 2014-11-04 10:46:45 -05:00
Nobuhiro Iwamatsu
d8659c6d25 arm: rmobile: lager: Fix change of the CPU frequency
The change of the CPU frequency is waited for until PLL0ST of the PLLECR is
set to 1.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-11-04 08:58:23 +09:00
Ye.Li
8fe280f330 imx: mx6 sabreauto: Add board support for USB EHCI
On mx6 sabreauto board, there are two USB ports:
0: OTG
1: HOST
The EHCI driver is enabled for this board, but the IOMUX and VBUS power
control is not implemented, which cause both USB port failed to work.
This patch fix the problem by adding the board support codes.

Since the power control uses the GPIO pin from port expander MAX7310,
the PCA953X driver is enabled for accessing the MAX7310.

The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting
its daisy chain. Add a new function "imx_iomux_set_gpr_register" to
handle GPR register setting.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-11-03 11:21:49 +01:00
Ye.Li
60b1e39586 imx: mx6sl: Add IOMUX setting for USDHC1-3
Set the USDHC1-3 IOMUX settings which are used for mx6slevk board.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-11-03 11:21:49 +01:00
Ye.Li
0561b8edf0 imx: mx6sl: Add perclk_clk_sel bit define in CCM
The MX6SL has the perclk_clk_sel to select the perclk source. Add
its define in CCM

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-11-03 11:21:48 +01:00
Masahiro Yamada
9ea7f3a6d8 Remove unused files
[1] arch/arm/include/asm/arch-at91/at91_shdwn.h
 The top9000 was the last board to use this header file.
 It was removed by commit d58a9451e7 (ppc/arm: zap EMK boards).

[2] board/matrix_vision/common/*
 Some Matrix Vision boards were dropped by commit e7a565638a
 (powerpc: mpc83xx: remove board support for MERGERBOX and MVBLM7)
 and commit af55e35d33
 (powerpc: mpc5xxx: remove board support for MVBC_P and MVSMR).
 Since then these files have been unused.

[3] include/usb/omap1510_udc.h
  The omap5912osk was the last board to use this header file.
  It was removed by commit 62d636aa2a
  (omap: remove omap5912osk board support).

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-By: Wolfgang Denk <wd@denx.de>
2014-10-31 00:38:15 +01:00
Soeren Moch
4bfa2db8e1 arm: arch-mx6: typo fixes in crm_regs.h
fix typos in video pll related register names and bit defines

Signed-off-by: Soeren Moch <smoch@web.de>
2014-10-30 11:58:18 +01:00
Przemyslaw Marczak
9e306f15c6 exynos4/4x12: gpio: use gpio extra base addresses
This patch adds extra gpio part addresses to exynos4
and exynos4x12_gpio_data arrays, which are required
since the gpio enum lists are linear

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-10-30 19:56:16 +09:00
Przemyslaw Marczak
92f4dbaf1a exynos4/4x12: cpu: add extra gpio base addresses
After remove the offsets in Exynos4/4x12 gpio enums,
an additional gpio base addresses are required.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-10-30 19:56:16 +09:00
Anatolij Gustschin
9c56936eb5 arm: imx6: fix typos in CCM_ANALOG_PLL_VIDEO_DENOM register name
Fix name for Video PLL denominator register.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2014-10-30 10:51:24 +01:00
Yehuda Yitschak
59a9cfdd16 gic: fixed compilation error in GICv2 wait for interrupt macro
a hexadicemal value was missing the "0x" prefix which caused
	assembler error

Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
2014-10-28 07:57:31 +01:00
Tom Rini
0ce4af99c0 Merge branch 'master' of git://git.denx.de/u-boot-imx 2014-10-27 09:08:42 -04:00
Tom Rini
5aa7bece10 Merge branch 'master' of git://git.denx.de/u-boot-ti 2014-10-27 09:05:43 -04:00
Tom Rini
674ca84d11 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2014-10-27 09:05:20 -04:00
Marek Vasut
34584d190d arm: socfpga: Zap spl.h and ad-hoc related syms
Switch to the common spl.h file and zap the arch/spl.h . Since the arch/spl.h
contained various ad-hoc symbols, zap those symbols as well and rework the
board configuration a little so it doesn't depend on them.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Pavel Machek <pavel@denx.de>
2014-10-27 02:26:24 +01:00
Tom Rini
d0796defbe Merge http://git.denx.de/u-boot-sunxi 2014-10-26 14:13:24 -04:00
Tom Rini
1fba907f9a Merge branch 'master' of git://git.denx.de/u-boot-usb 2014-10-26 14:12:18 -04:00
Tom Rini
84a6df09c7 Merge git://git.denx.de/u-boot-dm
Fix a trivial conflict over adding <dm.h>

Conflicts:
	arch/arm/cpu/armv7/omap3/board.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-10-26 14:03:08 -04:00
Jeroen Hofstee
7b8119ddf5 tegra: add proto for pin_mux_mmc
while at it, fix a typo

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-10-25 15:27:37 -04:00
Jeroen Hofstee
49c4bc3a6c arm: vectors: provide protypes from vectors.S
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-10-25 15:27:36 -04:00
Jeroen Hofstee
bf8550287d omap3: board: add missing include and proto
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-10-25 15:27:35 -04:00
Jeroen Hofstee
67c398d2c0 arch-mx: add missing include
mxs_wait_mask_set and friends need a declaration
of struct mxs_register_32.

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-10-25 07:27:37 -04:00
Hans de Goede
9e54f6ee01 sunxi: Add clock_get_pll5p() function
This is a preparation patch for making the pll5 "p" divisor configurable
through Kconfig.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:37:24 +02:00