Commit graph

450 commits

Author SHA1 Message Date
Simon Glass
51e9dad296 x86: Add support for panther (Asus Chromebox)
Support running U-Boot as a coreboot payload. Tested peripherals include:

- Video (HDMI and DisplayPort)
- SATA disk
- Gigabit Ethernet
- SPI flash

USB3 does not work. This may be a problem with the USB3 PCI driver or
something in the USB3 stack and has not been investigated So far this is
disabled. The SD card slot also does not work.

For video, coreboot will need to run the OPROM to set this up.

With this board, bare support (running without coreboot) is not available
as yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-16 19:27:40 -06:00
Simon Glass
892ff8e972 x86: Support machines with >4GB of RAM
Some systems have more than 4GB of RAM. U-Boot can only place things below
4GB so any memory above that should not be used. Ignore any such memory so
that the memory size will not exceed the maximum.

This prevents gd->ram_size exceeding 4GB which causes problems for PCI
devices which use DMA.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-04-16 19:27:40 -06:00
Masahiro Yamada
326a682358 malloc_f: enable SYS_MALLOC_F by default if DM is on
This option has a bool type, not hex.
Fix it and enable it if CONFIG_DM is on because Driver Model always
requires malloc memory.  Devices are scanned twice, before/after
relocation.  CONFIG_SYS_MALLOC_F should be enabled to use malloc
memory before relocation.  As it is board-independent, handle it
globally.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Robert Baldyga <r.baldyga@samsung.com>
2015-03-28 09:03:09 -04:00
Masahiro Yamada
0a9e7ee5bd generic-board: select SYS_GENERIC_BOARD for some architectures
We have done with the generic board conversion for all the boards
of ARC, Blackfin, M68000, MicroBlaze, MIPS, NIOS2, Sandbox, X86.

Let's select SYS_GENERIC_BOARD for those architectures, so we can
tell which architecture has finished the conversion at a glance.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-03-28 09:03:08 -04:00
Masahiro Yamada
0a12e6872e generic-board: move __HAVE_ARCH_GENERIC_BOARD to Kconfig
Move the option to Kconfig renaming it to CONFIG_HAVE_GENERIC_BOARD.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-03-28 09:03:08 -04:00
Bin Meng
e4ad6031a7 x86: quark: Enable on-chip ethernet controllers
Intel Quark SoC integrates two 10/100 ethernet controllers which can
be connected to an external RMII PHY. The MAC IP is from Designware.
Enable this support with the existing U-Boot Designware MAC driver
so that the ethernet port on Intel Galileo board can be used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-03-24 21:22:37 -06:00
Tom Rini
1c854dc5d4 arch/x86/cpu/quark/mrc.c: Switch to U_BOOT_DATE / U_BOOT_TIME
Using __DATE__ and __TIME__ results in an error due to -Werror=date-time
with gcc-4.9 (__DATE__ / __TIME__ might prevent reproducible builds) so
switch these over to U_BOOT_DATE / U_BOOT_TIME

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-03-24 21:22:37 -06:00
Bin Meng
312cc39e27 x86: quark: MRC codes clean up
This patch cleans up the quark MRC codes coding style by:
- Remove BIT0/1../31 defines from mrc_util.h
- Create names for the documented BITs and use them
- For undocumented single BITs, use (1 << n) directly
- For undocumented ORed BITs, use the hex number directly
- Remove redundancy parenthesis all over the codes
- Replace to use lower case hex numbers

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-03-24 21:22:37 -06:00
Rob Herring
7682a99826 remove unnecessary version.h includes
Various files are needlessly rebuilt every time due to the version and
build time changing. As version.h is not actually needed, remove the
include.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Macpaul Lin <macpaul@andestech.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: York Sun <yorksun@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philippe Reynes <tremyfr@yahoo.fr>
Cc: Eric Jarrige <eric.jarrige@armadeus.org>
Cc: "David Müller" <d.mueller@elsoft.ch>
Cc: Phil Edworthy <phil.edworthy@renesas.com>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Torsten Koschorrek <koschorrek@synertronixx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
2015-03-24 10:50:50 -04:00
Simon Glass
b724bd7d63 dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to Kconfig
Move this option to Kconfig and update all boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-12 15:17:28 -07:00
Simon Glass
9a89d50d8e dm: x86: Move driver model CONFIGs to Kconfig
Remove driver model CONFIGs from the board config headers and use Kconfig
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-12 10:35:34 -07:00
Tom Rini
db7a7dee68 Merge branch 'master' of git://git.denx.de/u-boot-x86 2015-02-10 10:42:56 -05:00
Michal Simek
0267ba5d86 common: Move dram_init() declaration to common location
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-02-09 15:08:48 +01:00
Bin Meng
ba877efb80 x86: Use tab instead of space to indent in PCIE_ECAM_BASE
Space is used before 'default' in PCIE_ECAM_BASE in arch/x86/Kconfig
so it looks misaligned. Replace the space with tab to indent.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:46 -07:00
Bin Meng
6df7ffea13 x86: Add SD/MMC support to quark/galileo
Intel Galileo board has a microSD slot which is routed from Quark SoC
SDIO controller. Enable SD/MMC support so that we can use an SD card.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:45 -07:00
Bin Meng
728b393f3b x86: Add SPI support to quark/galileo
The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:45 -07:00
Bin Meng
d8b1d22512 x86: galileo: Add GPIO support
Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31),
which is just the same one found in other x86 chipset. Since we
programmed the GPIO register block base address, we should be
able to enable the GPIO support on Intel Galileo board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:45 -07:00
Bin Meng
b162257d4f x86: quark: Initialize non-standard BARs
Quark SoC has some non-standard BARs (excluding PCI standard BARs)
which need be initialized with suggested values. This includes GPIO,
WDT, RCBA, PCIe ECAM and some ACPI register block base addresses.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:44 -07:00
Bin Meng
20c34115d6 x86: quark: Call MRC in dram_init()
Now that we have added Quark MRC codes, call MRC in dram_init() so
that DRAM can be initialized on a Quark based board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:44 -07:00
Bin Meng
236b711e89 x86: quark: Enable the Memory Reference Code build
Turn on the Memory Reference code build in the quark Makefile.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:43 -07:00
Bin Meng
b829f12afa x86: quark: Add System Memory Controller support
The codes are actually doing the memory initialization stuff.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:43 -07:00
Bin Meng
38ad43e436 x86: quark: Add utility codes needed for MRC
Add various utility codes needed for Quark MRC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:43 -07:00
Bin Meng
0a391b1c79 x86: quark: Add Memory Reference Code (MRC) main routines
Add the main routines for Quark Memory Reference Code (MRC).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:42 -07:00
Bin Meng
ea94532461 x86: quark: Bypass TSC calibration
For some unknown reason, the TSC calibration via PIT does not work on
Quark. Enable bypassing TSC calibration and override TSC_FREQ_IN_MHZ
to 400 per Quark datasheet in the Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:42 -07:00
Bin Meng
f56aeaa4ac x86: Allow overriding TSC_FREQ_IN_MHZ
We should allow the value of TSC_FREQ_IN_MHZ to be overridden by
the one in arch/cpu/<xxx>/Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:42 -07:00
Bin Meng
ef46bea02b x86: Enable the Intel quark/galileo build
Make the Intel quark/galileo support avaiable in Kconfig and Makefile.
With this patch, we can generate u-boot.rom for Intel galileo board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:42 -07:00
Bin Meng
afee3fb8c8 x86: Add basic Intel Galileo board support
New board/intel/galileo board directory with minimum codes, plus
board dts, defconfig and configuration files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:41 -07:00
Bin Meng
828d9af5ec x86: Add basic Intel Quark processor support
Add minimum codes to support Intel Quark SoC. DRAM initialization
is not ready yet so a hardcoded gd->ram_size is assigned.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:41 -07:00
Bin Meng
0fae4d24df x86: quark: Add Cache-As-RAM initialization
Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is
initialized by hardware. eSRAM is the ideal place to be used
for Cache-As-RAM (CAR) before system memory is available.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:41 -07:00
Bin Meng
3c8ae536ec x86: Define macros for pci configuration space access
Move PCI_REG_ADDR and PCI_REG_DATA from arch/x86/lib/pci_type1.c to
arch/x86/include/asm/pci.h, also define PCI_CFG_EN so that these
macros can be used for pci configuration space access.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:40 -07:00
Bin Meng
faa8323299 x86: quark: Add routines to access message bus registers
In the Quark SoC, some chipset commands are accomplished by utilizing
the internal message network within the host bridge (D0:F0). Accesses
to this network are accomplished by populating the message control
register (MCR), Message Control Register eXtension (MCRX) and the
message data register (MDR).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:40 -07:00
Bin Meng
b994efbd2d x86: Add header files for Intel Quark SoC defines
device.h for integrated pci devices' bdf on Quark SoC and quark.h for
various memory-mapped and i/o-mapped base addresses within SoC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:40 -07:00
Simon Glass
3a1a18ff18 x86: Add support for Intel Minnowboard Max
This is a relatively low-cost x86 board in a small form factor. The main
peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
series CPU. So far only the dual core 2GB variant is supported.

This uses the existing FSP support. Binary blobs are required to make this
board work. The microcode update is included as a patch (all 3000 lines of
it).

Change-Id: I0088c47fe87cf08ae635b343d32c332269062156
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06 12:07:39 -07:00
Simon Glass
447f8b018e x86: Allow a UART to be set up before the FSP is ready
Since the FSP is a black box it helps to have some sort of debugging
available to check its inputs. If the debug UART is in use, set it up
after CAR is available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06 12:07:38 -07:00
Simon Glass
8ce24cd991 x86: Allow FSP Kconfig settings for all x86
While queensbay is the first chip with these settings, others will want to
use them too. Make them common.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06 12:07:38 -07:00
Simon Glass
f0809f9a38 x86: Remove unnecessary casts and fix comment typos
Tidy up the FSP support code a little.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06 12:07:37 -07:00
Simon Glass
91785f70b9 x86: mmc: Move common FSP functions into a common file
Since these board functions seem to be the same for all boards which use
FSP, move them into a common file. We can adjust this later if future FSPs
need more flexibility.

This creates a generic PCI MMC device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06 12:07:36 -07:00
Simon Glass
7b02bf3c7d x86: Make CAR and DRAM FSP code common
For now this code seems to be the same for all FSP platforms. Make it
common until we see what differences are required.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-05 22:16:44 -07:00
Simon Glass
82196cf34f x86: Adjust the FSP types slightly
To avoid casts, find_fsp_header() should return a pointer. Add asmlinkage
to two API functions which use that convention. UPD_TERMINATOR is common
so move it into a common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-05 22:16:43 -07:00
Simon Glass
1021af4ded x86: Move common FSP code into a common location
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-05 22:16:43 -07:00
Simon Glass
bc17d8f4ac x86: video: Allow video ROM execution to fall back to the other method
If the BIOS emulator is not available, allow use of native execution if
available, and vice versa. This can be controlled by the caller.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-05 22:16:43 -07:00
Simon Glass
2d934e5703 x86: Rename MMCONF_BASE_ADDRESS and make it common across x86
This setting will be used by more than just ivybridge so make it common.

Also rename it to PCIE_ECAM_BASE which is a more descriptive name.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-05 22:16:43 -07:00
Simon Glass
380ab5cc27 x86: ivybridge: Drop the Kconfig MRC cache information
This is now stored in the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:46 -07:00
Simon Glass
069f5481ba x86: config: Enable hook for saving MRC configuration
Add a hook to ensure that this information is saved.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-24 06:13:45 -07:00
Simon Glass
191c008a21 x86: Implement a cache for Memory Reference Code parameters
The memory reference code takes a very long time to 'train' its SDRAM
interface, around half a second. To avoid this delay on every boot we can
store the parameters from the last training sessions to speed up the next.

Add an implementation of this, storing the training data in CMOS RAM and
SPI flash.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:45 -07:00
Simon Glass
a9aff2f46a x86: dts: Add SPI flash MRC details for chromebook_link
Correct the SPI flash compatible string, add an alias and specify the
position of the MRC cache, used to store SDRAM training settings for the
Memory Reference Code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:45 -07:00
Simon Glass
b18c68d891 x86: Use ipchecksum from net/
The existing IP checksum function is only accessible to the 'coreboot' cpu.
Drop it in favour of the new code in the network subsystem.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:44 -07:00
Bin Meng
fea1c47f54 x86: Fix various code format issues in start16.S
Various minor code format issues are fixed in start16.S:
- U-boot -> U-Boot
- 32bit -> 32-bit
- Use TAB instead of SPACE to indent
- Move the indention location of the GDT comment block

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:55 -07:00
Bin Meng
3b621ccabd x86: Test mtrr support flag before accessing mtrr msr
On some x86 processors (like Intel Quark) the MTRR registers are not
supported. This is reflected by the CPUID (EAX 01H) result EDX[12].
Accessing the MTRR registers on such processors will cause #GP so we
must test the support flag before accessing MTRR MSRs.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:55 -07:00
Bin Meng
4949166906 x86: Save mtrr support flag in global data
CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this
flag in x86_cpu_init_f() and save it in global data.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:55 -07:00
Bin Meng
566d1754d3 x86: Add missing DECLARE_GLOBAL_DATA_PTR for mtrr.c
arch/x86/cpu/mtrr.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:54 -07:00
Sebastien Ronsse
07570e7097 x86: Fix out of bounds irq handlers access
Using coreboot-x86_defconfig, the following error occurred prior to this modification:
CC	arch/x86/lib/interrupts
arch/x86/lib/interrupts.c: In function ‘do_irqinfo’:
arch/x86/lib/interrupts.c:134:24: error: iteration 16u invokes undefined behavior [-Werror=aggressive-loop-optimizations]
   if (irq_handlers[irq].handler != NULL) {
                        ^
arch/x86/lib/interrupts.c:133:2: note: containing loop
  for (irq = 0; irq <= CONFIG_SYS_NUM_IRQS; irq++) {
  ^
cc1: all warnings being treated as errors
scripts/Makefile.build:275: recipe for target 'arch/x86/lib/interrupts.o' failed
make[1]: *** [arch/x86/lib/interrupts.o] Error 1
Makefile:1093: recipe for target 'arch/x86/lib' failed
make: *** [arch/x86/lib] Error 2

Change-Id: I3572a822081b72ab760f1eb99442e1161d3d167e
Signed-off-by: Sebastien Ronsse <sronsse@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 17:24:54 -07:00
Simon Glass
bdc88d4eb3 x86: Support ROMs on other archs
We shouldn't assume that the VGA ROM can always be loaded at c0000. This
is only true on x86 machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-23 17:24:15 -07:00
Bin Meng
cdcc17d73d x86: coreboot: Configure pci memory regions
Configure coreboot pci memory regions so that pci device drivers
could work correctly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:05 -08:00
Bin Meng
ade8127a79 x86: Make chromebook_link the default board for coreboot
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.

Note the symbolic link file chromebook_link.dts is deleted and
link.dts is renamed to chromebook_link.dts.

To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86
define needs to be moved to arch/x86/cpu/ivybridge/Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:04 -08:00
Bin Meng
9d74f03460 x86: coreboot: Move coreboot-specific defines from coreboot.h to Kconfig
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.

Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:03 -08:00
Bin Meng
7698d36a10 x86: Hide ROM chip size when CONFIG_X86_RESET_VECTOR is not selected
When CONFIG_X86_RESET_VECTOR is not selected, specifying the ROM chip
size is meaningless, hence hide it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:03 -08:00
Bin Meng
8cb20ccc34 x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configuration file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:03 -08:00
Bin Meng
3ba6a0f4f6 x86: Allow a hardcoded TSC frequency provided by Kconfig
By default U-Boot automatically calibrates TSC running frequency via
MSR and PIT. The calibration may not work on every x86 processor, so
a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
allow bypassing the calibration and assign a hardcoded TSC frequency
CONFIG_TSC_FREQ_IN_MHZ.

Normally the bypass should be turned on in a simulation environment
like qemu.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:02 -08:00
Bin Meng
5c564b0d2f x86: coreboot: Set up timer base correctly
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.

Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
the value of base_time in the timestamp table is still zero, so
we must exclude this case too (this is currently seen on booting
coreboot in qemu).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:02 -08:00
Bin Meng
b2439aecd3 x86: fsp: Drop get_hob_type() and get_hob_length()
These two are not worth having separate inline functions as they are
really simple, so drop them.

Also changed 'type' parameter of fsp_get_next_hob() from u16 to uint.

Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:02 -08:00
Simon Glass
cb3b2e62ca x86: Add an 'mtrr' command to list and adjust MTRRs
It is useful to be able to see the MTRR setup in U-Boot. Add a command
to list the state of the variable MTRR registers and allow them to be
changed.

Update the documentation to list some of the available commands.

This does not support fixed MTRRs as yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13 07:25:02 -08:00
Simon Glass
c72f74e278 x86: ivybridge: Update microcode early in boot
At present the normal update (which happens much later) does not work. This
seems to have something to do with the 'no eviction' mode in the CAR, or at
least moving the microcode update after that causes it not to work.

For now, do an update early on so that it definitely works. Also refuse to
continue unless the microcode update check (later in boot) is successful.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:02 -08:00
Simon Glass
801d70ce02 x86: Disable CAR before relocation on platforms that need it
For platforms with CAR we should disable it before relocation. Check if
this function is available and call it if so.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
7b00896ade x86: ivybridge: Add a way to turn off the CAR
Cache-as-RAM should be turned off when we relocate since we want to run from
RAM. Add a function to perform this task.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
db55bd7dad x86: Commit the current MTRRs before relocation
Once we stop running from ROM we should set up the MTTRs to speed up
execution. This is only needed for platforms that don't have an FSP.
Also in the Coreboot case, the MTRRs are set up for us.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
aaafcd6c3f x86: ivybridge: Request MTRRs for DRAM regions
We should use MTRRs to speed up execution. Add a list of MTRR requests which
will dealt with when we relocate and run from RAM.

We set RAM as cacheable (with write-back) and registers as non-cacheable.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
9818a00eea x86: ivybridge: Set up an MTRR for the video frame buffer
Set the frame buffer to write-combining. This makes it faster, although for
scrolling write-through is even faster for U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
Simon Glass
aff2523f69 x86: Add support for MTRRs
Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.

Clean up the existing header file to follow style, and remove the unneeded
code.

These can speed up booting so should be supported. Add these to global_data
so they can be requested while booting. We will apply the changes during
relocation (in a later commit).

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
Simon Glass
3a5659f7cf x86: ivybridge: Drop support for ROM caching
This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we
don't really need ROM caching (we read the VGA BIOS from ROM but that is
about it)

Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
Simon Glass
f4a6f0aed0 x86: Tidy up VESA mode numbers
There are some bits which should be ignored when displaying the mode number.
Make sure that they are not included in the mode that is displayed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:59 -08:00
Simon Glass
818f602112 x86: Use cache, don't clear the display in video BIOS
There is no need to run with the cache disabled, and there is no point in
clearing the display frame buffer since U-Boot does it later.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:59 -08:00
Simon Glass
d19ee5c27e x86: ivybridge: Only run the Video BIOS when video is enabled
This takes about about 700ms on link when running natively and 900ms when
running using the emulator. It is a waste of time if video is not enabled,
so don't bother running the video BIOS in that case.

We could add a command to run the video BIOS later when needed, but this is
not considered at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13 07:24:59 -08:00
Simon Glass
6c911c4322 x86: Drop RAMTOP Kconfig
We don't need this in U-Boot since we calculate it based on available memory.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13 07:24:58 -08:00
Simon Glass
bbd43d659c x86: Correct XIP_ROM_SIZE
This should default to the size of the ROM for faster execution before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:58 -08:00
Bin Meng
b21b208184 x86: crownbay: Add pci devices in the dts file
The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton
1/2/3/4). Add the corresponding device nodes in the crownbay.dts per
Open Firmware PCI bus bindings.

Also a comment block is added for the 'stdout-path' property in the
chosen node, mentioning that by default the legacy superio serial
port (io addr 0x3f8) is still used on Crown Bay as the console port.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:57 -08:00
Bin Meng
1eb47efc49 x86: Use ePAPR defined properties for x86-uart
Use ePAPR defined properties for x86-uart: clock-frequency and
current-speed. Assign the value of clock-frequency in device tree
to plat->clock of x86-uart instead of using hardcoded number.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:57 -08:00
Bin Meng
949dbc12db x86: Simplify the fsp hob access functions
Remove the troublesome union hob_pointers so that some annoying casts
are no longer needed in those hob access routines. This also improves
the readability.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
8f9052fd98 pci: Make pci apis usable before relocation
Introduce a gd->hose to save the pci hose in the early phase so that
apis in drivers/pci/pci.c can be used before relocation. Architecture
codes need assign a valid gd->hose in the early phase.

Some variables are declared as static so change them to be either
stack variable or global data member so that they can be used before
relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which
just affects some print format.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
fa5530b85d x86: Support pci bus scan in the early phase
On x86, some peripherals on pci buses need to be accessed in the
early phase (eg: pci uart) with a valid pci memory/io address,
thus scan the pci bus and do the corresponding resource allocation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
4722c035cf x86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.c
arch/x86/cpu/pci.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
120c41695b x86: Clean up the board dts files
This commits cleans up the board dts files.

- Correct the serial port register size to 8
- Remove the misleading status = "disabled" statement in the
  serial.dtsi
- Move the inclusion of skeleton.dtsi from serial.dtsi to board
  dts files
- Let the board dts file define stdout-path in the chosen node
- Remove device nodes in board dts files thar are duplicated to
  skeleton.dtsi

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:40 -08:00
Bin Meng
9ca5a0ca0e x86: Rename coreboot.dsti to serial.dtsi
The name of coreboot.dtsi is misleading, as it actually describes
the legacy serial port device node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:40 -08:00
Bin Meng
57706e4bd6 x86: Remove alex.dts in arch/x86/dts
No board is using alex.dts, so remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:40 -08:00
Bin Meng
255fd5caa5 x86: Clean up the FSP support codes
This is the follow-on patch to clean up the FSP support codes:

- Remove the _t suffix on the structures defines
- Use __packed for structure defines
- Use U-Boot's assert()
- Use standard bool true/false
- Remove read_unaligned64()
- Use memcmp() in the compare_guid()
- Remove the cast in the memset() call
- Replace some magic numbers with macros
- Use panic() when no valid FSP image header is found
- Change some FSP utility routines to use an fsp_ prefix
- Add comment blocks for asm_continuation and fsp_init_done
- Remove some casts in find_fsp_header()
- Change HOB access macros to static inline routines
- Add comments to mention find_fsp_header() may be called in a
  stackless environment
- Add comments to mention init(&params) in fsp_init() cannot
  be removed

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:08 -07:00
Bin Meng
41702bac01 x86: Rename coreboot-serial to x86-serial
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:08 -07:00
Bin Meng
aada6276c6 x86: crownbay: Add SDHCI support
There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:08 -07:00
Bin Meng
adfe3b247a x86: crownbay: Add SPI flash support
The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:07 -07:00
Bin Meng
8c5224c9f5 x86: Use consistent name XXX_ADDR for binary blob flash address
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:07 -07:00
Bin Meng
58f542de30 x86: Add queensbay and crownbay Kconfig files
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Bin Meng
240a79d95c x86: Enable the queensbay cpu directory build
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Bin Meng
b71eec3129 x86: ich6-gpio: Add Intel Tunnel Creek GPIO support
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.

Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Simon Glass
0f61de8d9d x86: Convert microcode format to device-tree-only
To avoid having two microcode formats, adjust the build system to support
obtaining the microcode from the device tree, even in the case where it
must be made available before the device tree can be accessed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-18 17:26:06 -07:00
Bin Meng
b2e02d2865 x86: Add basic support to queensbay platform and crownbay board
Implement minimum required functions for the basic support to
queensbay platform and crownbay board.

Currently the implementation is to call fsp_init() in the car_init().
We may move that call to cpu_init_f() in the future.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Bin Meng
efbeeafe95 x86: Integrate Tunnel Creek processor microcode
Integrate the processor microcode version 1.05 for Tunnel Creek,
CPUID device 20661h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:05 -07:00
Simon Glass
b591ee3913 x86: Correct problems in the microcode loading
There are several problems in the code. The device tree decode is incorrect
in ways that are masked due to a matching bug. Both are fixed. Also
microcode_read_rev() should be inline and called before the microcode is
written.

Note: microcode writing does not work correctly on ivybridge for me. Further
work is needed to resolve this. But this patch tidies up the existing code
so that will be easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:05 -07:00
Simon Glass
cf29e3e303 x86: ivybridge: Update the microcode
There are new microcode revisions available. Update them. Also change
the format so that the first 48 bytes are not omitted from the device tree
data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:05 -07:00
Simon Glass
81f79ef792 x86: Move microcode updates into a separate directory
We might end up with a few of these, so put them in their own directory.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-18 17:26:05 -07:00
Masahiro Yamada
e6126a5872 x86: move arch-specific asmlinkage to <asm/linkage.h>
Commit 65dd74a674 (x86: ivybridge: Implement SDRAM init) introduced
x86-specific asmlinkage into arch/x86/include/asm/config.h.

Commit ed0a2fbf14 (x86: Add a definition of asmlinkage) added the
same macro define again, this time, into include/common.h.
(Please do not add arch-specific stuff to include/common.h any more;
it is already too cluttered.)

The generic asmlinkage is defined in <linux/linkage.h>.  If you want
to override it with an arch-specific one, the best way is to add it
to <asm/linkage.h> like Linux Kernel.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-12-15 07:22:53 -07:00
Bin Meng
ba7b38a529 x86: Add a simple command to show FSP HOB information
FSP builds a series of data structures called the Hand-Off-Blocks
(HOBs) as it progresses through initializing the silicon. These data
structures conform to the HOB format as described in the Platform
Initialization (PI) specification Volume 3 Shared Architectual
Elements specification, which is part of the UEFI specification.

Create a simple command to parse the HOB list to display the HOB
address, type and length in bytes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:06 -07:00