The usage of bss values in drivers before initialisation of bss is forbidden.
In that special case some data in .rel.dyn gets corrupted.
This patch is the same as recently applied for arm926js architecture.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Heiko Schocher <hs@denx.de>
The patch adds suupport for the Freescale's mx35pdk board
(known as well as mx35_3stack).
The board boots from the NOR flash. Following devices
are supported:
- two ethernet devices (FEC and SMC911x on debug board)
- I2C
- PMIC (MC13892) via I2C interface
- UART
- NOR flash (64MB)
- NAND flash (2GB)
- basic access to mc9sdz60 registers via I2C interface
Signed-off-by: Stefano Babic <sbabic@denx.de>
This patch cleans driver code replacing all accesses
to registers with fixed offsets with a corresponding
structure.
Signed-off-by: Stefano Babic <sbabic@denx.de>
The MXC SPI driver didn't calculate the SPI clock up to
now and just used highest possible divider 512 for DATA
RATE in the control register. This results in very low
transfer rates.
The patch adds code to calculate and setup the SPI clock
frequency for transfers.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Stefano Babic <sbabic@denx.de>
We need to shift only one time in each cycle in the swapping loop
for unaligned tx case. Currently two byte shift operations are
performed in each loop cycle causing zero gaps in the transmited
data, so not all data scheduled for transmition is actually
transmited.
The proper swapping in unaligned rx case is missing, so add it
as we need to put the received data into the rx buffer in the
correct byte order.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
The patch adds helper funtions for basic access to the registers
of the MC9sdz60 chip (multifunctional device with RTC and CAN) via
I2C interface.
Signed-off-by: Stefano Babic <sbabic@denx.de>
There is sporadic failures when more as one I2C slave
is on the bus and the processor tries to communicate
with more as one slave.
The problem was seen on a mx35pdk (two I2C slaves,
PMIC controller and CAN/RTC chip).
The current driver uses the IIF bit in the status register
to check if the bus is busy or not. According to the manual,
this is not correct, because the IIB bit should be checked.
Not only, to check if a transfer is finished must be checked
the ICF bit, and this is not tested at all.
This patch comes from analyse with a corresponding driver
provided by Freescale as part of the LTIB tool. Comparing
the two drivers, it appears that the current u-boot driver checks
the wrong bits, and depending on race condition, the transfer
can be successful or not.
The patch gets rid also of own debug function (DPRINTF),
replaced with the general debug().
Tested on Freescale mx35pdk.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
This driver accesses to processor's register
via __REG macros, that are removed (or are planned
to be removed) and replaced by C structures.
This patches replaces all occurrencies of __REG macros.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
The patch adds basic support for the Freescale's i.MX35
(arm1136 based) processor.
The patch adds also a prototype for the initialization
of the FEC(ethernet controller) to netdev.h to avoid
warnings.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Supported:
MMC
IDE
PMIC
SPI flash
LEDs
I can boot the kernel supplied by freescale/genesi with this from MMC card
and/or PATA disk.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
This patch add the MX53 boot image support.
This patch has been tested on Freescale MX53EVK board
and MX51EVK board.
Signed-off-by: Jason Liu <r64343@freescale.com>
Add initial support for Freescale MX53 processor,
- Add the iomux support and the pin definition,
- Add the regs definition, clean up some unused def from mx51,
- Add the low level init support, make use the freq input of setup_pll macro
Signed-off-by: Jason Liu <r64343@freescale.com>
The early bootup information is not print out due to
the UART pin iomux not set up correctly before board_init
Add the board_early_init_f function and enable the
CONFIG_BOARD_EARLY_INIT_F. Move the UART pin setting
from board_init to board_early_init_f function.
This patch also move the FEC pin iomux setup to the
board_early_init_f.
Signed-off-by: Jason Liu <r64343@freescale.com>
Make at91 header includes in soft_i2c depend only on CONFIG_AT91FAMILY
rather than individual SoCs.
Signed-off-by: Ryan Mallon <ryan@bluewatersys.com>
Acked-by: Reinhard Meyer<u-boot@emk-elektronik.de>
Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash
memory, real time clock and additional serial EEPROM on i2c bus (enabled).
USB controller is available, but not presently enabled.
Additional board information is available at:
http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx
Environment is configured to precede the actual u-boot image so that it's
located at the beginning of flash erase block (made necessary by the recent
changes to the embedded environment handling). This is achieved by means of
custom ld script.
Signed-off-by: Alex Dubov <oakad@yahoo.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix the bits for ngpixis to reset to alternative bank. Originally the mask
was 0xE0, which left it possible to reset to bank 3 if DIP switch is set to
boot from bank 1. Changing to 0xF0 gurantees to reset to bank 2.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CONFIG_SPLASH_SCREEN_ALIGN makes uboot support display
offset for splashimage. The framebuffer writing address
should be calculated according to different kinds of
framebuffer pixel format, i.e., bits per pixel value.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Linker needs to use the proper endian/bfd flags even when doing partial linking.
LDFLAGS_u-boot sets linker option which is called it when U-boot is built
(u-boot final).
LDFLAGS sets necessary option by partial linking (use in cmd_link_o_target).
CC: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Faraday's ftpmu010 is a power managemnet unit which support cpu
sleep and frequency scaling. It has been integrated into many SoC.
This patch also move ftpmu010 to a proper place for later enhancement.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
If we built POST on PPC's that didn't enable CONFIG_SYS_POST_FPU we'd
get the following warning with newer toolchains:
powerpc-linux-gnu-ld: Warning: lib_powerpc/fpu/libpostpowerpcfpu.o
uses hard float, libpost.o uses soft float
We actually worked around this sometime ago with the following commit:
commit ce82ff0538
Author: Yuri Tikhonov <yur@emcraft.com>
Date: Sat Dec 20 14:54:21 2008 +0300
FPU POST: fix warnings when building with 2.18 binutils
However, this only took into effect if CONFIG_SYS_POST_FPU was enabled.
We can simply move the GNU_FPOST_ATTR out of the CONFIG_SYS_POST_FPU
ifdef block to address the issue.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Patch 8ef583a0 [miiphy: convert to linux/mii.h] introduced the following
compiler warnings in the uec ethernet driver:
In file included from /local/home/galak/git/u-boot-85xx/include/miiphy.h:37:0,
from uec.c:32:
/local/home/galak/git/u-boot-85xx/include/linux/mii.h:133:0: warning: "LPA_1000FULL" redefined
uec_phy.h:34:0: note: this is the location of the previous definition
/local/home/galak/git/u-boot-85xx/include/linux/mii.h:134:0: warning: "LPA_1000HALF" redefined
uec_phy.h:35:0: note: this is the location of the previous definition
In file included from /local/home/galak/git/u-boot-85xx/include/miiphy.h:37:0,
from uec_phy.c:27:
/local/home/galak/git/u-boot-85xx/include/linux/mii.h:133:0: warning: "LPA_1000FULL" redefined
uec_phy.h:34:0: note: this is the location of the previous definition
/local/home/galak/git/u-boot-85xx/include/linux/mii.h:134:0: warning: "LPA_1000HALF" redefined
uec_phy.h:35:0: note: this is the location of the previous definition
Fix them be removing the duplication in the uec code and utlizing the
linux/mii.h version instead.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
ctrl_regs.c: In function 'set_ddr_sdram_mode_2':
ctrl_regs.c:690:6: warning: unused variable 'i'
'i' is only used by DDR3 code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
.boards.depend was created in the source tree even when calling make
with O=objtree, and distclean O=objtree wouldn't clean it. Create
.boards.depend in objtree instead as to clean it up properly.
Reported-by: Loc Minier <loic.minier@linaro.org>
Signed-off-by: Wolfgang Denk <wd@denx.de>
When building with srctree != objtree, the build creates arch/soc/cpu
specific symlinks in the source tree. This means that the same source
tree can't be used for multiple builds at the same time. Also, these
symlinks in the source tree are only cleaned up if one passes the same
O= to distclean.
When srctree != objtree, mkconfig creates an $objtree/include2 directory
in the objtree to host the asm -> arch/$arch/include/asm symlink so that
"#include <asm>" can be used. But it also creates another identical
symlink in $objtree/include.
Then, mkconfig creates two symlinks:
$objtree/include/asm/arch -> arch/$arch/include/asm/arch-$cpu (or $soc)
$objtree/include/asm/proc -> arch/$arch/include/asm/proc-armv (on arm)
but because $objtree/include/asm points at $srctree already, the two
symlinks are created under $srctree.
To fix this, create a real $objtree/include/asm directory, instead of a
symlink. Update cleanup code accordingly.
Signed-off-by: Loc Minier <loic.minier@linaro.org>
Future SoC (like the P1010) replace the LBC controller with the new IFC
(Integrated Flash Controller) so ensure we properly protect code that is
related to the LBC.
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
u-boot cannot be compiled after disabling CONFIG_PCI.
Place PCI related codes under #ifdef CONFIG_PCI
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Hwconfig is called before relocating. Use the new hwconfig APIs.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Extend board specific parameters to include cpo, write leveling override
Extend write leveling sample to 0xf
Adding rcw overrid for quad-rank RDIMMs
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM.
Also adding polling after enabling DDR controller to ensure completion.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version
(major, minor, errata) to determine if unique mode registers are available.
If true, always use unique mode registers. Dynamic ODT is enabled if needed.
The table is documented in doc/README.fsl-ddr. This function may also need
to be extend for future other platforms if such a feature exists.
Enable address parity and RCW by default for RDIMMs.
Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for
quad-rank RDIMMs.
Use a formula to calculate rodt_on for timing_cfg_5.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch exposes more registers which can be used by the DDR drivers or
interactive debugging. U-boot doesn't use all the registers in DDRC.
When advanced tuning is required, writing to those registers is needed.
Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers
Add options to override rcw, address parity to RDIMMs.
Use array for debug registers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
ECC can be turned on/off by hwconfig without recompiling. So enable it
by default.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file,
ECC can be turned on/off by this switch. If this switch is omitted, it is ON by
default.
Updated hwconfig calls to use local buffer.
Syntax is
hwconfig=fsl_ddr:ecc=on
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
