Commit graph

1698 commits

Author SHA1 Message Date
Tom Rini
797f165f7a Merge git://git.denx.de/u-boot-fsl-qoriq 2017-04-04 09:17:08 -04:00
Stefan Roese
fbaa266230 net: mvpp2: Remove unreferenced in_use_thresh from struct mvpp2_bm_pool
As pointed out by Stefan Chulski, this variable is unused and should be
removed.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:44:37 +02:00
Stefan Roese
fb64072934 net: mvpp2: Configure SMI PHY address needed for PHY polling
On PPv2.2 we enable PHY polling, so we also need to configure the PHY
address in the specific PHY address rgisters.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:44:32 +02:00
Stefan Roese
3e3cbb4967 net: mvpp2: Enable PHY polling mode on PPv2.2
Testing shows, that PHY polling needs to be enabled on Armada 7k/8k.
Otherwise ethernet transfers will not work correctly. PHY polling
is enabled per default after reset, so we do not need to specifically
enable it, but this makes it clearer.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:44:26 +02:00
Stefan Roese
025e5921be net: mvpp2: Add missing PHY_INTERFACE_MODE_RGMII_ID
Add a missing occurrance of PHY_INTERFACE_MODE_RGMII_ID, which should
be handled identical to PHY_INTERFACE_MODE_RGMII.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:44:11 +02:00
Stefan Roese
2fe23044cd net: mvpp2: Add GoP and NetC support for port 0 (SFI)
This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver for the missing port 0. This code is
mostly copied from the Marvell U-Boot version and was written by Stefan
Chulski. Please note that only SFI support have been added, as this
is the only interface that this code has been tested with. XAUI and
RXAUI support might follow at a later stage.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:44:02 +02:00
Stefan Roese
31aa1e3815 net: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII)
This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver. This code is mostly copied from the
Marvell U-Boot version and was written by Stefan Chulski. Please
note that only RGMII and SGMII support have been added, as these are
the only interfaces that this code has been tested with.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:43:42 +02:00
Stefan Roese
9acb7da14e net: mvpp2: Read phy-speed from DT to select between 1GB and 2.5GB SGMII
Read the "phy-speed" DT property to differentiate between 1 and 2.5GB
SGMII operations. Please note that its unclear right now, if this
DT property will be accepted in mainline Linux. If not, we need to
revisit this code and change it to use the accepted property.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:43:20 +02:00
Stefan Roese
66b11ccbb6 net: mvpp2: Restructure probe / init functions
This patch does a bit of restructuring of the probe / init functions,
mainly to allow earlier register access as it is needed for the upcoming
GoP (Group of Ports) and NetC (Net Complex) code.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:42:59 +02:00
Stefan Roese
ff572c6d53 net: mvpp2: Add RX and TX FIFO configuration for PPv2.2
This patch adds the PPv2.2 specific FIFO configuration to the mvpp2
driver. The RX FIFO packet data size is changed to the recommended
FIFO sizes. The TX FIFO configuration is newly added.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:42:39 +02:00
Stefan Roese
c9607c9325 net: mvpp2: Handle eth device naming in multi-CP case correctly
Currently, the naming of the ethernet ports is not handled correctly in
the multi-CP (Communication Processor) case. On Armada 8k, the slave-CP
also instantiates an ethernet controller with the same device ID's.
This patch now takes this into account and adds the required base-id
so that the slave-CP ethernet devices will be named "mvpp2-3 ...".

This patch also updates my Copyright notice to include 2017 as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:42:33 +02:00
Stefan Roese
e7935c4770 net: mvpp2: Enable compilation for Armada 7K/8K platforms
Since Armada 7K/8K is also equipped with a newer version of the MVPP2
ethernet controller, lets enable compilation of this driver for these
platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:42:20 +02:00
Stefan Roese
30edc374ea net: mvpp2.c: Clear all buffer / descriptor areas before usage
This fixes problems noticed with the PPv2.2 A7k/8k port, when not all
elements of the descriptors had been cleared before use.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:42:16 +02:00
Stefan Roese
1fabbd074e net: mvpp2: Move probe function from MISC to ETH DM driver
This patch moves the base_probe function mvpp2_base_probe() from the
MISC driver to the ETH driver. When integrated in the MISC driver,
probe is called too early before the U-Boot ethernet infrastructure
(especially the MDIO / PHY interface) has been initialized. Resulting
in errors in mdio_register().

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:42:11 +02:00
Stefan Roese
0a61e9ad1c net: mvpp2: Add MDIO support for PPv2.2
In U-Boot the MDIO / SMI support is integrated in the mvpp2 driver,
currently only supporting the 32bit platforms (Armada 37x). This patch
now adds the A7k/8k PPv2.2 MDIO support to that the phy / mii IF
can be used as well on these platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:42:05 +02:00
Thomas Petazzoni
a83a6418a2 net: mvpp2: finally add the PPv2.2 compatible string
Now that the mvpp2 driver has been modified to accommodate the support
for PPv2.2, we can finally advertise this support by adding the
appropriate compatible string.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:42:01 +02:00
Thomas Petazzoni
09b3f948dc net: mvpp2: adapt rxq distribution to PPv2.2
In PPv2.1, we have a maximum of 8 RXQs per port, with a default of 4
RXQs per port, and we were assigning RXQs 0->3 to the first port, 4->7
to the second port, 8->11 to the third port, etc.

In PPv2.2, we have a maximum of 32 RXQs per port, and we must allocate
RXQs from the range of 32 RXQs available for each port. So port 0 must
use RXQs in the range 0->31, port 1 in the range 32->63, etc.

This commit adapts the mvpp2 to this difference between PPv2.1 and
PPv2.2:

- The constant definition MVPP2_MAX_RXQ is replaced by a new field
  'max_port_rxqs' in 'struct mvpp2', which stores the maximum number of
  RXQs per port. This field is initialized during ->probe() depending
  on the IP version.

- MVPP2_RXQ_TOTAL_NUM is removed, and instead we calculate the total
  number of RXQs by multiplying the number of ports by the maximum of
  RXQs per port. This was anyway used in only one place.

- In mvpp2_port_probe(), the calculation of port->first_rxq is adjusted
  to cope with the different allocation strategy between PPv2.1 and
  PPv2.2. Due to this change, the 'next_first_rxq' argument of this
  function is no longer needed and is removed.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:41:30 +02:00
Thomas Petazzoni
bc0bbf41b1 net: mvpp2: rework RXQ interrupt group initialization for PPv2.2
This commit adjusts how the MVPP2_ISR_RXQ_GROUP_REG register is
configured, since it changed between PPv2.1 and PPv2.2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:41:25 +02:00
Thomas Petazzoni
cdf77799a3 net: mvpp2: add AXI bridge initialization for PPv2.2
The PPv2.2 unit is connected to an AXI bus on Armada 7K/8K, so this
commit adds the necessary initialization of the AXI bridge.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:41:22 +02:00
Thomas Petazzoni
7c7311f1a2 net: mvpp2: handle misc PPv2.1/PPv2.2 differences
This commit handles a few miscellaneous differences between PPv2.1 and
PPv2.2 in different areas, where code done for PPv2.1 doesn't apply for
PPv2.2 or needs to be adjusted (getting the MAC address, disabling PHY
polling, etc.).

Changed by Stefan for U-Boot:
Since mvpp2_port_power_up() has multiple callers in U-Boot, the U-Boot
version of this patch does not remove this function but simply adds the
check for MVPP21 before the mvpp2_port_fc_adv_enable() call.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:41:17 +02:00
Thomas Petazzoni
26a5278c9e net: mvpp2: handle register mapping and access for PPv2.2
This commit adjusts the mvpp2 driver register mapping and access logic
to support PPv2.2, to handle a number of differences.

Due to how the registers are laid out in memory, the Device Tree binding
for the "reg" property is different:

- On PPv2.1, we had a first area for the common registers, and then one
  area per port.

- On PPv2.2, we have a first area for the common registers, and a
  second area for all the per-ports registers.

In addition, on PPv2.2, the area for the common registers is split into
so-called "address spaces" of 64 KB each. They allow to access the same
registers, but from different CPUs. Hence the introduction of cpu_base[]
in 'struct mvpp2', and the modification of the mvpp2_write() and
mvpp2_read() register accessors. For PPv2.1, the compatibility is
preserved by using an "address space" size of 0.

Changed by Stefan for U-Boot:
Since we don't support multiple CPUs in U-Boot, I've removed all the
code, macros and variables introduced in the Linux patch version for this.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:41:11 +02:00
Thomas Petazzoni
80350f55cf net: mvpp2: adjust mvpp2_{rxq,txq}_init for PPv2.2
In PPv2.2, the MVPP2_RXQ_DESC_ADDR_REG and MVPP2_TXQ_DESC_ADDR_REG
registers have a slightly different layout, because they need to contain
a 64-bit address for the RX and TX descriptor arrays. This commit
adjusts those functions accordingly.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:41:07 +02:00
Thomas Petazzoni
b8c8e6ffac net: mvpp2: adapt mvpp2_defaults_set() to PPv2.2
This commit modifies the mvpp2_defaults_set() function to not do the
loopback and FIFO threshold initialization, which are not needed for
PPv2.2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:41:03 +02:00
Thomas Petazzoni
8f3e4c3800 net: mvpp2: adapt the mvpp2_rxq_*_pool_set functions to PPv2.2
The MVPP2_RXQ_CONFIG_REG register has a slightly different layout
between PPv2.1 and PPv2.2, so this commit adapts the functions modifying
this register to accommodate for both the PPv2.1 and PPv2.2 cases.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:59 +02:00
Thomas Petazzoni
c8feeb2b93 net: mvpp2: adjust the allocation/free of BM pools for PPv2.2
This commit adjusts the allocation and freeing of BM pools to support
PPv2.2. This involves:

- Checking that the number of buffer pointers is a multiple of 16, as
  required by the hardware.

- Adjusting the size of the DMA coherent area allocated for buffer
  pointers. Indeed, PPv2.2 needs space for 2 pointers of 64-bits per
  buffer, as opposed to 2 pointers of 32-bits per buffer in
  PPv2.1. The size in bytes is now stored in a new field of the
  mvpp2_bm_pool structure.

- On PPv2.2, getting the physical and virtual address of each buffer
  requires reading the MVPP2_BM_ADDR_HIGH_ALLOC to get the high order
  bits of those addresses. A new utility function
  mvpp2_bm_bufs_get_addrs() is introduced to handle this.

- On PPv2.2, releasing a buffer requires writing the high order 32 bits
  of the physical address to MVPP2_BM_PHY_VIRT_HIGH_RLS_REG. We no
  longer need to write the virtual address to MVPP2_BM_VIRT_RLS_REG.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:54 +02:00
Thomas Petazzoni
f50a0118d1 net: mvpp2: introduce PPv2.2 HW descriptors and adapt accessors
This commit adds the definition of the PPv2.2 HW descriptors, adjusts
the mvpp2_tx_desc and mvpp2_rx_desc structures accordingly, and adapts
the accessors to work on both PPv2.1 and PPv2.2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:49 +02:00
Thomas Petazzoni
9a6db0bb06 net: mvpp2: introduce an intermediate union for the TX/RX descriptors
Since the format of the HW descriptors is different between PPv2.1 and
PPv2.2, this commit introduces an intermediate union, with for now
only the PPv2.1 descriptors. The bulk of the driver code only
manipulates opaque mvpp2_tx_desc and mvpp2_rx_desc pointers, and the
descriptors can only be accessed and modified through the accessor
functions. A follow-up commit will add the descriptor definitions for
PPv2.2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:44 +02:00
Thomas Petazzoni
16a9898d80 net: mvpp2: add hw_version field in "struct mvpp2"
In preparation to the introduction for the support of PPv2.2 in the
mvpp2 driver, this commit adds a hw_version field to the struct
mvpp2, and uses the .data field of the DT match table to fill it in.

Having the MVPP21 and MVPP22 definitions available will allow to start
adding the necessary conditional code to support PPv2.2.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:39 +02:00
Thomas Petazzoni
cfa414aefd net: mvpp2: add and use accessors for TX/RX descriptors
The PPv2.2 IP has a different TX and RX descriptor layout compared to
PPv2.1. In order to prepare for the introduction of PPv2.2 support in
mvpp2, this commit adds accessors for the different fields of the TX
and RX descriptors, and changes the code to use them.

For now, the mvpp2_port argument passed to the accessors is not used,
but it will be used in follow-up to update the descriptor according to
the version of the IP being used.

Apart from the mechanical changes to use the newly introduced
accessors, a few other changes, needed to use the accessors, are made:

- The mvpp2_txq_inc_put() function now takes a mvpp2_port as first
  argument, as it is needed to use the accessors.

- Similarly, the mvpp2_bm_cookie_build() gains a mvpp2_port first
  argument, for the same reason.

- In mvpp2_rx_error(), instead of accessing the RX descriptor in each
  case of the switch, we introduce a local variable to store the
  packet size.

- Similarly, in mvpp2_buff_hdr_rx(), we introduce a local "cookie"
  variable to store the RX descriptor cookie, rather than accessing
  it from the descriptor each time.

- In mvpp2_tx_frag_process() and mvpp2_tx() instead of accessing the
  packet size from the TX descriptor, we use the actual value
  available in the function, which is used to set the TX descriptor
  packet size a few lines before.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:34 +02:00
Thomas Petazzoni
cd9ee19226 net: mvpp2: store physical address of buffer in rx_desc->buf_cookie
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:30 +02:00
Thomas Petazzoni
15f4df3091 net: mvpp2: remove support for buffer header
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:23 +02:00
Thomas Petazzoni
4dae32e676 net: mvpp2: use "dma" instead of "phys" where appropriate
As indicated by Russell King, the mvpp2 driver currently uses a lot
"phys" or "phys_addr" to store what really is a DMA address. This commit
clarifies this by using "dma" or "dma_addr" where appropriate.

This is especially important as we are going to introduce more changes
where the distinction between physical address and DMA address will be
key.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:18 +02:00
Stefan Roese
a7c28ff184 net: mvpp2: enable building on 64-bit platforms (more U-Boot specific)
Some more U-Boot specific 64bit support changes, mostly changing u32
to unsigned long.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:14 +02:00
Thomas Petazzoni
d1d075a558 net: mvpp2: enable building on 64-bit platforms
The mvpp2 is going to be extended to support the Marvell Armada 7K/8K
platform, which is ARM64. As a preparation to this work, this commit
enables building the mvpp2 driver on ARM64, by:

 - Adjusting the Kconfig dependency

 - Fixing the types used in the driver so that they are 32/64-bits
   compliant. We use dma_addr_t for DMA addresses, and unsigned long
   for virtual addresses.

It is worth mentioning that after this commit, the driver is for now
still only used on 32-bits platforms, and will only work on 32-bits
platforms.

Changed by Stefan for U-Boot:
Removed the Kconfig change as it does not apply to U-Boot this way.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:09 +02:00
Thomas Petazzoni
c0abc761b1 net: mvpp2: simplify MVPP2_PRS_RI_* definitions
Some of the MVPP2_PRS_RI_* definitions use the ~(value) syntax, which
doesn't compile nicely on 64-bit. Moreover, those definitions are in
fact unneeded, since they are always used in combination with a bit
mask that ensures only the appropriate bits are modified.

Therefore, such definitions should just be set to 0x0. In addition, as
suggested by Russell King, we change the _MASK definitions to also use
the BIT() macro so that it is clear they are related to the values
defined afterwards.

For example:

 #define MVPP2_PRS_RI_L2_CAST_MASK              0x600
 #define MVPP2_PRS_RI_L2_UCAST                  ~(BIT(9) | BIT(10))
 #define MVPP2_PRS_RI_L2_MCAST                  BIT(9)
 #define MVPP2_PRS_RI_L2_BCAST                  BIT(10)

becomes

 #define MVPP2_PRS_RI_L2_CAST_MASK              (BIT(9) | BIT(10))
 #define MVPP2_PRS_RI_L2_UCAST                  0x0
 #define MVPP2_PRS_RI_L2_MCAST                  BIT(9)
 #define MVPP2_PRS_RI_L2_BCAST                  BIT(10)

Because the values (MVPP2_PRS_RI_L2_UCAST, MVPP2_PRS_RI_L2_MCAST and
MVPP2_PRS_RI_L2_BCAST) are always applied with
MVPP2_PRS_RI_L2_CAST_MASK, and therefore there is no need for
MVPP2_PRS_RI_L2_UCAST to be defined as ~(BIT(9) | BIT(10)).

It fixes the following warnings when building the driver on a 64-bit
platform (which is not possible as of this commit, but will be enabled
in a follow-up commit):

drivers/net/ethernet/marvell/mvpp2.c: In function ‘mvpp2_prs_mac_promisc_set’:
drivers/net/ethernet/marvell/mvpp2.c:524:33: warning: large integer implicitly truncated to unsigned type [-Woverflow]
 #define MVPP2_PRS_RI_L2_UCAST   ~(BIT(9) | BIT(10))
                                  ^
drivers/net/ethernet/marvell/mvpp2.c:1459:33: note: in expansion of macro ‘MVPP2_PRS_RI_L2_UCAST’
     mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:40:02 +02:00
Thomas Petazzoni
6b28f42a51 net: mvpp2: fix indentation of MVPP2_EXT_GLOBAL_CTRL_DEFAULT
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:39:59 +02:00
Thomas Petazzoni
dbeb6de136 net: mvpp2: remove unused register definitions
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:39:55 +02:00
Thomas Petazzoni
f1060f0dd0 net: mvpp2: simplify mvpp2_bm_bufs_add()
The mvpp2_bm_bufs_add() currently creates a fake cookie by calling
mvpp2_bm_cookie_pool_set(), just to be able to call
mvpp2_pool_refill(). But all what mvpp2_pool_refill() does is extract
the pool ID from the cookie, and call mvpp2_bm_pool_put() with this ID.

Instead of doing this convoluted thing, just call mvpp2_bm_pool_put()
directly, since we have the BM pool ID.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:39:49 +02:00
Stefan Roese
f811e04ad7 net: mvpp2: Round up top tx buffer boundaries for dcache ops
check_cache_range() warns that the top boundaries are not properly
aligned when flushing or invalidating the buffers and make these
operations fail.

This gets rid of the warnings:
CACHE: Misaligned operation at range ...

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-29 07:39:44 +02:00
Konstantin Porotchkin
3fbeb52bda mvebu: neta: a37xx: Add fixed link support to neta driver
Add support for fixed link to NETA driver.
This feature requreed for proper support of SFP modules
and onboard connected devices like Ethernet switches

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Terry Zhou <bjzhou@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-29 07:38:09 +02:00
Konstantin Porotchkin
2a4d94dd6c mvebu: neta: Add support for board init function
Add ability to use board-specific initialization flow
to NETA driver (for instance Ethernet switch bring-up)

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-29 07:38:09 +02:00
Prabhakar Kushwaha
1b7dba990f arm: fsl-layerscape: Move QSGMII wriop_init to SoC file
MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.

So move QSGMII wriop_init_dpmac() to SoC file.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:08:25 -07:00
Hannes Schmelzer
db40c1aa1c drivers/net/phy: add fixed-phy / fixed-link support
This patch adds support for having a "fixed-link" to some other MAC
(like some embedded switch-device).

For this purpose we introduce a new phy-driver, called "Fixed PHY".

Fixed PHY works only with CONFIG_DM_ETH enabled, since the fixed-link is
described with a subnode below ethernet interface.

Most ethernet drivers (unfortunately not all are following same scheme
for searching/attaching phys) are calling "phy_connect(...)" for getting
a phy-device.
At this point we link in, we search here for a subnode called "fixed-
link", once found we start phy_device_create(...) with the special phy-
id PHY_FIXED_ID (0xa5a55a5a).

During init the "Fixed PHY" driver has registered with this id and now
gets probed, during probe we get all the details about fixed-link out of
dts, later on the phy reports this values.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-03-26 09:58:26 -05:00
Suji Velupillai
5c624b9e9c net: fix cache misaligned issue in Broadcom SF2 driver
Fixed cache misaligned issue in the net driver. The issue shows-up when
a call to flush_dcache_range is made with unaligned memory. The memory
must be aligned to ARCH_DMA_MINALIGN.

Signed-off-by: Suji Velupillai <suji.velupillai@broadcom.com>
Tested-by: Suji Velupillai <suji.velupillai@broadcom.com>
Reviewed-by: Arun Parameswaran <arun.parameswaran@broadcom.com>
Reviewed-by: JD Zheng <jiandong.zheng@broadcom.com>
Reviewed-by: Shamez Kurji <shamez.kurji@broadcom.com>
Signed-off-by: Steve Rae <steve.rae@raedomain.com>

Cover Letter:
This series resolves issues specific to the Broadcom SF2 driver:
- fix cache misaligned issue
- convert to Kconfig
END
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-26 09:58:15 -05:00
oliver@schinagl.nl
ace1520cb5 net: sunxi-emac: Write HW address via function
Currently the mac address is programmed directly in _sunxi_emac_eth_init
making it a one time inflexible operation. By moving it into a separate
function, we can now use this more flexibly.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-26 09:40:57 -05:00
Konstantin Porotchkin
278d30c802 mvebu: neta: a37xx: Add fixed link support to neta driver
Add support for fixed link to NETA driver.
This feature requreed for proper support of SFP modules
and onboard connected devices like Ethernet switches

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Terry Zhou <bjzhou@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23 08:50:50 +01:00
Konstantin Porotchkin
976feda2d8 mvebu: neta: Add support for board init function
Add ability to use board-specific initialization flow
to NETA driver (for instance Ethernet switch bring-up)

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23 08:50:50 +01:00
Tim Harvey
b4f4b0f54b drivers: net: phy: add MV88E6xx options to Kconfig
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-20 19:09:49 +01:00
Tom Rini
b504ff9f6b Xilinx changes for v2017.05
- Move to DM clk driver
 - Add clk support for zynq_sdhci
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Merge tag 'xilinx-for-v2017.05' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2017.05

- Move to DM clk driver
- Add clk support for zynq_sdhci
2017-03-16 16:44:23 -04:00
York Sun
437858b620 driver: net: fsl-mc: Update calculation of MC RAM
Since the reserved RAM is tracked by gd->arch.resv_ram, calculation
of MC memory blocks can be simplified. The MC RAM is guaranteed to be
aligned by the reservation process.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-14 08:44:03 -07:00
York Sun
36cc0de0b9 armv8: layerscape: Rewrite memory reservation
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved
at the end of DDR. DDR is spit into two or three banks. This patch
reverts commit aabd7ddb and simplifies the calculation of reserved
memory, and moves the code into common SoC file. Secure memory is
carved out first. DDR bank size is reduced. Reserved memory is then
allocated on the top of available memory. U-Boot still has access
to reserved memory as data transferring is needed. Device tree is
fixed with reduced memory size to hide the reserved memory from OS.
The same region is reserved for efi_loader.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14 08:44:03 -07:00
Nathan Rossi
2c2ab8d65f net: zynq_gem: Fix masking of supported phydev features
When the zynq_gem driver initializes the phy it sets the supported
features that the phy can support and advertise. However instead of
masking the supported features such that it limits the available
features it sets the phy to have the exact supported features of the
zynq_gem. This is problematic as it will enable features that a phy does
not have or cannot advertise.

Specifically this appears as an issue when using a phy that is only
capable of 10/100, but the zynq_gem driver will override this and try to
enable and advertise 10/100/1000.

Reported-by: Arno Steffens <star@gmx.li>
Fixes: 80243528ef ("net: gem: Fix gem driver on 1Gbps LAN")
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Tested-by: Arno Steffens <star@gmx.li>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2017-03-07 11:27:33 -06:00
Wenyou Yang
3fd2b3aa19 net: macb: Fix ETH not found when clock not support
For the boards such as smartweb on which the clock driver isn't
supported, the ethernet fail to be found when booting up with
the below log.
---8<---
Net:   No ethernet found.
--->8---

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-03-01 21:28:39 -05:00
Tom Rini
7131d2d06b drivers/net/Kconfig: Correct use of apostrophe
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-02-27 12:14:58 -05:00
Stefan Herbrechtsmeier
781745bd87 zynq: Move zynq to clock framework
Move the zynq to clock framework and remove unused functions as well as
the CONFIG_ZYNQ_PS_CLK_FREQ configuration.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17 10:22:46 +01:00
Stefan Herbrechtsmeier
eff55c55c7 net: zynq: Add clk framework support to zynq ethernet driver
If available use the clock framework to set the tx clock rate of the
zynq ethernet controller.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17 10:22:46 +01:00
Stefan Herbrechtsmeier
a259243e9d net: zynq: Don't overwrite gem_rclk_ctrl with default value
The gem[0-1]_rclk_ctrl registers control the source of the rx clock,
control and data signals and configure via ps7_init function. Don't
overwrite the register with the default value.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17 10:22:46 +01:00
Tom Rini
e1a71f8b33 Merge branch 'master' of git://git.denx.de/u-boot-net 2017-02-09 11:56:35 -05:00
John Haechten
a5fd13ad19 net: phy: MSCC Add Support for VSC8530-VSC8531-VSC8540-VSC8541
Signed-off-by: John Haechten <john.haechten@microsemi.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-08 16:32:58 -06:00
Tom Rini
21342d4aed Merge git://git.denx.de/u-boot-dm 2017-02-08 16:24:44 -05:00
Lokesh Vutla
e9ced147bc drivers: net: cpsw: Fix reading of mac address for am43 SoCs
cpsw driver tries to get macid for am43xx SoCs using the compatible
ti,am4372. But not all variants of am43x uses this complatible like
epos evm uses ti,am438x. So use a generic compatible ti,am43 to get
macid for all am43 based platforms.

Tested-by: Aparna Balasubramanian <aparnab@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-02-08 16:24:25 -05:00
Simon Glass
e160f7d430 dm: core: Replace of_offset with accessor
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-08 06:12:14 -07:00
Alex
af2cbfd6b9 drivers: net: Provide Kconfig menu for PHYLIB
Provide the necessary Kconfig symbols so that PHYLIB support may be
enabled in Kconfig, as opposed to needing to #define these symbols in
C source headers.

BITBANGMII and MV88E6352_SWITCH are left out of the PHYLIB submenu as
they don't seem to explicitly depend on it (i.e. they do not use the
phy_driver class).

Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-07 11:05:03 -06:00
Joe Hershberger
93cc2959cf net: phy: Improve the Marvell 151x constants
Use some constants for the phy configuration instead of so many magic
numbers.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-07 10:54:35 -06:00
Daniel Strnad
5ad9204fa9 net: fec_mxc: Fix corruption of device tree blob
Modifying content of dev->name leads to the device tree corruption
because it points to the node name located there.

Signed-off-by: Daniel Strnad <strnadda@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-07 10:54:34 -06:00
Heiner Kallweit
655217d968 net: designware: Fix for use with current Linux device tree for Meson GX
In Uboot for Meson GX the compatible string in meson-gxbb.dtsi so far is:
compatible = "amlogic,meson6-dwmac", "snps,dwmac";

On Linux in the same dt file it's
compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";

To avoid breaking ethernet with the next DT synch from Linux to U-Boot
(planned as prerequisite for adding Meson GX MMC driver to U-Boot) add
"amlogic,meson-gx-dwmac" to the compatibility list in the designware
driver.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-07 10:54:34 -06:00
Mugunthan V N
6463170064 net: phy: dp83867: Add support for MAC impedance configuration
Add support for programmable MAC impedance configuration and
fix typo in DT impedance parameters names.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-07 10:54:34 -06:00
Phil Edworthy
3b5f52801d net: phy: vitesse: Fix cis8204 RGMII_ID code
Commit 79e86ccb37 "vitesse: remove duplicated
argument to ||" correctly removed a redundant check.

However, I believe that the original code was simply wrong, and should have
been checking against RGMII_ID.

To fix this and avoid similar problems in the future, use the
phy_interface_is_rgmii helper function.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-07 10:54:34 -06:00
Phil Edworthy
24d98cb424 net: phy: Marvell: Use phy_interface_is_rgmii helper function
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-07 10:54:34 -06:00
Phil Edworthy
998640b478 net: phy: Add support for Marvell M88E1512
This device also works with the 88E1518 code, so we just adjust
the UID mask accordingly.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-07 10:54:33 -06:00
Phil Edworthy
83cfbeb0df net: phy: Fix mask so that we can identify Marvell 88E1518
The mask for the 88E1510 meant that the 88E1518 code would never be
used.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-07 10:54:33 -06:00
Phil Edworthy
8abdeadc5c net: phy: ti: Fix dp83867 RGMII_TXID interface path
There is code that is specifically for RGMII_TXID interface, but this
will never get used because the code checks that the RGMII interface
is RGMII_ID to RGMII_RXID; RGMII_TXID is after this.

To fix this and avoid similar problems in the future, use the
phy_interface_is_rgmii helper function.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-07 10:54:33 -06:00
Wenyou Yang
6d2c1d26ee net: macb: Remove redundant #ifdef CONFIG_DM_ETH
Remove the redundant #ifdef CONFIG_DM_ETH/#endif.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-07 10:54:31 -06:00
Wenyou Yang
577aa3b358 net: macb: Add the clock support
Due to introducing the at91 clock driver, add the clock support.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-07 10:54:31 -06:00
Wenyou Yang
ebcb40a5a0 net: Kconfig: Add CONFIG_MACB option
Add CONFIG_MACB option in KConfig to be used to select the Cadence
MACB Ethernet driver.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2017-02-07 10:54:31 -06:00
Tom Rini
c83a824e62 Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	configs/ls1046aqds_defconfig
	configs/ls1046aqds_nand_defconfig
	configs/ls1046aqds_qspi_defconfig
	configs/ls1046aqds_sdcard_ifc_defconfig
	configs/ls1046aqds_sdcard_qspi_defconfig
	configs/ls1046ardb_emmc_defconfig
	configs/ls1046ardb_qspi_defconfig
	configs/ls1046ardb_sdcard_defconfig
2017-02-03 20:33:42 -05:00
Dirk Eibach
c52d428dcc net: phy: Support Marvell 88E1680
Add support for Marvell 88E1680 Integrated Octal
10/100/1000 Mbps Energy Efficient Ethernet Transceiver.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-02-01 09:01:46 +01:00
Bogdan Purcareata
5707dfb02e drivers: net: fsl-mc: Fixup MAC addresses in DPC
Fixup port_mac_address property in MC DPC with values from the u-boot
environment. Since u-boot already reads the environment MAC addresses
when probing the PHYs, use these values.

The u-boot environment MAC addresses take precedence over any eventual
ones defined in the DPC, except for the case where they are randomly
assigned (no u-boot env value declared for port).

The patch assumes the "/board_info/ports/" node is present in the DPC.

Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[York S: Fix several indentations]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-31 09:25:21 -08:00
Michael Kurz
008ed16c82 net: phy: add SMSC LAN8742 phy
This patch adds support for SMSC LAN8742 in phylib

Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-01-28 14:04:47 -05:00
Michael Kurz
b20b70fcc0 net: stm32: add designware mac glue code for stm32
This patch adds glue code required for enabling the designware
mac on stm32f7 devices.

Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-01-28 14:04:47 -05:00
Sjoerd Simons
0125bcf01c net: gmac_rockchip: Add Rockchip GMAC driver
Add a new driver for the GMAC ethernet interface present in Rockchip
RK3288 SOCs. This driver subclasses the generic design-ware driver to
add the glue needed specifically for Rockchip.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-01-11 20:23:50 -07:00
Simon Glass
e72ced2340 net: designware: Export the operation functions
Export all functions so that drivers can use them, or not, as the need
arises.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-01-11 20:23:50 -07:00
Simon Glass
f63f28ee25 net: designware: Split the link init into a separate function
With rockchip we need to make adjustments after the link speed is set but
before enabling received/transmit. In preparation for this, split these
two pieces into separate functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-01-11 20:23:50 -07:00
Simon Glass
0ea38db90c net: designware: Adjust dw_adjust_link() to return an error
This function can fail, so return the error if there is one.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-01-11 20:23:50 -07:00
Sjoerd Simons
b9e08d0e80 net: designware: Export various functions/struct to allow subclassing
To allow other DM drivers to subclass the designware driver various
functions and structures need to be exported. Export these.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-01-11 20:23:50 -07:00
Kamensky Ivan
1e94629757 xilinx_phy: Pass correct pointer to fdtdec_get_int()
This patch fixes incorrect pointer on offset device in device tree blob.
When using with the component "Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII"
it does not understand what type is XAE_PHY_TYPE_1000BASE_X and trying
to change frequency.

Signed-off-by: Kamensky Ivan <kamensky.ivan@mail.ru>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-01-11 07:00:27 +01:00
Siva Durga Prasad Paladugu
a765bdd1cb net: zynq_gem: Use clock driver for ZynqMP
Enable and use the clock driver routine
defined in clock driver toset required
clock appropriately.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-01-10 10:18:12 +01:00
Michal Simek
b908fcad84 net: gem: Use wait_for_bit() instead of private mdio_wait()
Using generic wait_for_bit() implementation instead of
using private wait function.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-01-10 10:18:11 +01:00
York Sun
08a37fd13b powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014
Remove these SoCs from Kconfig because they don't have individual
configuration. Clean up existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:20 -05:00
Ajay Bhargav
c7c47ca246 Update Maintainer and Author's email address
I am not longer using my old email address
"ajay.bhargav@einfochips.com". For U-Boot development email address is
now updated to contact@8051projects.net

Signed-off-by: Ajay Bhargav <contact@8051projects.net>
2016-12-27 11:24:17 -05:00
Michal Simek
6516e3f253 net: xilinx: Use mdio_register_seq() to support multiple instances
axi_emac, emaclite and gem have the same issue with registering
multiple instances with mdio busses. mdio bus name has to be uniq but
drivers are setting up only one name for all.
Use mdio_register_seq() and pass dev->seq number to allow multiple
mdio instances registration.

Reported-by: Phani Kiran Kara <phanikiran.kara@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-20 07:40:04 +01:00
Tom Rini
8ea05705a7 Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Migrate CONFIG_ARCH_USE_MEMSET/MEMCPY with this merge.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-18 17:43:20 -05:00
Jagan Teki
1ed2570f7e dm: net: fec: Add .read_rom_hwaddr
Add .read_rom_hwaddr on dm eth_ops.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-12-16 17:15:27 +01:00
Jagan Teki
567173a610 net: fec_mxc: Driver cleanups
- Remove exctra space
- Add space
- Add tab space
- Fix single line comments quotes
- Fix 'CHECK: Avoid CamelCase'
- Fix 'CHECK: Alignment should match open parenthesis'
- Fix 'WARNING: line over 80 characters'
- Re-arrage header include files

Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-12-16 17:15:27 +01:00
Jagan Teki
60752ca86a net: fec_mxc: Convert into driver model
This patch add driver model support for fec_mxc driver.

Cc: Simon Glass <sjg@chromium.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-16 17:15:27 +01:00
Jagan Teki
f54183e65d net: fec_mxc: Remove unneeded eth_device arg from fec_get_hwaddr
fec_get_hwaddr never used eth_device argument, hence removed.

Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-12-16 17:15:27 +01:00
Patrick Bruenn
98d62e618b arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC
Add CX9020 board based on mx53loco.
Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse
serial_mxc with DTE and prepare for device tree migration of other
functions and imx53 devices.

The CX9020 differs from i.MX53 Quick Start Board by:
- use uart2 instead of uart1
- DVI-D connector instead of VGA
- no audio
- CCAT FPGA connected to emi
- enable rtc

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2016-12-16 12:57:12 +01:00
Priyanka Jain
8e62f1ee03 driver: fsl-mc: qbman: Add QBMAN 4.1 support
LS2080A SoC family has QBMAN ver 4.0 whereas newer
SoCs like LS2088A, LS1088A has QBMAN ver 4.1
QBMAN ver 4.0 and ver 4.1 supports dqrr size as 4 and 8 respectively.

Add support of
	to check QBMAN version based on SoC SVR
	update dqrr_size accordingly
	update code to support larger dqrr_size

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-15 11:57:05 -08:00
Tom Rini
361a879902 Revert "Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze"
This reverts commit 3edc0c2522, reversing
changes made to bb135a0180.
2016-12-09 07:56:54 -05:00
Tom Rini
3edc0c2522 Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze 2016-12-09 07:10:39 -05:00