According to Documentation/devicetree/bindings/spi/spi-gpio.yaml
from Linux, the recommended spio-gpio properties are:
sck-gpios, miso-gpios and mosi-gpios.
gpio-sck, gpio-mosi and gpio-miso are considered deprecated.
Currently, U-Boot only supports the deprecated properties.
Allow the soft_spi driver to support both the new and old properties.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Current code expects that SPI_TX_BYTE is single bit mode
but it is wrong. It indicates byte program mode,
not single bit mode.
If SPI_TX_DUAL, SPI_TX_QUAD and SPI_TX_OCTAL bits are not set,
the default transfer bus width is single bit.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an
updated SPI controller that add the capability to allow the driver to
control chip select explicitly. Driver can control and keep cs low
between the transfers natively. Hence the dummy cs workaround or prepend
mode found in the bcm63xx-hsspi driver are no longer needed and this new
driver is much cleaner.
Port from linux patch:
Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zhang@broadcom.com
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Due to the controller limitation to keep the chip select low during the
bus idle time between the transfer, a dummy cs workaround was used when
this driver was first upstreamed to the u-boot based on linux kernel
driver. It basically picks the dummy cs as !actual_cs so typically dummy
cs is 1 when most of the case only cs 0 is used in the board design.
Then invert the polarity of both cs and tell the controller to start the
transfers using dummy cs. Assuming both cs are active low before the
inversion, effectively this keeps dummy cs high and actual cs low during
the transfer and workaround the issue.
This workaround requires that dummy cs 1 pin to is set to SPI chip
selection function in the pinmux when the transfer clock is above 25MHz.
The old chips likely have default pinmux set to chip select on the dummy
cs pin so it works but this is not case for the new Broadband BCA chips
and this workaround stop working. This is specifically an issue to
support SPI NAND and SPI NOR flash because these flash devices can
typically run at or above 100MHz.
This patch utilizes the prepend feature of the controller to combine the
multiple transfers in the same message to a single transfer when
possible. This way there is no need to keep clock low between transfers
and solve the issue without any pinmux requirement.
Multiple transfers within a SPI message may be combined into one
transfer if the following are all true:
* One or more half duplex write transfer in single bit mode
* Optional full duplex read/write at the end
* No delay and cs_change between transfers
Most of the SPI device meets this requirements such as SPI NOR, SPI NAND
flash, Broadcom SPI voice card and etc. So this change switches to the
prepend mode as the default mode. For any SPI message that does not meet
the above requirement, we switch to original dummy cs mode but limit the
clock rate to the safe 25MHz.
Port from linux patch:
Link: https://lore.kernel.org/r/20230209200246.141520-12-william.zhang@broadcom.com
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
New compatible string brcm,bcmbca-hsspi-v1.0 is introduced based on
dts document brcm,bcm63xx-hsspi.yaml. Add it to the driver to support
this new binding.
Port from linux patch:
Link: https://lore.kernel.org/r/20230207065826.285013-6-william.zhang@broadcom.com
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Currently the driver always sets the controller to dual data bit mode
for both tx and rx data in the profile mode control register even for
single data bit transfer. Luckily the opcode is set correctly according
to SPI transfer data bit width so it does not actually cause issues.
This change fixes the problem by setting tx and rx data bit mode field
correctly according to the actual SPI transfer tx and rx data bit width.
Fixes: 29cc4368ad ("dm: spi: add BCM63xx HSSPI driver")
Port from linux patch:
Link: https://lore.kernel.org/r/20230209200246.141520-11-william.zhang@broadcom.com
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
ARCH_BCMBCA was introduced to cover individual Broadcom broadband SoC
for common features and IP blocks. Use this config instead of each chip
config as the Kconfig dependency for Broadcom HSSPI driver.
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add support for an optional external chip-select gpio.
Signed-off-by: Lukas Funke <lukas.funke@weidmueller.com>
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Remove the platform data header because its content is only used by the
driver.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Rename the flush function into pl022_spi_flush to avoid conflicting
types with previous declaration of the function in stdio.h header.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Align the compatible property with the kernel device tree binding [1]
by removing the '-spi' suffix.
[1] https://www.kernel.org/doc/Documentation/devicetree/bindings/spi/spi-pl022.yaml
Signed-off-by: Lukas Funke <lukas.funke@weidmueller.com>
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.
The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint timer driver to
support ACLINT mtimer device, using a per-driver data field to hold
the mtimer offset to the base address encoded in the mtimer node.
[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of
DDR capacity includes 2G/4G/8G, a DT can not support multiple
capacities, so the capacity size information is recorded to EEPROM, when
DDR initialization required capacity size information is read from
EEPROM.
If there is no information in EEPROM, it is initialized with the default
size defined in DT.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The StarFive ETHQOS hardware has its own clock and reset,so add a
corresponding glue driver to configure them.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have
verified the driver on StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
DM_GPIO depends on GPIO to be enabled but select will cause that DM_GPIO is
selected without GPIO which ends up in compilation error:
undefined reference to `dm_gpio_set_value'
undefined reference to `dm_gpio_get_value'
undefined reference to `dm_gpio_free'
undefined reference to `gpio_request_by_name'
Signed-off-by: Michal Simek <michal.simek@amd.com>
[trini: Fix configs which had relied on these select's]
Signed-off-by: Tom Rini <trini@konsulko.com>
There is a problem that the rates of PLL0 and PLL1 are set incorrectly
because the postdiv1_mask value is incorrectly entered when setting
the pll clk reg. Modify postdiv1's mask value to be put correctly.
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
If we're building non FU540/FU740 SoC drivers, then the sifive-prci.o
is not needed. Only build this when CONFIG_CLK_SIFIVE_PRCI is selected.
Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The regulator core can return different codes which are not considered
a real error for this function.
Return success in such cases.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Simplify the subsystem by renaming `dev_pdata` to just `plat`.
No functional change, just trivial renaming.
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Some devices share a regulator supply, when the first one will request
regulator disable, the second device will have it's supply cut off before
graciously shutting down. Hence there will be timeouts and other failed
operations.
Implement a reference counter mechanism similar with what is done in
Linux, to keep track of enable and disable requests, and only disable the
regulator when the last of the consumers has requested shutdown.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
GPIOD_ACTIVE_LOW is not enough to configure a GPIO as an output, we need
GPIOD_IS_OUT as well.
Fixes: b252d79b09 ("usb: dwc3: Add support to reset usb ULPI phy")
Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Using CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y and CONFIG_OF_LIVE=y triggers
a Data Abort exception from unaligned memory access when the pinctrl
driver iterate node properties, e.g. for UART2 on RK3568.
setting mux of GPIO0-24 to 1
setting mux of GPIO0-24 to 1
"Synchronous Abort" handler, esr 0x96000021
elr: 000000000000e554 lr : 000000000000e54c
x 0: 0000000000000a5c x 1: 0000000000000a5c
x 2: 0000000000000007 x 3: 0000000000000065
x 4: 0000000000000007 x 5: 0000000000022d4e
x 6: 0000000000000a7c x 7: 00000000000227a4
x 8: 0000000000021cf0 x 9: 0000000000000a7c
x10: 0000000000021cf0 x11: 0000000000021cf0
x12: 00000000003fda1c x13: 0000000000000007
x14: 00000000003fd9ec x15: 000000000001c0ff
x16: 0000000007000000 x17: 00000000fdccd028
x18: 00000000003fde20 x19: 0000000000000018
x20: 0000000000020670 x21: 0000000000000000
x22: 00000000003fdb00 x23: 00000000003fef90
x24: 0000000000020688 x25: 0000000000000000
x26: 0000000000000001 x27: 00000000003ffc50
x28: 0000000000000000 x29: 00000000003fda60
Code: b94083e1 97ffd508 93407c01 37f81260 (f9401038)
Resetting CPU ...
Fix this by replacing the loop to access node properties with use of
ofnode_for_each_prop instead of the current ifdef.
Also continue to next prop instead of aborting at first sign of an
unknown property.
This fixes the Data Abort exception and also pinconf of e.g. pull and
drive in SPL, e.g. for UART2 on RK3568.
setting mux of GPIO0-24 to 1
setting mux of GPIO0-24 to 1
setting pull of GPIO0-24 to 5
setting mux of GPIO0-25 to 1
setting mux of GPIO0-25 to 1
setting pull of GPIO0-25 to 5
Fixes: e7ae4cf27a ("pinctrl: rockchip: Add common rockchip pinctrl driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The support for #address-cells=2 has a loophole: if the reg is actually 0,
but the #address-cells is actually 1, like in such case below:
syscon {
#address-cells = <1>;
phy {
reg = <0 0x10>;
};
};
then the second u32 of the 'reg' is the size, not the address.
The code should check for the parent's #address-cells value, and not
assume that if the first u32 is 0, then the #address-cells is 2, and the
reg property is something like
reg = <0 0xff00 0x10>;
Fixed this by looking for the #address-cells value and retrieving the
reg address only if this is ==2.
To avoid breaking anything I also kept the check `if reg==0` as some DT's
may have a wrong #address-cells as parent and even if this commit is
correct, it might break the existing wrong device-trees.
Fixes: d538efb9ad ("phy: rockchip: inno-usb2: Add support #address_cells = 2")
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This patch adds Power controller driver support for Amlogic
A1 family using secure monitor calls. The power domains register
only can access in secure world.
Signed-off-by: Alexey Romanov <avromanov@sberdevices.ru>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230531093156.29240-4-avromanov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Based on Linux kernel commit:
dabad1ff85611 (pinctrl: meson: add pinctrl driver support for Meson-A1 SoC)
Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230505125639.3605-5-ivprusov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Fix the write to the HPRT register which treat W1C fields
as if they were mere RW. This leads to unintended clearing of such fields
This bug was found during the testing on Simics model. Referring to
specification DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG)
Databook (3.30a)"5.3.4.8 Host Port Control and Status Register (HPRT)", the
HPRT.PrtPwr is cleared by this mistake. In the Linux driver (contrary to
U-Boot), HPRT is always read using dwc2_read_hprt0 helper function which
clears W1C bits. So after write back those bits are zeroes.
Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
At first SPI transfers, multiple chip selects can be
enabled simultaneously. This is due to chip select
polarity, which is not properly initialized for all
channels. This patch fixes the issue.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
In lan78xx_read_otp() we want to know if sig is LAN78XX_OTP_INDICATOR_1
or LAN78XX_OTP_INDICATOR_2. In the case of matching the first one we
set offset to itself, and clang warns about this. Rework the logic so
that if sig is the second indicator we adjust the offset as today and if
it does not match the first indicator we return -EINVAL
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Enable NVME and PCI NVMe drivers for SPL builds. Also enable PCI_PNP
for SPL which is required to auto configure the PCIe devices.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Add a generic API to support loading of SPL payload from any supported
filesystem on a given partition of a block device.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Move header to include to allow external code
to get the internal bdev structures to access
block device operations.
as at it, just add the UCLASS_NVMXIP string
so we get the correct output in partitions
listing.
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
To avoid spurious chars, BRR register must only be written when
USART is disabled.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
In case there is still chars from previous bootstage to transmit, wait
for TC (Transmission Complete) bit to be set which ensure that the last
data written in the USART_TDR has been transmitted out of the shift
register.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
The '_' character is discouraged in the node name, this patch adds the
new prefix of regulator subnode, with the '-' character, in STM32MP1 driver
to support the new naming rule in Linux kernel device trees.
It is a preliminary patch before Linux device tree synchronization
for STMicroelectronics boards.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
With MTD support in driver model, the direct call of mtdparts_init
should be avoided and replaced by mtd_probe_devices.
With the modificaton when MTDIDS/MTDPARTS are empty the OF fallback
with partition describe in device tree is correctly performed,
introduced by commit dc339bf784 ("mtd: add support for parsing
partitions defined in OF").
With this patch the dependency with CONFIG_CMD_MTDPARTS is removed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This patch targets the last remaining commands left to sync to their
latest form - mainly the mc_get_version() API.
Besides this, remove any macro which is now of no help.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sync the Data Path IO APIs to their latest form, this means the layout
of each command is created based on structures which clearly describe
the endianness of each field rather than some macros.
The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sync the Data Path Soft Parser APIs to their latest form, this
means the layout of each command is created based on structures which
clearly describe the endianness of each field rather than some macros.
The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sync the Data Path Network Interface APIs to their latest form, this
means the layout of each command is created based on structures which
clearly describe the endianness of each field rather than some macros.
The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sync the Data Resource Container APIs to their latest form, this means
the layout of each command is created based on structures which clearly
describe the endianness of each field rather than some macros.
The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sync the Data Path MAC APIs to their latest form, this means the
layout of each command is created based on structures which clearly
describe the endianness of each field rather than some macros.
The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sync the Data Path Buffer Pool APIs to their latest form, this means the
layout of each command is created based on structures which clearly
describe the endianness of each field rather than some macros.
The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
There are multiple MC APIs which were added years ago but they are not
used at all in the u-boot source code. Remove all these APIs.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The rtl8169 driver uses calls to dm_pci_bus_to_phys,
which are compiled under CONFIG_PCI.
Without CONFIG_PCI, this happens:
drivers/net/rtl8169.o: in function `rtl_recv_common':
drivers/net/rtl8169.c:555: undefined reference to `dm_pci_bus_to_phys'
It is only natural that this driver depends on CONFIG_PCI then.
The device does not work connected in another way anyway, and the driver
does not assume anything else at this moment.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Export the already existing DPNI and DPMAC counters through the newly
added callbacks.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The ldpaa_eth driver already had a DPMAC statistics dump, this patch
extends the list of stats and adds a bit more structure to the code.
For a bit more context, the DPAA2 u-boot software architecture uses a
default network interface object - a DPNI - which, at runtime, will get
connected to the currently used DPMAC object.
Each time the .stop() eth callback is called, the DPMAC is destroyed
thus any previous counters will get lost.
As a preparation for the next patches, we add a software kept set of
DPMAC counters which will get updated before each destroy operation
takes place.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
