Commit graph

113 commits

Author SHA1 Message Date
Simon Glass
77f9b1fb62 x86: ivybridge: Perform Intel microcode update on boot
Microcode updates are stored in the device tree. Work through these and
apply any that are needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
94060ff278 x86: ivybridge: Check BIST value on boot
The built-in self test value should be checked before we continue booting.
Refuse to continue if there is something wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
f5fbbe9579 x86: ivybridge: Perform initial CPU setup
Set up the flex ratio (controls speed versus heat output) and a few other
very early things.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:13 +01:00
Simon Glass
378a8634ad x86: Tidy up coreboot header usage
There is no need to explicitly write 'arch-coreboot' when including headers,
as when the arch directory points to coreboot the correct files will be
used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:13 +01:00
Simon Glass
2b6051541b x86: ivybridge: Add early LPC init so that serial works
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:12 +01:00
Simon Glass
6fb3b72e87 x86: pci: Allow configuration before relocation
Add simple PCI access routines for x86 which permit use before relocation.
The normal PCI stack is still used, but for pre-relocation use there can
only ever be a single hose. After relocation, fall back to the normal
access, although even then on x86 machines there is normally only a single
PCI bus.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:12 +01:00
Simon Glass
6e5b12b614 x86: ivybridge: Enable PCI in early init
Enable PCI so we can access devices that need to be set up before relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:12 +01:00
Simon Glass
7430f10864 x86: Support use of PCI before relocation
Add support for using PCI before SDRAM is available, using early malloc()
and global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:34:12 +01:00
Simon Glass
d188b18f65 x86: Refactor PCI to permit alternate init
We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will allow us
to use early malloc() to store information about a PCI hose.

Common PCI code moves to arch/x86/cpu/pci.c and a new
board_pci_setup_hose() function is provided by boards to set up the (single)
hose used by that board.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:34:11 +01:00
Simon Glass
70a09c6c3d x86: chromebook_link: Implement CAR support (cache as RAM)
Add support for CAR so that we have memory to use prior to DRAM init.
On link there is a total of 128KB of CAR available, although some is
used for the memory reference code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:11 +01:00
Simon Glass
d1cd045982 x86: Emit post codes in startup code for Chromebooks
On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post code that was
emitted. This allows diagnosis of a boot problem since it is possible to
see where the code got to before it died.

On modern hardware these codes are not normally visible. On Chromebooks
they are displayed by the Embedded Controller (EC), so it is useful to emit
them. We must enable this feature for the EC to see the codes, so add an
option for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:34:11 +01:00
Simon Glass
8ef07571a0 x86: Add chromebook_link board
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.

This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:11 +01:00
Masahiro Yamada
a5eb04db1a x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directory
The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile
are redundant because the build system descends into the directory
only when CONFIG_SYS_COREBOOT is defined.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:24:12 +01:00
Simon Glass
727c1a9871 x86: Replace fill_processor_name() with cpu_get_name()
This implementation has a 'cpu' prefix and returns a pointer to the string,
avoiding the need for copying.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:12 +01:00
Simon Glass
6cba6b9209 x86: Fix a warning with gcc 4.4.4
This warning appears even though it seems that the compiler could work it
out. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:24:10 +01:00
Bin Meng
52f952bf5e x86: Do CPU identification in the early phase
The CPU identification happens in x86_cpu_init_f() and corresponding
fields are saved in the global data for later use.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:10 +01:00
Simon Glass
f67cd51e65 x86: Save the BIST value on reset
The built in self test value is available in register eax on start-up. Save
it so that it can be accessed later. Unfortunately we must wait until the
global_data is available before we can do this, so there is a little bit of
shuffling to keep it around.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:10 +01:00
Simon Glass
e1ffd81797 x86: Fix up some missing prototypes
Some functions are missing prototypes. Fix those that are specific to x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:09 +01:00
Simon Glass
8b37c7694f x86: Use the standard arch_cpu_init() function
Instead of an x86-specific cpu_init_f() function, use the normal U-Boot one
for this purpose. Also remove a useless/misleading comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:09 +01:00
Simon Glass
07387d1769 x86: Use the standard dram_init() function
Instead of having an x86-specific DRAM init function, adjust things so we
can use the normal one.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:09 +01:00
Simon Glass
76f90f3020 x86: Tidy up global descriptor table setup
This code is a little muddled, so tidy it up. Make sure that we put the
GDT in the right place and set it up properly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:09 +01:00
Simon Glass
3c00695ee1 x86: Invalidate TLB as early as possible
We should invalidate the TLB right at the start to ensure that we don't get
false address translations even though paging is disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:09 +01:00
Simon Glass
85d87328ea x86: Remove board_init16() call which is not used
This allows a board to do very early init, but no boards need to do this.
We may as well drop this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:08 +01:00
Simon Glass
200182a748 x86: Add support for starting 64-bit kernel
Add code to jump to a 64-bit Linux kernel. We need to set up a flat page
table structure, a new GDT and then go through a few hoops in the right
order.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-28 20:43:47 -06:00
Simon Glass
92cc94a1fe x86: Display basic CPU information on boot
Display the type of CPU (x86 or x86_64) when starting up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-28 20:42:56 -06:00
Simon Glass
7bddac947d x86: Move paging functions into cpu.c
These functions really don't belong in physmem as they relate to the
cpu. Move them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-28 20:42:51 -06:00
Simon Glass
5dbcaa2128 dm: x86: Support pre-reloc malloc()
Add support for this by reserving a block of memory below global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-23 19:45:28 -06:00
Simon Glass
fbd7282426 dm: x86: Zero global data before board_init_f()
To permit information to be passed from the early U-Boot code to
board_init_f() we cannot zero the global_data in board_init_f(). Instead
zero it in the start-up code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-23 19:45:28 -06:00
Bin Meng
35d4fed320 x86: Fix GDT limit in start16.S
GDT limit should be one less than an integral multiple of eight.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-10-22 09:03:07 -06:00
Bin Meng
fb00601ed6 x86: Fix rom version build with CONFIG_X86_RESET_VECTOR
When building U-Boot with CONFIG_X86_RESET_VECTOR, the linking
process misses the resetvec.o and start16.o so it cannot generate
the rom version of U-Boot. The arch/x86/cpu/Makefile is updated to
pull them into the final linking process.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-10-22 09:03:07 -06:00
Masahiro Yamada
90f984e397 kconfig: delete redundant CONFIG_${ARCH} definition
CONFIG_${ARCH} is defined by Kconfig.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2014-07-30 14:42:02 -04:00
Vasili Galka
dbb7234b2a x86: Enable 32-bit build using x86_64 multilib toolchain
Until now building the x86 arch boards required 32-bit toolchain. As
many x86_64 toolchains come with 32-bit support (multilib) that's a
good idea to enable build with such toolchains.

The change required was to specify the usage of 32-bit explicitly to
the compiler and the linker (-m32 and -m elf_i386 flags) and locate
the right libgcc path.

Signed-off-by: Vasili Galka <vvv444@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-06-23 15:37:23 -06:00
Masahiro Yamada
254d68b601 kbuild: move asm-offsets.c from SoC directory to arch/$(ARCH)/lib
U-Boot has supported two kinds of asm-offsets.h.

One is generic for all architectures and its source is located at
./lib/asm-offsets.c.

The other is SoC specific and its source is under SoC directory.
The problem here is that only boards with SoC directory can use
the asm-offsets infrastructure.
Putting asm-offsets.c right under CPU directory does not work.

Now a new demand is coming. PowerPC folks want to use asm-offsets.
But no PowerPC boards have SoC directory.

It seems inconsistent that some boards add asm-offsets.c to SoC
directoreis and some to CPU directories.
It looks more reasonable to put asm-offsets.c under arch/$(ARCH)/lib.

This commit merges asm-offsets.c under SoC directories into
arch/$(ARCH)/lib/asm-offsets.c.

By the way, I doubt the necessity of some entries in asm-offsets.c.
I am leaving refactoring to the board maintainers.
Please check "TODO" in the comment blocks in
arch/{arm,nds32}/lib/asm-offsets.c.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Yuantian Tang <Yuantian.Tang@freescale.com>
2014-03-28 15:06:29 -04:00
Masahiro Yamada
3954b739b3 x86: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
2013-11-01 11:42:12 -04:00
Wolfgang Denk
3765b3e7bd Coding Style cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:53 -04:00
Wolfgang Denk
cb3761ea99 SPDX-License-Identifier: convert BSD-3-Clause files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini Don't remove some copyrights by accident]
Signed-off-by: Tom Rini <trini@ti.com>
2013-08-19 15:45:35 -04:00
Stephen Warren
065202803d config: don't define CONFIG_ARCH_DEVICE_TREE
Now that nothing uses CONFIG_ARCH_DEVICE_TREE, stop defining it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-08-02 18:30:11 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Simon Glass
8f0278eab4 x86: Add coreboot timestamps
Add selected coreboot timestamps into bootstage to get a unified view of
the boot timings.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13 13:33:22 -07:00
Simon Glass
5397d8058c x86: Support adding coreboot timestanps to bootstage
Coreboot provides a lot of useful timing information. Provide a facility
to add this to bootstage on start-up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13 13:33:22 -07:00
Simon Glass
29756d4447 x86: Remove old broken timer implementation
Tidy up some old broken and unneeded implementations. These are not used
by coreboot or anything else now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Michael Spang <spang@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-05-13 13:33:21 -07:00
Simon Glass
e761ecdbb8 x86: Add TSC timer
This timer runs at a rate that can be calculated, well over 100MHz. It is
ideal for accurate timing and does not need interrupt servicing.

Tidy up some old broken and unneeded implementations at the same time.

To provide a consistent view of boot time, we use the same time
base as coreboot. Use the base timestamp supplied by coreboot
as U-Boot's base time.

Signed-off-by: Simon Glass <sjg@chromium.org>base
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13 13:33:21 -07:00
Simon Glass
7949703a95 x86: Rationalise kernel booting logic and bootstage
The 'Starting linux' message appears twice in the code, but both call
through the same place. Unify these and add calls to bootstage to
mark the occasion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Michael Spang <spang@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-05-13 13:33:20 -07:00
Simon Glass
c78a62acdf x86: Implement panic output for coreboot
panic_puts() can be called in early boot to display a message. It might
help with early debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org>
2013-05-13 13:33:20 -07:00
Simon Glass
7282d834cd x86: Declare global_data pointer when it is used
Several files use the global_data pointer without declaring it. This works
because the declaration is currently a NOP. But still it is better to
fix this so that x86 lines up with other archs.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13 13:33:20 -07:00
Simon Glass
20a8b41d50 x86: Remove unused portion of link script
Since we don't have real-mode code now, we can remove this chunk of the link
script.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-05-13 13:31:18 -07:00
Simon Glass
8b42dfc3b6 x86: Fix DRAM bank size init with generic board
The intention of the memory init code is that it should work the same with
CONFIG_SYS_GENERIC_BOARD and without. This is tricky because dram_init()
is called prior to relocation with generic board (matching other archs)
and after relocation without generic board.

Adjust the init sequence so that dram_init() is not called in the generic
board case, which seems like the easiest fix for now. Also ensure that
relocation addresses are still calculated.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-04-15 16:26:09 -07:00
Tom Rini
0ce033d258 Merge branch 'master' of git://git.denx.de/u-boot-arm
Albert's rework of the linker scripts conflicted with Simon's making
everyone use __bss_end.  We also had a minor conflict over
README.scrapyard being added to in mainline and enhanced in
u-boot-arm/master with proper formatting.

Conflicts:
	arch/arm/cpu/ixp/u-boot.lds
	arch/arm/cpu/u-boot.lds
	arch/arm/lib/Makefile
	board/actux1/u-boot.lds
	board/actux2/u-boot.lds
	board/actux3/u-boot.lds
	board/dvlhost/u-boot.lds
	board/freescale/mx31ads/u-boot.lds
	doc/README.scrapyard
	include/configs/tegra-common.h

Build tested for all of ARM and run-time tested on am335x_evm.

Signed-off-by: Tom Rini <trini@ti.com>
2013-03-18 14:37:18 -04:00
Simon Glass
86cfb6bdec x86: Use sections header to obtain link symbols
These are defined in asm-generic/sections.h, so remove them from
architecture-specific files.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:14:00 -04:00
Albert ARIBAUD
ef123c5253 Refactor linker-generated arrays
Refactor linker-generated array code so that symbols
which were previously linker-generated are now compiler-
generated. This causes relocation records of type
R_ARM_ABS32 to become R_ARM_RELATIVE, which makes
code which uses LGA able to run before relocation as
well as after.

Note: this affects more than ARM targets, as linker-
lists span possibly all target architectures, notably
PowerPC.

Conflicts:
	arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
	arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
	arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
	board/ait/cam_enc_4xx/u-boot-spl.lds
	board/davinci/da8xxevm/u-boot-spl-da850evm.lds
	board/davinci/da8xxevm/u-boot-spl-hawk.lds
	board/vpac270/u-boot-spl.lds

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-12 23:28:40 +01:00