Commit graph

259 commits

Author SHA1 Message Date
Philipp Tomsich
cbe18f10e6 rockchip: rk3399: spl: convert to using BOOT_DEVICE_BOOTROM
Instead of directly calling into the back-to-bootrom code, the RK3399
common SPL implementation now uses BOOT_DEVICE_BOOTROM to trigger a
transfer back into the bootrom.

With this factored out, the spl_board_init function can not be
customised for each RK3399 board.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01 00:33:32 +02:00
Kever Yang
f0768491db rockchip: rk3328: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
Kever Yang
c9eb7bca4b rockchip: rk3288: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
Kever Yang
5b67d7010b rockchip: rk3188: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
Kever Yang
b5934cf67c rockchip: rk3399: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01 00:33:31 +02:00
Kever Yang
6e5bd8d6f3 rockchip: ram: rk3399: update reg map for of-platdata
After Simon's patch, the dtoc can work with 64bit address,
so we need to fix reg number for it.
Depend on Simon's patch set:
https://patchwork.ozlabs.org/cover/807266/

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:38 +02:00
Jagan Teki
d55af074e5 rk3288: Add Vyasa initial board support
This patch adds support for Vyasa RK3288 initial board
from Amarula Solutions.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:36 +02:00
Philipp Tomsich
ba1657338b rockchip: rk3399: spl: remove hard-coded addresses for GRF and SGRF
On the RK3399, we will have either OF_PLATDATA or full OF_CONTROL
enabled: this allows the use of syscon to retrieve the addresses of
GRF and SGRF (except for the early debug UART setup, which runs so
early that the device-model is not initialised).

This removes the hard-coded addresses and goes through syscon to
retrieve the base-addresses of GRF and SGRF. After that, we use
the structure definitions to locate the respective registers.

In addition to this, the inclusion of header files is also cleaned up:
- all headers are included at the beginning (there was a spurious
  inclusion of the grf header from within a function)
- all #include statements for unused headers are removed
- the remaining #include statements are sorted (while keeping common.h
  included in front)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18 20:40:36 +02:00
David Wu
4c94aacd62 rockchip: rk322x: Disable integrated macphy for saving power consuming
Unfortunately, the integrated macphy default is enabled, which will
increase power consuming, if we do not use this PHY. So let's disable
it at first, which will save power consuming. If we really use it, then
enable it in driver level.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:33 +02:00
Kever Yang
c964a0dcae rockchip: rk322x: enable fastboot to set boot mode tag
To support fastboot "fastboot reboot-bootloader" cmd.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:32 +02:00
Kever Yang
e1f6881367 rockchip: rk3328: fix syscon id table
syscon id table need a dummy member as NULL ending, or else system
will panic while try to match a compatible in this table as a list.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-08 11:44:51 +02:00
Wadim Egorov
40d4f79b81 rockchip: rk3288: Add reset reason detection
Sometimes it's helpful to know the reset reason caused in the SoC.
Add reset reason detection for the RK3288 SoC.
This will set an environment variable which represents the reset reason.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-05 11:04:35 +02:00
Kever Yang
44c5ba557b rockchip: rk322x: update dram bank size
The DRAM start address is not 0, so need to update the last bank size
as:
DRAM start addr + DRAM_SIZE - last bank start addr

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-18 16:55:25 +02:00
Philipp Tomsich
a299a4879e rockchip: rk3399: spl: remove unused header inclusion
fdtdec.h is included, but not used in rk3399-board-spl.c: remove the
'#include'-statement.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-18 16:55:15 +02:00
Simon Glass
382bee57f1 env: Rename setenv() to env_set()
We are now using an env_ prefix for environment functions. Rename setenv()
for consistency. Also add function comments in common.h.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:22:18 -04:00
Kever Yang
18d38d3a94 rockchip: rk322x: set the DDR region as non-secure in SPL
Disable the ddr secure region setting in SPL and the ddr memory
becomes non-secure, every one can access it. the trust firmware
like OPTEE should have the correct setting for it after SPL if
there is one.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13 17:15:08 +02:00
Philipp Tomsich
e8f9ad94bf rockchip: rk3368: spl: move SPL_LDSCRIPT to Kconfig
With the new way of doing things (i.e. the hierarchical selection of
SPL_LDSCRIPT via Kconfig) in place, this moves the SPL_LDSCRIPT setting
for the RK3368 from defconfig back into Kconfig.

With this done, there should be no lingering cases of SPL_LDSCRIPT
outside of Kconfig files.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:15:08 +02:00
Philipp Tomsich
96b9082c64 rockchip: rk3188: rock: adjust for SPL/TPL split
With the changes to split SPL/TPL for the RK3368, I apparently missed
some needed adjustments to the RK3188 Kconfig and rock_defconfig.

This fixes build-issues for the rock board after applying the RK3368
enablement (and SPL/TPL) set that resulted from TPL_SERIAL_SUPPORT,
TPL_ROCKCHIP_BACK_TO_BROM and TPL_TINY_MEMSET being separate symbols
now.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:37 +02:00
Philipp Tomsich
3159a6fc39 rockchip: rk3368: remove setup of secure timer from TPL/SPL
When using DM timers w/ the timer0 block within the RK3368, we no
longer depend on the ARMv8 generic timer counting.  This allows us to
drop the secure timer initialisation from the TPL and SPL stages.

The secure timer will later be set up by ATF, which starts the ARMv8
generic timer.  Thus, there will be a dependency from Linux to the ATF
through the ARMv8 generic timer... this seems reasonable, as Linux
will require the ATF (and PSCI) to start up the secondary cores anyway
(in other words: we don't add any new dependencies).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:36 +02:00
Philipp Tomsich
5aa49af311 moveconfig: migrate TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE
We can finally drop TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE off the
whitelist (this time it's really happening!) and migrate the setting
(only used on the RK3368-uQ7 so far) into Kconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:35 +02:00
Philipp Tomsich
4cf4378ed0 rockchip: rk3368: mark TPL as not inheriting its stack, text-base and size from SPL
The RK3368 needs to have a different base-address and stack-pointer
for its TPL stage.  Now that we want to do this via Kconfig, we need
to tick the appropriate 'TPL_NEEDS_...' boxes.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:35 +02:00
Philipp Tomsich
d9d1242b82 rockchip: Kconfig: preset TPL_LDSCRIPT via Kconfig for the RK3368
Set TPL_LDSCRIPT in Kconfig, so we don't have to pollute our
header file.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
4d02d20605 rockchip: board: lion-rk3368: add support for the RK3368-uQ7
The RK3368-uQ7 (codenamed 'Lion') is a micro-Qseven (40mm x 70mm,
MXM-230 edge connector compatible with the Qseven specification)
form-factor system-on-module based on the octo-core Rockchip RK3368.
It is designed, supported and manufactured by Theobroma Systems.

It provides the following features:
 - 8x Cortex-A53 (in 2 clusters of 4 cores each)
 - (on-module) up to 4GB of DDR3 memory
 - (on-module) SPI-NOR flash
 - (on-module) eMMC
 - Gigabit Ethernet (with an on-module KSZ9031 PHY)
 - USB
 - HDMI
 - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
 - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
5071457e44 rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368
With SPL and TPL support for the RK3368 in place, mark SPL and TPL as
supported from Kconfig for the RK3368.  As this is primarily tested on
the RK3368-uQ7, we'll leave it to board's individual defconfig to
enable.

Also enable DEBUG_UART_BOARD_INIT for the RK3368, so we get output
during the early boot-up, as we turn on TPL and SPL.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
fbbd38001f rockchip: rk3368: spl: add SPL support
Adds SPL support for the RK3368 (assuming that our TPL stage has
initialised DRAM and set up the memory firewall).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
9b0bc59366 rockchip: spl: make spl-boot-order code reusable (split from rk3399)
In order to reuse the support for the u-boot,spl-boot-order property
from the rk3399, we split it into a reusable module that can be
included by the SPL code for any of our boards.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:34 +02:00
Philipp Tomsich
a55e497156 rockchip: rk3368: spl: add TPL support
This adds the TPL support for the RK3368, including the u-boot-tpl.lds.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:33 +02:00
Philipp Tomsich
403e9cbcd5 rockchip: rk3368: add DRAM controller driver with DRAM initialisation
This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).

At this stage, only the following feature-set is supported:
 - DDR3
 - 32-bit configuration (i.e. fully populated)
 - dual-rank (i.e. no auto-detection of ranks)
 - DDR3-1600K speed-bin

This driver expects to run from a TPL stage that will later return to
the RK3368 BROM.  It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
init code).

Unlike other DMC drivers for RK32xx and RK33xx parts, the required
timings are calculated within the driver based on a target frequency
and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
time).

The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
register for controlling the operation of its (single-channel) DRAM
controller in the GRF block.  This provides for selecting DDR3, mobile
DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure
definition (at offset 0x600).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:33 +02:00
Philipp Tomsich
832567d5aa rockchip: Makefile: streamline SPL/TPL configuration
Handling TPL and SPL in the Makefile for mach-rockchip was based on
nested if checks and/or if-else-if paths.  This can be simplified and
made more readable by using $(SPL_TPL_) and by introducing
intermediate variables for the aggregation of SPL and TPL features.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:33 +02:00
Philipp Tomsich
81bd0ad07c rockchip: rk3368: syscon: SGRF support for OF_PLATDATA
In TPL we will need to configure security in the SGRF of the RK3368.
This change adds support for the SGRF as a syscon device, so we can
retrieve its address range through the syscon API in TPL (and can
avoid having to hard-code the address).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:22 +02:00
Philipp Tomsich
66a63fec81 rockchip: rk3368: syscon: MSCH/PMUGRF/GRF support for OF_PLATDATA
The RK3368 has both a limited TPL size (just 0x7000 bytes) and the
added challenge of booting in AArch64, which increases the code size
for TPL (particularily when using the LP64 programming model).  For
this reason we expect the RK3368 to always use OF_PLATDATA for its
TPL stage.

This change adds support for the MSCH, PMUGRF and GRF register regions
in syscon, which are necessary for initialising the RK3368's DRAM
controller.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:22 +02:00
Philipp Tomsich
9a8f009f24 rockchip: rk3368: improve Kconfig text for the RK3368
The RK3368 option in Kconfig referred to the RK3328 (copy-and-paste)
and had a few typos and unnecessarily used UTF-8 characters.  While
fixing this, I also reformatted and further clarified the text
(e.g. made the grouping into a a big and little cluster of 4 cores
each explicit).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:22 +02:00
Philipp Tomsich
9e27c816a8 rockchip: Makefile: allow selective inclusion of sdram_common.o from TPL/SPL/U-Boot
The utility functions in sdram_common.c will be useful both for some
SPL implementations (and if unused, the linked will discard these
anyway) and for the full U-Boot stage.

This changes selects sdram_common.o through the $(SPL_TPL_) macro to
allow better control of its inclusion through the CONFIG_ROM,
CONFIG_SPL_RAM or CONFIG_TPL_RAM options.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:22 +02:00
Philipp Tomsich
19b68fb280 rockchip: back-to-bootrom: simplify the #ifdef-check for LIBCOMMON in TPL/SPL
With the finer-grained control over LIBCOMMON_SUPPORT for TPL/SPL (i.e.
with the newly introduced distinction between TPL_LIBCOMMON_SUPPORT and
SPL_LIBCOMMON_SUPPORT), we can simplify the #ifdef-check to simply use
CONFIG_IS_ENABELD.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up to use 'puts' and LIBCOMMON:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:19 +02:00
Philipp Tomsich
ee14d29db0 rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL
The back-to-bootrom option is rather unfortunately named
  CONFIG_ROCKCHIP_SPL_BACK_TO_BOOTROM
instead of
  CONFIG_SPL_ROCKCHIP_BACK_TO_BOOTROM

To make is selectable through CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BOOTROM),
we need to rename it.  At the same time, we introduce a TPL_ variant of
the option to give us finer-grained control over when it should be used.

This change is motivated by our RK3368 boot process, which returns to
the boot ROM only from the TPL stage, but not from the SPL stage.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[added fix-up for evb-rk3229_defconfig and phycore-rk3288_defconfig:]
[fixed inverted CONFIG_IS_ENABLED test for rk3288:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

include/configs/rock.h: undef
2017-08-13 17:12:19 +02:00
Philipp Tomsich
36979c7e56 rockchip: back-to-bootrom: add 'back-to-bootrom' support for AArch64
The back-to-bootrom support for Rockchip is equivalent to an
(assembly) implementation of setjmp/longjmp (i.e. it saves the
stack-pointer, link-register and callee-saved registers). Up until
now, this had only been implemented for AArch32 (i.e. ARMv7 or older),
which puts the new ARMv8 devices (which boot in AArch64 mode) at a
slight disadvantage.

To allow use of the 'back-to-bootrom' feature on new devices (e.g. the
RK3368), this commit adds an implementation for AArch64.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-13 17:12:19 +02:00
Andy Yan
77c17f4354 rockchip: use puts instead of printf when back to bootrom
printf will increase the code size more than 1kb, but platform
like rk3036 has no enough space for it.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
d26bfa73ed rockchip: enable SPL_LIBGENERIC for rk3036 based boards
function board_init_f_init_reserve will call memset, which
is implemented in lib, and enabled by CONFIG_SPL_LIBGENERIC_SUPPORT
in spl stage.
To reduce the code size, also enable SPL_TINY_MEMSET.
As rk3036 will return to bootrom immediately after dram
initialization, there is no need to run DM, so disable
SPL_DM_SERIAL.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Philipp Tomsich
c0508e427f rockchip: rk3399: enable SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT via Kconfig
SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT were previously
enabled through rk3399_common.h.  This change implies these options
through Kconfig.

These need to always be active for the RK3399, as follows:
 - SPL_SERIAL_SUPPORT is needed to pass the SPL build
 - SPL_DRIVERS_MISC_SUPPORT is needed to pass the SPL build

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
cb91173a7f rockchip: timer: make register sizes explicit
We are about to reuse the rockchip timer (header file) for 64bit ARMv8
chips, so it seems a good time to make the register sizes explicit by
changing from 'unsigned int' to 'u32'.

Reorders the header-includes in rk_timer.c to ensure that 'u32' is
definded before it is used by 'asm/arch/timer.h'.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:00 +02:00
Wadim Egorov
bafcf2db41 rockchip: Add basic support for phyCORE-RK3288 SoM based carrier board
The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC.
The module can be connected to different carrier boards.
It can be also equipped with different RAM, SPI flash and eMMC variants.
The Rapid Development Kit option is using the following setup:

  - 1 GB DDR3 RAM (2 Banks)
  - 1x 4 KB EEPROM
  - DP83867 Gigabit Ethernet PHY
  - 16 MB SPI Flash
  - 4 GB eMMC Flash

Add basic support for the PCM-947 carrier board, a RK3288 based development
board made by PHYTEC. This board works in a combination with
the phyCORE-RK3288 System on Module.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 15:23:38 +02:00
Kever Yang
64a524b08a rockchip: rk3036: sync os_reg2 define with other soc
Rockchip using the same bit definition for dram info and write
to os_reg, the col and bw info is not correct and let's fix it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:48 +02:00
Kever Yang
b24a8ec15c rockchip: add evb_rk3229 board
evb_rk3229 is a RK3229 based board, with:
- 8GB eMMC;
- 1GB DDR SDRAM;
- 2 USB2.0 HOST port;
- 1 MAC port;
- 1 HDMI port;
- IR;
- WiFi;

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
168eef7ada rockchip: rk322x: add basic soc support
Enable soc support for SPL and U-boot skeleton.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:46 +02:00
Kever Yang
975e4abad2 rockchip: correct the bank0 ram size
The bank0 ram size should be the DRAM size minus reserved size,
the DRAM size may be 1GB, 2GB, 4GB, we can not hard code it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Added DECLARE_GLOBAL_DATA_PTR for RK3328, RK3368 and RK3399:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
cc89369fb0 rockchip: rk3368: add sdram driver for U-Boot
Add sdram driver in U-Boot for get the correct sdram size from
sys_reg, so that U-Boot can co-work with Rockchip loader or SPL
to get different dram capability and then tell the kernel.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Kever Yang
39648e6167 rockchip: rk3328: add sdram driver in U-Boot
Add sdram driver in U-Boot for get the correct sdram size from
sys_reg, so that U-Boot can co-work with Rockchip loader or SPL
to get different dram capability and then tell the kernel.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:44 +02:00
Kever Yang
7805cdf494 rockchip: use common sdram function
Replace the sdram_init() in board init and rockchip_sdram_size() in
sdram driver for all the Rockchip SoCs which enable CONFIG_RAM.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Make dram_init() in rk3036-board.c conditional on CONFIG_RAM:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:44 +02:00
Kever Yang
6d1970fa8a rockchip: add sdram_common for common functions
There are some functions like sdram_size_mb can be re-used for
different rockchip SoCs, just put them into common file.
Add board_get_usable_ram_top() for ram_top init base on
SDRAM_MAX_SIZE.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Added SDRAM_MAX_SIZE definition for RK3036:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

fixup: 3036 fix for sdram_common
2017-07-11 12:13:44 +02:00
Kever Yang
be8da534e2 rockchip: rk3328: correct mem_region
According to rk3328 TRM:
0~0xff000000 is ddr space;
0xff000000~0xffffffff is device space.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:44 +02:00
Philipp Tomsich
8f1034e627 rockchip: dm: convert fdt_get to dev_read
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This covers the DRAM controller initialisation for the RK3188, RK3288
and RK3399... all of these read some of the tuning/setup/timing
parameters from the device-tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:44 +02:00
Simon Glass
fe97471632 rockchip: rk3288: Allow setting up clocks in U-Boot proper
If U-Boot is chain-loaded from a previous boot loader we must set up the
clocks the way U-Boot wants them. Add code for this. It will do nothing if
SPL has already done the job.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09 13:45:34 -06:00
Simon Glass
6f06ef57bb rockchip: rk3288: Add error debugging to veyron_init()
Add a debug() statement so we can see when something goes wrong with the
regulator.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09 13:39:34 -06:00
Andy Yan
2d1951fec6 rockchip: Add basic support for evb-rv1108 board
Add basic support for rv1108 evb, whith this patch we
can boot into u-boot console.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:25 -06:00
Andy Yan
2c1e11dd52 rockchip: Add core Soc start-up code for rv1108
RV1108 is embedded with an ARM Cortex-A7 single core and a DSP core
from Rockchip. It is designed for varies application scenario such
as car DVR, sports DV, secure camera and UAV camera.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:25 -06:00
Philipp Tomsich
fcb2158516 rockchip: arm64: rk3399: support DDR3-1866 (i.e. 933MHz clock)
The RK3399 is capable of driving DDR3 at 933MHz (i.e. DDR3-1866),
if the PCB layout permits and appropriate memory timings are used.

This changes the sanity checks to allow a DTS to request DDR3-1866
operation.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2017-06-07 07:29:23 -06:00
Philipp Tomsich
fbecb94e4b rockchip: arm64: rk3399: revise timeout-handling for DRAM PHY lock
Revise the loop watching for a timeout on obtaining a DRAM PHY lock to
clearly state a timeout in milliseconds and use get_timer (based on
the ARMv8 architected timer) to detect a timeout.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:23 -06:00
Andy Yan
9d7ed33926 rockchip: rk3368: Add PX5 Evaluation board
PX5 EVB is designed by Rockchip for automotive field
with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS
HDMI video input/output interface, audio codec ES8396,
WIFI / BT (on RTL8723BS), Gsensor BMA250E and light&proximity
sensor STK3410.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:20 -06:00
Andreas Färber
54c57ae051 rockchip: rk3368: Add initial support for RK3368 based GeekBox
The GeekBox is a TV box from GeekBuying, based on an MXM3 module.
The module can be used with base boards such as the GeekBox Landingship.
This adds basic support to chain-load U-Boot from Rockchip's miniloader.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:20 -06:00
Andy Yan
e2901ab8f6 rockchip: rk3368: add Sheep board
Sheep board is designed by Rockchip as a EVB for rk3368.
Currently it is able to boot a linux kernel and system
to console with the miniloader run as fist level loader.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2017-06-07 07:29:20 -06:00
Andreas Färber
37a0c60085 rockchip: rk3368: Add core start-up code for RK3368
The RK3368 is an octa-core Cortex-A53 SoC from Rockchip.
This adds basic support to chain-load U-Boot from Rockchip's
miniloader.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:19 -06:00
Kever Yang
c4a921513a rockchip; rk3399: disable SRAM security region
Some host like SD and eMMC may use DMA to transter data to SRAM,
set memory to non-secure to make sure the address can be accessed.

The security of SRAM in OS suppose to initialized in ATF bl31, and
the SPL is before the bl31.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07 06:57:49 -06:00
Simon Glass
da409ccc4a dm: core: Replace of_offset with accessor (part 2)
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:04 -06:00
Simon Glass
a821c4af79 dm: Rename dev_addr..() functions
These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.

In the end we will have:

   1. dev_read_addr...()    - works on devices, supports flat/live tree
   2. devfdt_get_addr...()  - current functions, flat tree only
   3. of_get_address() etc. - new functions, live tree only

All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.

Note this involves changing some dead code - the imx_lpi2c.c file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:01 -06:00
Ley Foon Tan
0680f1b1f7 Convert CONFIG_SPL_BOARD_INIT to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_BOARD_INIT

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
[trini: Update the Kconfig logic]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-22 07:29:48 -04:00
Tom Rini
80403aa636 rk3036: Fix unused variable warning
The variable grf is only referenced if EARLY_DEBUG is defined so move the
declaration to be under the existing guard.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-12 08:37:22 -04:00
Jacob Chen
453c5a927c power: rk808: rename to rk8xx
Since this driver can be used for rk8xx series pmic,
let's rename rk808 to rk8xx, to make it clear.

Configs parts are done by sed -i "s/RK808/RK8XX/g" `grep RK808 -lr ./`

Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
2017-05-10 13:37:22 -06:00
Kever Yang
fa1392a236 rockchip: reserve memory for rk3399 ATF data
There are 3 regions used by rk3399 ATF:
- bl31 code, located at 0x10000;
- cortex-m0 code and data, located at 0xff8c0000;
- bl31 data, located at 0xff8c1000 ~ 0xff8c4000;

SPL_TEXT_BASE starts from 0xff8c2000, we need to reserve memory
for ATF data, or else there will be memory corrupt after SPL
loads the ATF image.

More detail about cortex-M0 code in ATF:
https://github.com/ARM-software/arm-trusted-firmware/commit/
8382e17c4c6bffd15119dfce1ee4372e3c1a7890

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Kever Yang
76e1693b9b rockchip: rk3399: use actual dram size
Since our sdram driver is ready, we can use the actual size
instead of hard code.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Eddie Cai
7474bbe857 rockchip: enable debug uart
enable debug uart for rk3288 and print something to let people know
where we are

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Kever Yang
90c9127e47 rockchip: rk3399: correct memory region
RK3399 device memory region is 0xf8000000~0xffffffff.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Simon Glass
e1bc64eec2 rockchip: Print a message when returning to the bootrom
At present if the return to bootrom fails (e.g. because you are not using
the Rockchip's bootrom's pointer table in MMC) then the board prints
SPL message and hangs. Print a message first if we can, to help in
understanding what happened when it hangs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
2017-04-18 10:29:26 -04:00
Philipp Tomsich
7ee16de58b rockchip: rk3399: spl: add UART0 support for SPL
The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the
serial line available via standardised pins on the edge connector and
available on a RS232 connector).

To support boards (such as the RK3399-Q7) that require UART0 as a
debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate
iomux setup to the rk3399 SPL code.

As we are already touching this code, we also move the board-specific
UART setup (i.e. iomux setup) into board_debug_uart_init(). This will
be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT
is set.

As the RK3399 needs to use its board_debug_uart_init() function, we
have Kconfig enable it by default for RK3399 builds.

With everything set up to define CONFIG_BAUDRATE via defconfig and
with to have the SPL debug UART either on UART0 or UART2, the configs
for the RK3399 EVB are then update (the change for the RK3399-Q7 is
left for later to not cause issues on applying the change).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-15 10:18:29 -06:00
eric.gao@rock-chips.com
bc8e8fe40b rockchip: rk3399: Add missing sentinel in syscon
when enable PMIC rk808,the system will halt at very
 early stage,log is shown as bellow.

INFO:    plat_rockchip_pmu_init(1211): pd status 3e
INFO:    BL31: Initializing runtime services
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x200000
INFO:    SPSR = 0x3c9
time 44561b, 0 (<<----Just stop here)

It's caused by the absence of "{ }" in syscon_rk3399.c
,which will lead to memory overflow like below.According
 to Sysmap file ,we can find the function buck_get_value
of rk808 is just follow the compatible struct,the pointer
"of_match" point to "buck_get_value",but it is not a
struct and don't have member of compatible, In this case,
system crash. So,on the face, it looks like that rk808 is
guilty.but he is really innocent.

while (of_match->compatible) { <<----------
    if (!strcmp(of_match->compatible, compat)) {
    *of_idp = of_match;
    return 0;
    }
    of_match++;
}

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-04-15 10:13:17 -06:00
Klaus Goger
a13110a99f rockchip: ARM64: split RK3399-Q7 board off the RK3399-EVB board
The RK3399-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
Rockchip RK3399.

It provides the following feature set:
 * up to 4GB DDR3
 * on-module SPI-NOR flash
 * on-module eMMC (with 8-bit interace)
 * SD card (on a baseboad) via edge connector
 * Gigabit Ethernet w/ on-module Micrel KSZ9031 GbE PHY
 * HDMI/eDP/MIPI displays
 * 2x MIPI-CSI
 * USB
   - 1x USB 3.0 dual-role (direct connection)
   - 2x USB 3.0 host + 1x USB 2.0 (on-module USB 3.0 hub)
 * on-module STM32 Cortex-M0 companion controller, implementing:
   - low-power RTC functionality (ISL1208 emulation)
   - fan controller (AMC6821 emulation)
   - USB<->CAN bridge controller

Note that we use a multi-payload FIT image for booting and have
Cortex-M0 payload in a separate subimage: we thus rely on the FIT
image loader to put it into the SRAM region that ATF expects it in.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fixed build warning on puma-rk3399:
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-15 10:13:17 -06:00
Heiko Stübner
008a610b4c rockchip: rk3188: enable remap function
Most Rockchip socs have the ability to either map the bootrom or a sram
area to the starting address of the cpu by flipping a bit in the GRF.

Newer socs leave this untouched and mapped to the bootrom but the legacy
loaders on rk3188 and before enabled the remap functionality and the
current smp implementation in the Linux kernel also requires it to be
enabled, to bring up secondary cpus.

So to keep smp working in the kernel, mimic the behaviour of the legacy
bootloaders and enable the remap functionality.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-15 10:13:17 -06:00
Philipp Tomsich
504b9f1a5f rockchip: spl: rk3399: disable DDR security regions for SPL
The RK3399 hangs during DMA of the Designware MMC controller, when
performing DMA-based transactions in SPL due to the DDR security settings
left behind by the BootROM (i.e. accesses to the first MB of DRAM are
restricted... however, the DMA is likely to target this first MB, as it
transfers from/to the stack).

System security is not affected, as the final security configuration is
performed by the ATF, which is executed after the SPL stage.

With this fix in place, we can now drop 'fifo-mode' in the DTS for the
RK3399-Q7 (Puma).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-15 10:13:17 -06:00
Jernej Skrabec
7da8680b26 rockchip: Add support for MiQi rk3288 board
MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
expansion ports.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Jernej Skrabec
43b5c78d8d rockchip: cosmetic: Sort RK3288 boards
Sort rk3288 boards in alphabetical order.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Philipp Tomsich
d02d11f8ae rockchip: rk3399: spl: make SPL boot-order configurable via /chosen
The RK3399 does not have any boot selection pins and the BootROM probes
the boot interfaces using the following boot-order:
    1. SPI
    2. eMMC (sdhci in DTS)
    3. SD card (sdmmc in DTS)
    4. USB loader
For ease of deployment, the SPL stage should mirror the boot order of
the ROM and use the same probing order (assuming that valid images can
be detected by SPL) unless instructed otherwise.  The boot-order can
then be configured via the 'u-boot,spl-boot-order' property in the
chosen-node of the DTS.

While this approach is easily extensible to other boards, it is only
implemented for the RK3399 for now, as the large SRAM on the RK3399
makes this easy to fit the needed infrastructure into SPL and our
production setup already runs with DM, OF_CONTROL and BLK in SPL.

The new boot-order property is expected to be used in conjunction with
FIT images (and all legacy image formats disabled via Kconfig).

A boot-sequence with probing and fallthroughs from SPI via eMMC to SD
card (i.e. &spiflash, &sdhci, &sdmmc) has been validated on the RK3399-Q7.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Heiko Stübner
47197682ef rockchip: rk3188: Add Radxa Rock board
The Rock is a RK3188 based single board computer by Radxa.
Currently it still relies on the proprietary DDR init and
cannot use the generic SPL, but at least is able to boot
a linux kernel and system up to a regular login prompt.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix sort order in defconfig, enable CONFIG_SPL_TINY_MEMSET:
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Philipp Tomsich
f93a51186a rockchip: arm64: rk3399: remove unconditional debug message
An earlier upstream change contained an unconditional debug message
which would show up as a message similar to the following in the
U-Boot startup (after the ATF and before the U-Boot banner):
      time 159f019, 0

This commit removes this message (instead of making if conditional on
being a debug-build), as it doesn't pertain to any initialisation done
in this file.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Heiko Stübner
f4f57c58b5 rockchip: rk3188: Setup the armclk in spl
The armclk starts in slow mode (24MHz) on the rk3188, which results in U-Boot
startup taking a lot of time (U-Boot itself, but also the rc4 decoding done
in the bootrom).

With default pmic settings we can always reach a safe frequency of 600MHz
which is also the frequency the proprietary loader left the armclk at,
without needing access to the systems pmic.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Heiko Stübner
007a43524b rockchip: rk3188: Cleanup some SPL/TPL rename leftovers
In the beginning, we did SPL -> TPL -> U-Boot, but after clarification
of the real ordering swapped SPL and TPL.
It seems some renames were forgotten and may confuse future readers, so
also swap these to reflect the actual ordering.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Heiko Stübner
78959d4cbf rockchip: rk3188: Decode the actual amount of ram
There was still a static ram value set in the rk3188-board from the
time where we didn't have actual sdram init code.
Now the sdram init leaves the ram information in SYS_REG2 and we can
decode it similarly to the rk3288.

Right now we have two duplicates of that code, which is still ok and
doesn't really count as common code yet, but if we get a third copy
at some point from a newer soc, we should think about moving that to
a more general position.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Heiko Stübner
3408509f6f rockchip: rk3188: sdram: Set correct sdram base
Right now we're setting the wrong value of 0 as base in the ram_info struct,
which is obviously wrong for the rk3188. So instead set the correct value
we already have in CONFIG_SYS_SDRAM_BASE.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Heiko Stübner
3c732de9bf rockchip: rk3188: enable TPL_LIBGENERIC for generic memset
Commit c67c8c604b ("board_init.c: Always use memset()") dropped the naive
memset alternative from board_init_f_init_reserve.
So activate CONFIG_TPL_LIBGENERIC for that common memset implementation.
We cannot use the ARCH-specific memset, as that would incur 200bytes of
additional TPL size, space we do not have.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-04-04 20:01:57 -06:00
Kever Yang
232cf96222 rockchip: spl: use spl_early_init() instead of spl_init()
Rockchip spl driver needs using spl_early_init().

Fixes: b3d2861e (spl: Remove overwrite of relocated malloc limit)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Philipp Tomsich
3d54eabcaf rockchip: spl: RK3399: use boot0 hook to create space for SPL magic
The SPL binary needs to be prefixed with the boot magic ('RK33' for
the RK3399) on the Rockchip platform and starts execution of the
instruction word following immediately after this boot magic.

This poses a challenge for AArch64 (ARMv8) binaries, as the .text
section would need to start on the odd address, violating natural
alignment (and potentially triggering a fault for any code that
tries to access 64bit values embedded in the .text section).

A quick and easy fix is to have the .text section include the 'RK33'
magic and pad it with a boot0 hook to insert 4 bytes of padding at the
start of the section (with the intention of having mkimage overwrite
this padding with the appropriate boot magic). This avoids having to
modify the linker scripts or more complex logic in mkimage.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-04-04 20:01:57 -06:00
Kever Yang
625ec503cb rockchip: rk3328: add evb-rk3328 support
evb-rk3328 is an evb from Rockchip based on rk3328 SoC:
- 2 USB2.0 Host port;
- 1 USB3.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;

Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-03-16 16:03:46 -06:00
Kever Yang
41793000d7 rockchip: rk3328: add clock driver
Add rk3328 clock driver and cru structure definition.

Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-03-16 16:03:46 -06:00
Kever Yang
85a3cfb80a rockchip: rk3328: add soc basic support
RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU.
It supports two USB2.0 EHCI ports. Other interfaces are very
much like RK3288, the DRAM are 32bit width address and support
address from 0 to 4GB-16MB range.

Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error:
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-03-16 16:03:46 -06:00
Kever Yang
66e87cc842 rockchip: config: rk3399: enable SPL config for evb-rk3399
Enable all the CONFIGs which need by SPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Drop CONFIG_ROCKCHIP_DWMMC for now due to build error:
Move changes to arch/arm/mach-rockchip/Kconfig to this patch:
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-03-16 16:03:46 -06:00
Kever Yang
3012a840ed rockchip: arm64: rk3399: add SPL support
Add SPL support for rk3399, default with of-platdata enabled.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Drop Kconfig changes to fix build error:
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-03-16 16:03:46 -06:00
Kever Yang
fa437430ad rockchip: arm64: rk3399: add ddr controller driver
RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from
coreboot, support 4GB lpddr3 in this version.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Added rockchip: tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-03-16 16:03:45 -06:00
Heiko Stübner
df9041ec72 rockchip: rk3188: Add main, spl and tpl boards
The rk3188 needs 3 U-Boot stages: a tpl living in 1KB of sram, a spl
the resides in the rest of the sram and loads the regular U-Boot living
in regular ram.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-03-16 16:03:45 -06:00
Heiko Stübner
3e747197b1 rockchip: rk3188: Add sdram driver
The sdram controller blocks are very similar to the rk3288 in utilizing
memory scheduler, Designware uPCTL and Designware PUBL blocks, only
limited to one bank instead of two.

There are some minimal differences when setting up the ram, so it gets
a separate driver for the rk3188 but reuses the driver structs, as there
is no need to define the same again.

More optimization can happen when the modelling of the controller parts
in the dts actually follow the hardware layout hopefully at some point
in the future.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-03-16 16:03:45 -06:00
Heiko Stübner
0a2be69fbf rockchip: rk3188: Add core support
Add the core architecture code for the rk3188.
It doesn't support the SPL yet, as because of some
unknown error it doesn't start yet.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Drop these defines from rk3188_common.h
   CONFIG_GENERIC_MMC, CONFIG_BOUNCE_BUFFER, CONFIG_DOS_PARTITION
   CONFIG_PARTITION_UUIDS, CONFIG_CMD_PART:
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-03-16 16:03:45 -06:00
Heiko Stübner
aade077e43 rockchip: Move bootrom-related declarations to a header
So far spl-boards have declared the back_to_brom() function as simple
extern in the files themself. That doesn't scale well if every boards
defines this on its own.
Therefore move the declarations to a bootrom header.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-03-16 16:03:44 -06:00
Heiko Stübner
1d845947a3 rockchip: Move bootrom helper compilation to a hidden option
Right now the ROCKCHIP_SPL_BACK_TO_BROM option both triggers
compilation of the bootrom hook-code as well as enabling the
behaviour of loading the full U-Boot via the boot.

New added socs may always need the bootrom code, while still
being able to decide between loading U-Boot regularly or via
the bootrom separately.

So move the compilation of the bootrom code to a hidden option
that gets selected by ROCKCHIP_SPL_BACK_TO_BROM, but can also
be selected by other parts.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-03-16 16:03:44 -06:00