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Author SHA1 Message Date
Yang Xiwen
e90711f0e9 arm: add support for Hisilicon HiSTB family SoCs
First supported chip is hi3798mv200 (which is similar to Hi3798cv200
used by poplar).

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
2023-05-03 09:05:24 -04:00
Michal Simek
f6aebdf676 arm64: versal-net: Add support for Versal NET platform
Versal NET platform is based on Versal chip which is reusing a lot of IPs.
For more information about new IPs please take a look at DT which describe
currently supported devices.
The patch is adding architecture and board support with soc detection
algorithm. Generic setting should be very similar to Versal but it will
likely diverge in longer run.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/320206853dc370ce290a4e7b6d0bb26b05206021.1663589964.git.michal.simek@amd.com
2022-09-26 14:23:29 +02:00
Peng Fan
2f5ee7f812 arm: makefile: cleanup mach-imx usage
All the SoCs use mach-imx has CONFIG_MACH_IMX selected, so
the macro could be the gate to build arch/arm/mach-imx to simplify
the rules.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:00 +02:00
Tom Rini
95cc3efcc1 arm: Remove strongarm support
There are no platforms using this architecture anymore, remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-08 17:57:33 -04:00
Tom Rini
a457ebd786 arm: Remove PXA architecture support
With the last platform for this architecture removed, remove the rest of
the architecture support as well.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-07 09:29:08 -04:00
Nick Hawkins
4276c9b2aa ARM: hpe: gxp: add core support
The GXP is the HPE BMC SoC that is used in the majority
of current generation HPE servers. Traditionally the asic will
last multiple generations of server before being replaced.

Info about SoC:

HPE GXP is the name of the HPE Soc. This SoC is used to implement many BMC
features at HPE. It supports ARMv7 architecture based on the Cortex A9
core. It is capable of using an AXI bus to whicha memory controller is
attached. It has multiple SPI interfaces to connect boot flash and BIOS
flash. It uses a 10/100/1000 MAC for network connectivity. It has multiple
i2c engines to drive connectivity with a host infrastructure. There
currently are no public specifications but this process is being worked.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
2022-06-22 21:30:04 -04:00
William Zhang
f8209d3051 arm: bcmbca: introduce the bcmbca architecture and 47622 SOC
This is the initial support for Broadcom's ARM-based 47622 SOC.

In this change, our first SOC is an armv7 platform called 47622. The
initial support includes a bare-bone implementation and dts with ARM
PL011 uart.

The SOC-specific code resides in arch/arm/mach-bcmbca/<soc> and board
related code is in board/broadcom/bcmba.

The u-boot image can be loaded from flash or network to the entry
point address in the memory and boot from there.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Kursad Oney <kursad.oney@broadcom.com>
Signed-off-by: Anand Gore <anand.gore@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-06-10 13:37:32 -04:00
Tom Rini
dc22afb975 spl: Remove CONFIG_SPL_START_S_PATH and rework the logic behind it
In some cases, when we don't use CONFIG_SPL_FRAMEWORK nor are we on
PowerPC using their specific SPL/TPL framework, we need to specify the
start.S file to use for these typically very constrained systems.  Do
this within the Makefile logic, rather than introducing a string-based
CONFIG option, as this would get slightly complex to do in Kconfig for a
very limited number of users.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:29 -04:00
Jim Liu
84335544ea arm: nuvoton: Add support for Nuvoton NPCM750 BMC
Add basic support for the Nuvoton NPCM750 EVB (Poleg).

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-05-05 09:28:47 -04:00
Mark Kettenis
003b657edc arm: apple: Add initial support for Apple's M1 SoC
Add support for Apple's M1 SoC that is used in "Apple Silicon"
Macs.  This builds a basic U-Boot that can be used as a payload
for the m1n1 boot loader being developed by the Asahi Linux
project.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Add MAINTAINERS entry]
2021-10-31 08:46:44 -04:00
Tom Rini
14b38cb0c2 arm: Remove flea3 board
This board has not been converted to CONFIG_DM by the deadline.
Remove it.  As this is the last mx35 platform, remove that support as
well.

Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2021-10-01 12:08:19 -04:00
Marek Vasut
270f8710f9 crc32: Add crc32 implementation using __builtin_aarch64_crc32b
ARMv8.0 has optional crc32 instruction for crc32 calculation. The
instruction is mandatory since ARMv8.1. The crc32 calculation is
faster using the dedicated instruction, e.g. 1.4 GHz iMX8MN gives:

  => time crc32 0x50000000 0x2000000
  time: 0.126 seconds # crc32 instruction
  time: 0.213 seconds # software crc32

Add implementation using the compiler builtin wrapper for the crc32
instruction and enable it by default, since we don't support any
platforms which do not implement this instruction.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
[trini: Make crc32_table guarded by CONFIG_ARM64_CRC32]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Peng Fan
9ef89ea9b0 arm: imx: basic i.MX8ULP support
Add basic i.MX8ULP support

For the MMU part, Using a simple way the calculate the MMU size to avoid
default heavy calcaulation. And align address and size in the table
settings to 2MB or 4GB as much as possible. So we can reduce the 4K page
allocations in MMU table which will spends much time in create the
page table

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:50 +02:00
Suneel Garapati
0a668f6d38 arm: octeontx2: Add support for OcteonTX2 SoC platforms
This patch adds support for all OcteonTX2 96xx/95xx
boards from Marvell.
For 96xx boards, use octeontx_96xx_defconfig and
for 95xx boards, use octeontx_95xx_defconfig.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
03c2288070 arm: octeontx: Add support for OcteonTX SoC platforms
This patch adds support for all OcteonTX 81xx/83xx
boards from Marvell.
For 81xx boards, use octeontx_81xx_defconfig and
for 83xx boards, use octeontx_83xx_defconfig.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
2020-08-25 08:01:16 +02:00
Stefan Bosch
95e9a8e2cb arm: add mach-nexell (all files except header files)
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- SPL not supported yet --> no spl-directory in arch/arm/mach-nexell.
  Appropriate line in Makefile removed.
- clock.c: 'section(".data")' added to declaration of clk_periphs[] and
  core_hz.
- Kconfig: Changes to have a structure like in mach-bcm283x/Kconfig,
  e.g. "config ..." entries moved from other Kconfig.
- timer.c: 'section(".data")' added to declaration of timestamp and
  lastdec.
- arch/arm/mach-nexell/serial.c removed because this is for the UARTs
  of the S5P6818 SoC which is not supported yet. S5P4418 UARTs are
  different, here the (existing) PL011-code is used.
- '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where
  possible (and similar).

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2020-07-29 08:43:40 -04:00
Robert Marko
e479a7d52e arm: Add support for Qualcomm IPQ40xx family
This introduces initial support for the popular Qualcomm
IPQ40x8 and IPQ40x9 WiSoC series.

IPQ40xx series have 4x Cortex A7 ARM-v7A cores.
Supported are: IPQ4018, IPQ4019, IPQ4028 and IPQ4029.

IPQ40x8 and IPQ40x9 use the same cores, but differ in
addressable RAM size (1GB for IPQ40x9 and 256MB for IPQ40x8)
and supported peripherals (IPQ40x8 lacks RGMII, LCD controller
and EMMC/SDHCI controllers).

IQP4028/IPQ4029 models differ from IPQ4018/IPQ4019 only
by their rated temperatures rates with IPQ402X models being
rated for wider temperature ranges.

Initially this supports:
* Simple clock driver (Only for UART1 now, will be extended)
* Pinctrl driver (Supports UARTX and GPIO now, will be extended)
* GPIOs already supported by msm_gpio driver with updates
* UARTs already supported by serial_msm driver with updates

Further peripherals will come in later patches.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
2020-07-29 08:43:40 -04:00
Trevor Woerner
71f6354b0e rename symbol: CONFIG_STM32 -> CONFIG_ARCH_STM32
Have this symbol follow the pattern of all other such symbols.

Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-15 14:47:35 -04:00
Trevor Woerner
18138ab203 rename symbol: CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
Have this symbol follow the pattern of all other such symbols.

Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-15 14:47:35 -04:00
Trevor Woerner
bb0fb4c0f4 rename symbol: CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
Have this symbol follow the pattern of all other such symbols.
This patch also removes a TODO from the code.

Reviewed-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-15 14:47:35 -04:00
Trevor Woerner
b16a331697 rename symbol: CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
Have this symbol follow the pattern of all other such symbols.
This patch removes a TODO from the code.

Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-15 14:47:35 -04:00
Trevor Woerner
9bffc54996 arch/arm/Makefile: sort machine names
The comment immediately above the block of machine directory names implored
users to keep the macro names sorted, but, alas, this is no longer the case.

Put the list of machine directory names back in alphanumerical order by
CONFIG_* macro name, as the comment asks. Sort all the symbols as though they
all followed the convention of having the string "ARCH_" in the middle of
their definitions.

Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-15 14:47:35 -04:00
Trevor Woerner
b3d9a8b185 arm: lpc32xx: move SoC to mach-lpc32xx
Following the example of most other SoCs in arch/$(ARCH)/cpu/$(CPU)/$(SOC)
move the lpc32xx code from arch/arm/cpu/arm926ejs/lpc32xx to
arch/arm/mach-lpc32xx.

Following the checklist from
commit 01f1445630 ("ARM: prepare for moving SoC sources into mach-*"):

    [1] move files from arch/arm/cpu/arm926ejs/lpc32xx to arch/arm/mach-lpx32xx
    [2] add machine entry to arch/arm/Makefile
    [3] remove "obj-y += ..." from arch/arm/cpu/arm926ejs/Makefile
    [4] fix the Kconfig file path in arch/arm/Kconfig
    [5] (no MAINTAINERS update)

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-15 14:47:35 -04:00
Stephan Gerhold
689088f9da arm: Add support for ST-Ericsson U8500 SoC
The NovaThor U8500 SoC was released by ST-Ericsson in 2011.
It was used for some development boards like the CALAO Systems
Snowball SBC, but mass production was primarily for Android
smartphones like the Samsung Galaxy S III mini.

Previous support for U8500 was removed in
commit 68282f55b8 ("arm: Remove unused ST-Ericsson u8500 arch")
since none of the boards were converted to generic boards
before the deadline.

The new code does not have much in common with the previous code.
I have completely rewritten everything, embracing the Driver Model
and device trees wherever possible.

The U8500 support is a bit more minimal for now - my primary
use case is to use U-Boot as alternative bootloader for some of the
U8500 Samsung smartphones. At the moment U-Boot is chain-loaded from
the original Samsung bootloader. A side effect of this is that we
can (temporarily) get away without implementing some functionality
- e.g. all clocks are already enabled by the original bootloader.

More functionality will be added in future patches.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: John Rigby <john.rigby@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-22 17:47:57 -05:00
Giulio Benetti
77eb9a90dd imx: Add basic support for the NXP IMXRT10xx SoC family
Add i.IMXRT family basic support.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14 22:54:00 +01:00
Heinrich Schuchardt
0c5c3f2935 arm: -march=armv5t for ARM11
In GCC 9 support for the Armv5 and Armv5E architectures (which have no
known implementations) has been removed, cf.
https://gcc.gnu.org/gcc-9/changes.html

Commit 16540d07fd ("arm: fix -march for ARM11") changed the value of the
compiler flag from -march=armv5 and -march=armv5t into -march=armv6 for
ARM11.

The values prior to this patch were:

    arch-$(CONFIG_CPU_ARM1136)     =-march=armv5
    arch-$(CONFIG_CPU_ARM1176)     =-march=armv5t

The change lead to a regression with the Raspberry Pi Zero W not booting
anymore.

Use -march=armv5t both for ARM1136 and ARM1176.

Fixes: 16540d07fd ("arm: fix -march for ARM11")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Joris Offouga <offougajoris@gmail.com>
2019-12-09 10:36:00 -05:00
Heinrich Schuchardt
16540d07fd arm: fix -march for ARM11
In GCC 9 support for the Armv5 and Armv5E architectures (which have no
known implementations) has been removed, cf.
https://gcc.gnu.org/gcc-9/changes.html

ARM11 is an armv6 implementation. So change the architecture flag for the
compiler to armv6 for ARM11.

Suggested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-11-23 14:53:48 -05:00
Peng Fan
c1e0940f7c arm: imx: build mach-imx for i.MX8
To enable SPL for i.MX8, we could reuse code in arch/arm/mach-imx.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Michal Simek
274ccb5b11 arm64: zynqmp: Move SoC sources to mach-zynqmp
Similar changes was done for Zynq in past and this patch just follow
this pattern to separate cpu code from SoC code.

Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/*
And also fix references to these files.

Based on
"ARM: zynq: move SoC sources to mach-zynq"
(sha1: 0107f24036)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:44 +01:00
Peng Fan
cd357ad112 imx: rename mx8m,MX8M to imx8m,IMX8M
Rename mx8m,MX8M to imx8m,IMX8M

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jon Nettleton <jon@solid-run.com>
2019-01-01 14:12:18 +01:00
Ryder Lee
cbd2fba1ec arm: MediaTek: add basic support for MT7629 boards
This adds a general board file based on MT7629 SoCs from MediaTek.

Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:50 -05:00
Tom Rini
cf033e04da Merged imx8 architecture, fix build for imx8 + warnings
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Merge tag 'u-boot-imx-20181025' of git://git.denx.de/u-boot-imx

Merged imx8 architecture, fix build for imx8 + warnings
2018-10-25 10:16:21 -04:00
Peng Fan
a6bba0bd00 arm: build mach-imx for i.MX8
Build mach-imx for i.MX8

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Michal Simek
ec48b6c991 arm64: versal: Add support for new Xilinx Versal ACAPs
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency.

The patch is adding necessary infrastructure in place without enabling
platform which is done in separate patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:21 +02:00
Lokesh Vutla
586bde93eb arm: K3: Add initial support for TI's K3 generation of SoCs
Add support for Texas Instruments' K3 Generation Processor
families.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-09-11 08:32:55 -04:00
Adam Ford
de39dc7162 arm: armv7-a: Compile and tune for armv7-a instead of armv5
arch/arm/Makefile references armv5 for backwards compatibility with
older compilers.  This patch removes those references to armv5,
since by now newer compilers are required which should have armv7
support enabled.

The Makefile also also has a list of options for mtune, but the
entry for CONFIG_CPU_V7A is empty, so this patch tunes the
CPU_V7A architecture to generic-armv7-a.

The following size changed apply to omap3_logic using GCC.

Stock
text data bss dec hex filename
50910 429 67580 118919 1d087 spl/u-boot-spl
540713 22700 327072 890485   d9675 u-boot

Without Armv5
text data bss dec hex filename
50916 429 67580 118925   1d08d spl/u-boot-spl
540719 22700 327064 890483   d9673 u-boot

mtune=generic-armv7-a
text data bss dec hex filename
50932 429 67580 118941   1d09d spl/u-boot-spl
540519 22700 327080 890299   d95bb u-boot

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-09-10 20:48:16 -04:00
Thomas Fitzsimmons
894c3ad27f board: arm: Add support for Broadcom BCM7445
Add support for loading U-Boot on the Broadcom 7445 SoC.  This port
assumes Broadcom's BOLT bootloader is acting as the second stage
bootloader, and U-Boot is acting as the third stage bootloader, loaded
as an ELF program by BOLT.

Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
2018-07-10 16:55:57 -04:00
Manivannan Sadhasivam
97775d26c2 arm: Add support for Actions Semi OWL SoC family
This commit adds Actions Semi OWL SoC family support with S900 as the
first target SoC.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-07-09 15:25:15 -04:00
Tom Rini
ea37f0b312 arm: armv7m: Clean up some thumb / compiler flag options
- The correct way to build with thumb mode is to select SYS_THUMB_BUILD
- We should be setting -march=armv7-m in arch/arm/Makefile not the
  sub-config.mk file.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-23 13:03:42 -04:00
Michal Simek
1d6c54ecb3 arm: zynqmp: Add ZynqMP minimal R5 support
Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
This patch is adding minimal support to get U-Boot boot.
U-Boot on R5 runs out of DDR with default configuration that's why
DDR needs to be partitioned if there is something else running on arm64.
Console is done via Cadence uart driver and the first Cadence Triple
Timer Counter is used for time.

This configuration with uart1 was tested on zcu100-revC.

U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200)

Model: Xilinx ZynqMP R5
DRAM:  512 MiB
WARNING: Caches not enabled
MMC:
In:    serial@ff010000
Out:   serial@ff010000
Err:   serial@ff010000
Net:   Net Initialization Skipped
No ethernet found.
ZynqMP r5>

There are two ways how to run this on ZynqMP.
1. Run from ZynqMP arm64
tftpb 20000000 u-boot-r5.elf
setenv autostart no && bootelf -p 20000000
cpu 4 disable && cpu 4 release 10000000 lockstep
or
cpu 4 disable && cpu 4 release 10000000 split

2. Load via jtag when directly to R5

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:38:23 +02:00
Michal Simek
4bbd6b1d94 arm: v7R: Add initial support
The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded,
real-time systems. It implements the ARMv7-R architecture, and includes
Thumb-2 technology for optimum code density and processing throughput.

Except for MPU(Memory Protection Unit) and few CP15 registers, most of the
features are compatible with v7 architecture. So,reuse the same armv7
folder and introduce a new config CPU_V7R in order to differentiate
from v7 based platforms.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-05-07 15:53:28 -04:00
Lokesh Vutla
acf1500138 arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A
Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under
armv7 folder. This led to a misconception of creating separate folders
for armv7m and armv7r. There is no reason to create separate folder for
other armv7 based architectures when it can co-exist with few Kconfig
symbols.

As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later
separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and
can co exist in the same folder.

Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Suggested-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-05-07 15:53:24 -04:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Patrick Delaunay
2514c2d0e6 arm: stm32: add new architecture for STM32MP family
- add new arch stm32mp for STM32 MPU/Soc based on Cortex A
- support for stm32mp157 SOC
- SPL is used as first boot stage loader
- using driver model for all the drivers, even in SPL
- all security feature are deactivated (ETZC and TZC)
- reused STM32 MCU drivers when it is possible

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-19 16:14:21 -04:00
Peng Fan
7a7391fd7e imx: add i.MX8M into Kconfig
Add i.MX8M into Kconfig, create a new folder mx8m
dedicated for i.MX8M.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2018-02-04 12:00:58 +01:00
Stefano Babic
552a848e4f imx: reorganize IMX code as other SOCs
Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/<SOC>.

This change is also coherent with the structure in kernel.

Signed-off-by: Stefano Babic <sbabic@denx.de>

CC: Fabio Estevam <fabio.estevam@nxp.com>
CC: Akshay Bhat <akshaybhat@timesys.com>
CC: Ken Lin <Ken.Lin@advantech.com.tw>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Heiko Schocher <hs@denx.de>
CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com>
CC: Christian Gmeiner <christian.gmeiner@gmail.com>
CC: Stefan Roese <sr@denx.de>
CC: Patrick Bruenn <p.bruenn@beckhoff.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Nikita Kiryanov <nikita@compulab.co.il>
CC: Otavio Salvador <otavio@ossystems.com.br>
CC: "Eric Bénard" <eric@eukrea.com>
CC: Jagan Teki <jagan@amarulasolutions.com>
CC: Ye Li <ye.li@nxp.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Adrian Alonso <adrian.alonso@nxp.com>
CC: Alison Wang <b18965@freescale.com>
CC: Tim Harvey <tharvey@gateworks.com>
CC: Martin Donnelly <martin.donnelly@ge.com>
CC: Marcin Niestroj <m.niestroj@grinn-global.com>
CC: Lukasz Majewski <lukma@denx.de>
CC: Adam Ford <aford173@gmail.com>
CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr>
CC: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Soeren Moch <smoch@web.de>
CC: Richard Hu <richard.hu@technexion.com>
CC: Wig Cheng <wig.cheng@technexion.com>
CC: Vanessa Maegima <vanessa.maegima@nxp.com>
CC: Max Krummenacher <max.krummenacher@toradex.com>
CC: Stefan Agner <stefan.agner@toradex.com>
CC: Markus Niebel <Markus.Niebel@tq-group.com>
CC: Breno Lima <breno.lima@nxp.com>
CC: Francesco Montefoschi <francesco.montefoschi@udoo.org>
CC: Jaehoon Chung <jh80.chung@samsung.com>
CC: Scott Wood <oss@buserror.net>
CC: Joe Hershberger <joe.hershberger@ni.com>
CC: Anatolij Gustschin <agust@denx.de>
CC: Simon Glass <sjg@chromium.org>
CC: "Andrew F. Davis" <afd@ti.com>
CC: "Łukasz Majewski" <l.majewski@samsung.com>
CC: Patrice Chotard <patrice.chotard@st.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Hans de Goede <hdegoede@redhat.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Stephen Warren <swarren@nvidia.com>
CC: Andre Przywara <andre.przywara@arm.com>
CC: "Álvaro Fernández Rojas" <noltari@gmail.com>
CC: York Sun <york.sun@nxp.com>
CC: Xiaoliang Yang <xiaoliang.yang@nxp.com>
CC: Chen-Yu Tsai <wens@csie.org>
CC: George McCollister <george.mccollister@gmail.com>
CC: Sven Ebenfeld <sven.ebenfeld@gmail.com>
CC: Filip Brozovic <fbrozovic@gmail.com>
CC: Petr Kulhavy <brain@jikos.cz>
CC: Eric Nelson <eric@nelint.com>
CC: Bai Ping <ping.bai@nxp.com>
CC: Anson Huang <Anson.Huang@nxp.com>
CC: Sanchayan Maity <maitysanchayan@gmail.com>
CC: Lokesh Vutla <lokeshvutla@ti.com>
CC: Patrick Delaunay <patrick.delaunay@st.com>
CC: Gary Bisson <gary.bisson@boundarydevices.com>
CC: Alexander Graf <agraf@suse.de>
CC: u-boot@lists.denx.de
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-07-12 10:17:44 +02:00
Masahiro Yamada
a93fbf4a78 ARM: omap2+: rename config to ARCH_OMAP2PLUS and consolidate Kconfig
In Linux, CONFIG_ARCH_OMAP2PLUS is used for OMAP2 or later SoCs.
Rename CONFIG_ARCH_OMAP2 to CONFIG_ARCH_OMAP2PLUS to follow this
naming.

Move the OMAP2+ board/SoC choice down to mach-omap2/Kconfig to slim
down the arch/arm/Kconfig level.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-04-27 16:49:08 -04:00
Peng Fan
1b409828b1 imx: mx7ulp: Add soc level initialization codes and functions
Implement soc level functions to get cpu rev, reset cause, enable cache,
etc. We will disable the wdog and init clocks in s_init at very early u-boot
phase.

Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev
is hard coded to a fixed value. This may change in future.

Reuse some code in imx-common.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2017-03-17 09:27:08 +01:00
Tom Rini
43ade93bdb Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2017-02-01 16:34:25 -05:00
maxims@google.com
4697abea62 aspeed: Add drivers common to all Aspeed SoCs
Add support for Watchdog Timer, which is compatible with AST2400 and
AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver
does not follow the driver model. It also uses fixed clock, so no clock
driver is needed.

Add support for timer for Aspeed ast2400/ast2500 devices.
The driver actually controls several devices, but because all devices
share the same Control Register, it is somewhat difficult to completely
decouple them. Since only one timer is needed at the moment, this should
be OK. The timer uses fixed clock, so does not rely on a clock driver.

Add sysreset driver, which uses watchdog timer to do resets and particular
watchdog device to use is hardcoded (0)
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-28 14:04:27 -05:00